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2023-09-01mb/msi/ms7d25: Configure ASPM and Clock PM based on KconfigMichał Żygowski
Add support for FSP ASPM and Clock PM configuration based on Kconfig options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01amd/soc/common: Use relative offset for AMDFWZheng Bao
The amdfw.rom is mostly in region COREBOOT. Calculate the relative address as the CBFS module address. That is for future 32M flash size support. TEST=binary identical test on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst This commit is part of a series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: I2add8e4e6755e582b3be6a150cf83d1468f2f1be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72961 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-01vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84Subrata Banik
Update header files for FSP for Meteor Lake platform from 3292.83 to 3323.84. The patch changess only a few spacing alignment for FSP-M header and added few PPR (Post Package Repair) related variable for MemInfoHob header. BUG=b:297965979 TEST=Able to build and boot google/rex. Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-31mb/google/dedede/var/pirika: Add FW_CONFIG probe for EXT_VRDaniel_Peng
Add FW_CONFIG probe for absent FIVR bypass mode on peezer. BUG=b:296982082 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-31crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1Elyes Haouas
Change-Id: I1fb3630bf5e8a56ddcf6102faffde568134accc9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77375 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-31util/crossgcc: Update binutils from 2.40 to 2.41Elyes Haouas
Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-31util/crossgcc: Update GMP from 6.2.1 to 6.3.0Elyes Haouas
Change-Id: I67d443cb15d89482b20b01f4068502b16ac8fc8e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-31abuild:skyrim: Remove the setting for AMD FW base in configsZheng Bao
Change-Id: I56e0501b511866b8ccc200b55620f87883e12067 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-31mb/google/rex/var/karis: Update GPIO settings for NC pinsTyler Wang
According to the schematic, set below GPIO to NC: 1. GPP_C18 2. GPP_C19 3. GPP_S04 4. GPP_S05 BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: If1f847d2db83b63a351203f0449cc1368bef27f4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77558 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-31soc/amd/common/data_fabric: add support for extended MMIO addressesFelix Held
The Genoa SoC supports MMIO addresses larger than 48 bits. Since the MMIO base and limit registers in the data fabric only contain bits 16 to 47 of the MMIO address, the MMIO address extension register is introduced on some SoCs like Genoa. This additional register contains the upper bits of the MMIO base and limit. Since it's not available on all SoCs, introduce the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO Kconfig option to select the correct data_fabric_get_mmio_base_size implementation to be added to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic304f5797bc5661c1d511c95e457c6dde169d329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77514 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-08-31mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO listAnil Kumar
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:279173035 TEST=If CONFIG_UGOP_EARLY_GRAPHICS is set to y, check SOL text on HDMI during Pre-RAM boot stage. Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-31mb/google/rex: Enable Fast V-Mode for MTL-U 15WSubrata Banik
This patch sets the Fast V-Mode (FVM) configuration parameter as suggested in Intel doc 640982. As per the doc, Intel MTL-U 15W CPU supports FVM on IA and SA. Fast V-Mode (FVM): Intel Meteor Lake introduces the ability to manage the peak power events it calls "reactive peak power management". The Fast V-Mode is one such technique to perform the reactive peak power management. It relies on the detector integrated inside the processor which senses when the processor load current exceeds a present threshold by monitoring the processor power domain IMVP (Intel Mobile Voltage Positioning) VR sense point. The baseline ITRIP for IA is 66A and 21A for SA. BUG=b:286809233 TEST=Able to build and boot google/rex without seeing any performance regression. Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75763 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30haswell NRI: Collect SPD infoAngel Pons
Collect SPD data from DIMMs and memory-down, and find the common supported settings. Original-Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a Original-Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I7948554eb02113bdca380222a11cfb322f9615f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-30tests/lib: Add unit tests for ux_locales_get_text()Hsuan Ting Chen
Add unit tests for ux_locales_get_text() in lib/ux_locales.c. BUG=b:264666392, b:289995591 BRANCH=brya TEST=make tests/lib/ux_locales-test TEST=Make sure ux_locales.c has 100% test coverage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I4d73419c02478870942828d324c258ef0eaa983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-30ec/starlabs/merlin: Unconditionally enable the Keyboard BacklightSean Rhodes
KBL_STATE was originally intended to provide more granular control of the keyboard backlight. However, KBL_BRIGHTNESS has a valid value of "off" which achieves the same thing. Therefore, unconditionally set the KBL_STATE to enabled, and rely on KBL_BRIGHTNESS. Change-Id: Ic7ee6b96b1dcaa6633b111e92097bce87908885e Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77201 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30amdfwtool: Print more information when debug mode is setZheng Bao
Change-Id: I08187c339ebbe84b183f3c6e53f0eea540620fbf Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-30soc/intel/meteorlake: Allow to override Fast VmodeJay Patel
This patch adds option to override Fast Vmode on Meteor Lake SoC. This requires CepEnable, EnableFastVmode, IccLimit FSPM UPDs in FSP header. If the hardware supports Fast Vmode, the FSPM will set the ICC limit value to the value passed from coreboot. With CepEnable and EnableFastVmode enabled, if IccLimit is not specified by coreboot, FSPM sets IccLimit as default value. If no values assigned to all the three CepEnable, EnableFastVmode and IccLimit, coreboot sets their values to 0 and Fast Vmode is disabled. BUG=b:286809233 TEST=In debug MTL FSP logs, the value of FSP parameters is as passed from coreboot including enable_fast_vmode, cep_enable, and fast_vmode_i_trip. Also, fast_vmode_i_trip value is passed to pcode using mailbox command without any error. This test done on google/rex board. Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: Id05dccac56c504523f9327babe0c6fbeff488ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75566 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-30mb/google/rex/var/karis: Remove USB cameraTyler Wang
Karis use MIPI camera only, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I96316d63c068c48b5bec75d3b4c5444d15fd985f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77510 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/karis: Remove SAR sensorTyler Wang
According to the schematic, karis does not have a SAR sensor. Update GPIO settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ib3b66b9594f2d0fddbbfc56e99f06b6587487f2a Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-30mb/google/rex/var/karis: Set GPP_D04 to NCTyler Wang
Follow schematic, set GPP_D04 to NC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie222a2773ff7d2b87641f55b4d37ff3bdf761cd2 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/screebo: Enable GL9750 invert WP functionKun Liu
enable GL9750 invert WP function BRANCH=none BUG=b:297244291 TEST=emerge-rex coreboot Change-Id: I7fdc94b5ca6b316ee0291c38e39c5f8b08cbc127 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77414 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30drivers/genesyslogic/gl9750: Add invert write protect polarityBen Chuang
Add an option to invert write protect polarity for GL9750. Change-Id: I5761f3066291a2400caecbecc79ae893f0a0c146 Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77403 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29soc/amd/common/data_fabric/Makefile: remove invalid commentFelix Held
The !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE comment was likely a copy-paste leftover, so remove it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45b12d1dc5af84be99d54fea0c9ccf610cf5dae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-29Revert "soc/intel/meteorlake: Generate new TME key on each warm boot"Subrata Banik
This reverts commit 5013c60a871af8fbce8c38a1c342c454e5b8452f. Reason for revert: consecutive reboots are causing kernel panic. BUG=b:297153853 TEST=Able to perform 50 cycles of consecutive reboot after reverting this CL and it boots to the OS every single time(w/o any kernel panic). Change-Id: If6c96dcc62c706a522b98a1cf1dd1920ad6473a1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77467 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29drv/intel/fsp2_0: Add FW Splash Screen event log entriesSubrata Banik
This patch adds logic for logging the FW splash screen event to the event log. There could be three possible scenarios as below: 1. Platform w/o FW splash screen (i.e., either HAVE_FSP_LOGO_SUPPORT or BMP_LOGO configs not enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) not present in the event log. 39 | 2023-08-27 12:42:54-0700 | System boot | 12 40 | 2023-08-27 12:42:54-0700 | ACPI Wake | S5 41 | 2023-08-27 12:42:54-0700 | Wake Source | Power Button | 0 2. Platform w/ FW splash screen (i.e., both HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs are enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is enabled in the event log. 34 | 2023-08-27 12:07:29-0700 | System boot | 11 35 | 2023-08-27 12:07:29-0700 | Firmware Splash Screen | Enabled 36 | 2023-08-27 12:07:31-0700 | ACPI Wake | S5 37 | 2023-08-27 12:07:31-0700 | Wake Source | Power Button | 0 3. Failed to render FW splash screen (due to any reason if FSP failed to render the splash screen) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is disabled in the event log. 43 | 2023-08-27 13:06:10-0700 | System boot | 13 44 | 2023-08-27 13:06:10-0700 | Firmware Splash Screen | Disabled 45 | 2023-08-27 13:06:11-0700 | ACPI Wake | S5 46 | 2023-08-27 13:06:11-0700 | Wake Source | Power Button | 0 BUG=b:284799726 TEST=Verify that the event shows up in the event log when the user selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display the firmware splash screen. Change-Id: Ie9e09acff5443c31b881c300134bc0bb06c490c6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-29util/cbfstool: Add eventLog support for ELOG_TYPE_FW_SPLASH_SCREENSubrata Banik
This patch adds support for logging the firmware splash screen event to the event log. There could be two possible scenarios for this event: enabled and disabled. BUG=b:284799726 TEST=Verify that the event shows up in the event log when the user selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display the firmware splash screen. Change-Id: I1e224903df21159d6eef2849a7d6fb05de09f543 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-29commonlib: Add ELOG_TYPE_FW_SPLASH_SCREEN eventLogSubrata Banik
This patch adds a new eventLog type ELOG_TYPE_FW_SPLASH_SCREEN to support logging when we show firmware splash screen to the user. BUG=b:284799726 TEST=Event shows in eventlog when user selects BMP_LOGO and HAVE_FSP_LOGO_SUPPORT configs. Change-Id: Id1572ecb83ca025ff65608e7ae4f3a065024f6d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77507 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28src/device/dram/Makefile.inc: specify one file per lineSergii Dmytruk
A trivial follow-up on CB:67060. This makes contents of the file look a bit less regular, but more like the rest Makefile.inc in the code base. Change-Id: I772d37825e4b59cf927637dc39bfb3ee06115860 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77533 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28payloads/libpayload: Don't use old style function definitionElyes Haouas
Use "int foo(void)" instead of old-style "int foo()". Change-Id: Ic698dbbba74d579a21ff57005a7aa9bb8ce80253 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28util/msrtool: Don't use old style function definitionElyes Haouas
Use "int foo(void)" instead of old-style "int foo()". Change-Id: Ieb151c2db1c0ee9222dbacccae78ca725bdcde08 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77498 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28util/coreboot-configurator: Don't use old style function definitionElyes Haouas
Use "int foo(void)" instead of old-style "int foo()". Change-Id: I19869ce2f47b543af4552ea23ce1fd1beea2f892 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77497 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28util/inteltool: Don't use old style function definitionElyes Haouas
Use "int foo(void)" instead of old-style "int foo()". Change-Id: I609c0332132389c07b03db40dc48dc94ca836a56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28Revert "mb/google/brya: fix MRC cache failure for hynix parts"Nick Vaccaro
This change causes a freeze during boot on an RPL-UR that does not have the memory part string in the CBI. BUG=b:296353047 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot problematic DUT to kernel. This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365. Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28mb/google/rex/var/rex0: Enable BT offload audio for Intel MtP2 moduleAnil Kumar
Enable the required GPIO and FW_CONFIG support to configure BT offload audio in discrete mode for Intel Mysty Peak module on google/rex Proto2 HW. BUG=b:297125514 Test=Verified BT audio playback on google/rex Proto2. Change-Id: I560f1700f78f8b653dfcc2f26764f0ebf2652689 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77357 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-28drivers/spi/spi-generic: Fix typoElyes Haouas
'useable' -> 'usable'. Change-Id: Iad2e1ef97a5c98ffa6f33806bce5b77722e687e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28arch/x86/cpu: Remove unnecessary parenthesesElyes Haouas
Change-Id: I157a3a700ed998b1012c85857c5fad78f60d62dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77525 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/spi/tpm: Remove space between function name and '('Elyes Haouas
Change-Id: I9804fcd9076b5a4813f099db0852a5af5ac36609 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77523 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/lenovo/wacom: Remove space between function name and '('Elyes Haouas
Change-Id: Idc38c759489976cbdf51d9c4bb950ef6d470b93a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-28drivers/intel/gma: Remove space between function name and '('Elyes Haouas
Change-Id: Id7634099e40c0bf97944be124b494c41d6335ad7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28libpayload: Fix clang fallthrough warningArthur Heymans
Clang does not recognize comments to indicate falltrough is intended behavior. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idcf7a24fc763b80863902702172b4ea950e132b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77431 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-28util/xcompile: Fix libpayload compilation with clang/llvmArthur Heymans
x86 assembly code uses a lot of nested macros so increase the default value from 20 to 1000. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic23c452514de7dc1aa420541b756c443180b8b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77430 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28mb/google/rex/var/karis: Remove UWBTyler Wang
According to the schematic, karis does not have a UWB, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I8a442518c2007cde883183871cef96db416850c0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-27util/kconfig: Update toada to halt on errorsMartin Roth
The tool 'toada' which converts the Kconfig output to ada syntax keeps running even when it can't parse something. Change that behavior to halt, and update the error message to show where the error is coming from. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I29807a054581060d04b9ecbe02f2ba666c46bcf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-27util/kconfig: Allow toada to handle negative integersMartin Roth
Any builds using ADA were getting a message saying: `couldn't parse value '-1' for 'SEABIOS_DEBUG_LEVEL'` This change allows toada to parse negative integers. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6507c54976b67f1ad70846b6bd6c54c861130d3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77421 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-27Docs/acronyms.md: Fix build warnings & update some linksMartin Roth
- Change all links to wikipedia to https. - Update some links to wikipedia that were incomplete. - Update a few links that are now broken. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If780e15997c499d1df975b436fd9af530f324eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/77488 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-27doc/mainboard/index: Deduplicate menu points for T530 and W530Felix Singer
Both mainboards have the same documentation. Instead of having two list items referring to the same document, just merge the two items. This fixes the following Sphinx warning: WARNING: duplicated entry found in toctree: mainboard/lenovo/w530 Change-Id: I4140b34db01b1d5f47a39b9c1e33405e7789de63 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77503 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-27doc/mb/asus/{p2b-ls,p3b-f}: Remove reference to non-existing documentFelix Singer
The document for northbridge/intel/i440bx doesn't exist and it didn't exist at the time of introduction of these two mainboard documents. So replace the reference with just the northbridge name. This fixes the following Sphinx warning: WARNING: unknown document: '../../northbridge/intel/i440bx/index' Change-Id: Iaa67399f9d0e62d5d54ae08f5ebb8c70073c601f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-27doc,util: Regenerate documentation filesFelix Singer
Add new documentation generated by util/util_readme/util_readme.sh. This also fixes the following Sphinx warning: util/abuild/index.md: WARNING: document isn't included in any toctree Change-Id: I26c33af3c5a5853f6bcce23e982a6b192b01f1d7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-27doc/releases/4.22: Remove transitions from sectionsFelix Singer
Sections may not start with transitions. Remove them. This fixes the following Sphinx error: ERROR: Document or section may not begin with a transition. Change-Id: I519af83df14e44b0709dee7e338dba1ee6413f0a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77440 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-27acpi/acpi.h: Use __packed over __attribute__((packed))Elyes Haouas
Change-Id: Iabbb637c797a361a2cbc55505002774ff4f774e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77526 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issueJeremy Soller
Clevo started using OZ711LV2 for the SD card reader around the time of making its TGL boards. Without the driver, CPUs don't go to power states lower than C2 due to LTR not being programmed. After enabling the driver the CPU will go to C8 while the system is idle, giving significant power savings if the system is left on battery power. There is another issue with RPL where it only goes to C6 instead of C8. This may be due to the intel_idle driver in Linux (as of 6.5-rc6 mainline and 6.4.6 stable) not supporting RPL C-states. - tgl: Started being used with the Gazelle 3060 variant - adl: Used on all models - rpl: bonw15 does not have an SD card reader Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/amd: Move psp_transfer.h out of each SOC into commonMartin Roth
The psp_transfer.h file was the same under all SoCs, and is really tied to the file common/vboot/transfer.c, not the SOC. This patch makes an include directory under vboot to put the header into and sets it to be included for all SoCs using SOC_AMD_COMMON. This makes the header file available to all platforms, so that new chips that don't use the psp_verstage don't have to make a psp_transfer.h file just to satisfy the compiler. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b9f2adee3a1d4d8d32813ec0a850344b7d717b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77303 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/amd/pi: Add SPDX headers to all files that don't have themMartin Roth
License classifiers are much better about classifying files with SPDX headers than they are at classifying the general text licenses due to minor variations in the text. To help with classification, add the SPDX headers to the files. To see the current state of coreboot's licensing, see: https://coreboot.org/fossology/ Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If490f6705e7862d9ad02c925104113b355434101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-26soc/intel/common/block/oc_wdt: Add OC watchdog common blockMichał Żygowski
Add new block for handling overclocking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the microarchitectures utilizing intelblocks. The patch adds the common block for initializing and feeding the watchdog. Timeout is defined statically in Kconfig and should be set high enough by the board or SoC Kconfig to let the board boot with full memory training and avoid reset loops. Full training of 128GB DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs with newer memory technologies and higher RAM capacity may take more. The default has been set to 10 minutes. The patch also adds support for feeding watchdog in driverless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/rex/var/karis: memory: Add Micron MT62F512M32D2DR-031Tyler Wang
Add new memory part in the mem_parts_used.txt and generate the SPD ID. 1. MICRON MT62F512M32D2DR-031 WT:B BUG=b:291018417 TEST=emerge-rex coreboot Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/dedede/var/taranza: Add Wifi SAR for taranzaSheng-Liang Pan
BUG=b:297276380 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Cq-Depend: chrome-internal:6373154 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-08-26mb/google/rex/var/karis: Remove WWAN moduleTyler Wang
According to the schematic, karis does not have a WWAN module, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vendorcode/intel/edk2: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR tableSubrata Banik
This patch changes the SAR table selection logic to use FW_CONFIG which will eventually help to support different WiFi SAR tables. TEST=Able to build and boot google/rex. Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de Signed-off-by: YH Lin <yueherngl@google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/intel: Remove unnecessary Kconfig optionsMartin Roth
These Kconfig options were being used basically as #define statements, which is unnecessary. This isn't a good use of Kconfig options and would be better just as #defines if actually needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-26vc/siemens: Only add the include path for hwlib when neededMartin Roth
This patch moves the line adding hwlib to the include path to the inner makefile so that it doesn't get added to every build, but only when CONFIG_USE_SIEMENS_HWILIB=y Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id668b76366a554efff560cec746e637487ebdbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26vc/amd: Only pull in Makefiles & dirs that are neededMartin Roth
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled into the build when they aren't needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26vc/eltan: Only pull in vc/eltan/security Makefile when enabledMartin Roth
This change tells the build to only pull vc/eltan/security/Makefile.inc into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-26mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_configWisley Chen
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. BUG=b:296511904, b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified by EE Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26configs: Remove configs for unsupported boardsFelix Singer
Scaleway Tagada was removed with commit c013fa6234 and Intel Galileo was removed with commit 037c25d4dd. So remove their configs. Change-Id: I1c491f437b8a1104bdf31a34e3c7d2c4e5794301 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77415 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26soc/intel/meteorlake: Add PMC GPIO GPE group mappingCliff Huang
Add two missing mapping for GPIO GPE routes Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26libpayload: Skip unknown arguments to clangArthur Heymans
This compiler argument only exists on gcc. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I10902517c86daedc9853e6f6cac8fcf513211bb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77436 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26libpayload: Remove unnecessary bracketsArthur Heymans
This fixes compilation with clang. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I675056c8a15fe446bba81a144bfea64d106df293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77435 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26libpayload: Fix untyped function argumentsArthur Heymans
This is necessary with clang. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icc197fbd48b49bfa8770caf01727669b0ac59090 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-26docs: Tidy up the English in the testing tutorialSimon Glass
Tweak a few sentences noticed when reading this. BUG=none BRANCH=none TEST=none Change-Id: I0a072c83402bc551a6bbdb7cd7c55fc3505784b2 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77464 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: Patrick Georgi <patrick@coreboot.org>
2023-08-26docs: Mention add_intermediate and provide an exampleSimon Glass
This is a useful feature, so add a note about it. Change-Id: If29f6480f878bdaf877dc208cc4861b884e10840 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77465 Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-26payloads/U-Boot: Use github mirror and latest versionSimon Glass
Update the U-Boot version to the latest release. Also switch to github since it is typically much faster to download than the existing URL. Drop the 'experimental' tag since this payload is pretty stable. It is also tested regularly in U-Boot's CI. Change-Id: I082130539c3474593a82e4b21cb995380f4db168 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77149 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77463 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-26memrange: Honor `limit` in the last step of top-down stealingNico Huber
We only checked that the resource fits below the given `limit` in memranges_find_entry(), but then accidentally placed it at the top of the found memrange. As most resources have only a coarse limit, e.g. the 4G barrier of 32-bit space, this became only visible when artificially setting an unusual, lower limit on a resource. So, for the final placement, use `MIN(limit, range end)` instead of the range's end alone. Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-25mb/google/brask/var/kuldax: Set customized_leds value for RTL8111KDavid Wu
Set customized_leds value for RTL8111K to fix led can't work. BUG=b:297093096 BRANCH=firmware-brya-14505.B TEST=Verified RTL8125 and RTL8111K led can work normally. Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brya: Create nokris variantChen-Tsung Hsieh
Create the nokris variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:285838647 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOKRIS Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35 Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-25util/cbfstool: Add eventlog support for PSR data backup statusKrishna Prasad Bhat
In order to support logging of events for PSR data backup command status during CSE firmware downgrade, add support for ELOG_TYPE_PSR_DATA_BACKUP and ELOG_TYPE_PSR_DATA_LOST types. BRANCH=None BUG=b:273207144 TEST=Verify event shows in eventlog after CSE firmware downgrade Change-Id: Ibb78ac8d420bb7a64328ce009ddcb99030519ec6 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77005 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2023-08-25commonlib: Add PSR backup eventlog typesKrishna Prasad Bhat
Add new eventlog types to support logging of Platform Service Record (PSR) backup related messages. Eventlog entries are added on PSR data backup success/failure and also when PSR data is lost. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/rex/var/ovis: Update PWM_BUZZER GPIO configJakub Czapiga
BUG=b:271491845 TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08 Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25soc/intel/apollolake: Correct the logic for the legacy 8254 timerSean Rhodes
The `use_8254` should be flipped, the same as the other Intel SOCs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-25mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIGMark Hsieh
Joxer will have SKUs with no type-c on daughter board, add fw_config for EC control it. BUG=b:297131468 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25MAINTAINERS: Add Nicholas Chin for coreDOOM payload integrationNicholas Chin
Change-Id: Idd3acd204c0809753b6f5534790e1dc81c10b761 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71859 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/amd/birman: Enable two USB4 xHCI controller devicesAnand Vaikar
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command 00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0 00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1 Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-25payloads/external/LinuxBoot: Fix bootPatrick Rudolph
Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286 "payloads/external/LinuxBoot: Clean up". Include the initrd into the payload. Allows to actually use LinuxBoot. Change-Id: I5ab6b1a43a4100e83f4c188b9ea3451ab7b4ffe5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77412 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25soc/amd/common/include/root_complex: add IOHC MISC SMN base addressesFelix Held
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile SoCs have, so add the additional 3 SMN base address definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checksFelix Singer
When LZMA compression is selected, then it's not needed to check if LZ4 compression is selected in addition. So instead of handling both cases separately, check for LZ4 only if LZMA is not selected. This applies to the cases of both, FSP-M and FSP-S. Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-25mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio tableTyler Wang
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage gpio table. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/rex/var/karis: Fix incorrect GPIO pad numbersKapil Porwal
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of GPP_F14, GPP_F15 and GPP_F16 GPIOs. BUG=none TEST=none Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24Makefile: Fix typo in `make help` outputNico Huber
Change-Id: I124e7d68198050616795a67df23b6481f6fe1276 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77407 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24docs: Redirect top-level make targets to Documentation/Nico Huber
To avoid redundancy about how to call into `Makefile.sphinx`, only do that from the `Documentation/Makefile` and call into that from the top level. Change-Id: I99c462cdaf83d711e4b7c07b713d304274db8cb4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-24Kconfig: Add option to make clang the default compilerArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24docs/mb: update hp/compaq_elite_8300_usdt docsRiku Viitanen
- Internal flashing possible - Fix link - Link here from the list of mainboards - More consistent naming Change-Id: Iaf6448c1e9f0dae9480fa9785a12f09d42f8cf7d Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77377 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/hp/compaq_elite_8300_usdt: enable mSATARiku Viitanen
Tested with a Kingston UV500. It works the same (3Gb/s) as with vendor FW. According to smartctl -a /dev/sda: SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s) Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24mb/siemens/fa_ehl: Remove RTC RV3028C7Johannes Hahn
Delete this RTC from the configuration as fa_ehl mainboard uses a different real time clock. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove TPMJohannes Hahn
The mainboard currently does not make use of a dedicated TPM. Although it has one assembled. This TPM is not connected via LPC hence it is turned off in the devicetree. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove NC_FPGAJohannes Hahn
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA as it is not placed on this board. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24Makefile: Update build for include-what-you-useMartin Roth
This patch saves the output of the IWYU build into $(obj)/iwyu.txt. It will also automatically adds -k to the MAKEFLAFGS when IWYU is selected, so that the build doesn't halt after the first operation. When IWYU is not selected, there is no change to the build. This will allow us to create an automated IWYU build on jenkins. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0ea300d4c64bb923e9f7cc0e595885c3006ec3ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77192 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-24mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED configStanley Wu
Enable bit 9 for 100M mode green LED blink. Reference: - RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration BUG=b:293983804 TEST=emerge-dedede coreboot and verify LAN LED behavior Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-24mb/google/nissa/var/yaviks: rename DB_NONE to DB_1AWisley Chen
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko. BUG=b:294928078, b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Icb952c0716d446d5feb5580f357120a27193284e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24libpayload: Outsource delay function into own headerThomas Heijligen
For libflashrom we need the delay functions but when including the whole libpayload.h it has conflicting symbols. Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 18:22:10 +0000