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2022-03-04soc/mediatek/mt8195: Update header version from 1.8.1 to 1.9.1Ryan Chuang
Move some structures to common folder (CB:61293), so we need to update header version. BUG=none TEST=dram calibration pass Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-04soc/mediatek/mt8192: Update header version from 1.7.1 to 1.8.1Ryan Chuang
Move some structures to common folder (CB:61293), so we need to update header version for this. BUG=none TEST=dram calibration pass Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I8cf12f4967af116eaef88c1f688567f1da9fa6e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-03mb/google/zork: fix SMMSTORE size, alignment in default FMAPMatt DeVillier
SMMSTORE needs to have 64k size (minimum) and have 64k alignment as enforced by asserts added in commit 1ba6049 [drivers/smmstore/store.c: Add static assertion based on fmap]. Adjust size and alignment of SMMSTORE region in FMAP to ensure those conditions are met. Test: build google/morphius without asserts being tripped for above conditions. Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03mb/google/brya/var/nivviks: Configure WCAM DMIC data pinReka Norman
GPP_S6 was accidentally configured twice instead of configuring GPP_S7. So configure GPP_S7 according to the schematics. BUG=b:222218450 TEST=WCAM DMIC works on nivviks Change-Id: I5de36aaa504a8856803c783564162c36416b50b7 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62511 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03mb/google/glados: Drop TPM PIRQMatt DeVillier
The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ; Linux only works with 'tpm.tis_interrupts=0" and Windows fails to init the TPM citing a lack of available resources. With the PIRQ removed, both Linux and Windows are happy / the TPM is available for use. Test: build/boot Linux 5.16.x and Windows 11 on google/chell Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-03mb/google/brya: Change "mainboard: EC init" loglevel prefixIan Feng
Change loglevel prefix "BIOS_ERR" to "BIOS_DEBUG". BUG=b:220639445 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ie3de63fc13e7a5ed6a4b4617542851782fbb6f00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62508 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03soc/amd/*/northbridge,root_complex: add comment about PCI BARsFelix Held
Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource indexFelix Held
In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify mmconf_resource indexFelix Held
In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vbootJakub Czapiga
TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload cflags to make them build correctly without requiring payloads to provide defines. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-03drivers/{pcie,wifi}/generic: Update untrusted property nameTim Wawrzynczak
In order to align with established standards for establishing DMA boundaries[1] from ACPI, the UntrustedDevice property has been renamed to DmaProperty, which follows Microsoft's implementation. After discussions with Microsoft, they have agreed to make the `UID` property optional, so it is left out here, and instead it can be applied to: 1) Internal PCI devices 2) PCIe root ports 3) Downstream PCI(e) devices [1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports BUG=b:215424986 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id70e916532e3d3d70305fc61473da28c702fc397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-03soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entriesFelix Held
Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Stoneyridge with the other AMD SoCs. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=None, but equivalent change on Picasso was verified to not break anything on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries callFelix Held
Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03ec/starlabs/merlin: Don't report a battery capacity higher than design capacitySean Rhodes
If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design Capacity), only report the design capacity. This handles cases where the battery calibration is incorrect, and the battery runs out before the OS thinks it's empty. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-03mb/google/brya/var/vell: Change to ELAN touchpanel driverShon Wang
Disabled G2touch driver and add ELAN touchpanel driver for vell. Due to incorrect BIOS setting, touch screen IC FW can't update and work. According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10 BUG=b:221340736 TEST=emerge-brya coreboot and can flash touch screen FW Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2022-03-02soc/amd/common/vboot: Verify location of CBMEMC transfer bufferRaul E Rangel
Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02mb/google/brya/var/kinox: update gpio settingsDtrain Hsu
Configure GPIOs according to schematics BUG=b:218786363 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemcRaul E Rangel
We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/vboot: Split transfer buffer methods into separate fileRaul E Rangel
I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resumeRaul E Rangel
We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02acpi/acpi: drop weak cpu_get_lapic_addr implementationFelix Held
All SoCs/chipsets that select ARCH_X86 will end up using the implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the unused weak implementation that returns a different value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-02mb/siemens/mc_ehl: Disable HS400 mode for eMMCWerner Zeh
In order to achieve a stable eMMC interface disable the HS400 capability of the host controller. This will result in an operating mode of maximum HS200 (200 MHz single data rate) which leads to a more relaxed timing. Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-03-02Documentation/mainboard: Add QEMU POWER9 to index siteFelix Singer
The QEMU POWER9 target is supported since coreboot version 4.15. Documentation is available in the tree, but it's not referenced from the mainboard index page. Fix that. Change-Id: Ic3b98735840c146cb0bfb122df0e6f762c2beeca Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-02Documentation: Fix spelling of "QEMU"Felix Singer
Fix spelling and use the one from their website qemu.org. Change-Id: I36a88985ce3a7c59b732c1ca3198d86a591de6bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-02Documentation/mainboard: Add Supermicro X9SAE to index siteFelix Singer
The Supermicro X9SAE target is supported since coreboot version 4.15. Documentation is available in the tree, but it's not referenced from the mainboard index page. Fix that. Change-Id: I5d3d0b5b935f1a3ea353a3d9e39208db7c7895ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-02Documentation: Fix spelling of "Supermicro"Felix Singer
Fix the spelling and use the one from their website supermicro.com Change-Id: Id630d9d130082fb38f9151e0dfb6f6fbb5a2789d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-02device/pci_device.c: Improve pci_bridge_route() readabilityArthur Heymans
Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-02soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz testRex-BC Chen
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from default value 0x88 to 0xC0 for MT8186. We also add a new log message to show the capid value which is read from MT6366. This implementation is according to chapter 5.13 in MT8186 Functional Specification. BUG=b:218439447 TEST=set capid to 0xc0. TEST=XTAL 26MHz test passed. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02soc/mediatek: remove unused RTC_GPIO_USER_MASKRex-BC Chen
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02mb/google/brya: enable the SPD_CACHE_ENABLEZhuohao Lee
google/brask is using SODIMMs for DRAM. Reading spd data is surprisingly slow (~170 ms), therefore enable the SPD cache. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=run on the device and measure the boot time decrease. Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02mb/google/brya/variants: add the smbus addr for dimm1Zhuohao Lee
Align the setting with the adlrvp BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and works correctly in the brask Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02util/docker/coreboot-jenkins-node: Alphabetize installed toolsMartin Roth
It's easier to read and to add new packages when each package is on its own line and they're sorted alphabetically. Indenting them also makes it easier to see what's getting installed and what's a command. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02util/docker/coreboot-jenkins-node: add linkcheckerMartin Roth
The linkchecker tool is now being used to find broken links in our websites. Since it's not needed for building anything, just add it to the jenkins-node Dockerfile instead. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02mb/google/brya/var/vell: Remove Rcomp settingsGaggery Tsai
This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02mb/google/brya/var/primus{4es}: modify GPP_B3 as unlockedCasper Chang
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. Also set GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power on sequence. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-01soc/amd/common/fsp/fsp_validate.c: print warning instead of errorJulian Schroeder
If an AMD FSP binary has no valid image revision information, print a warning instead of an error. Change-Id: Ie9c5a387b81205fe93382778090260e41e261776 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01mb/amd/chausie: Always enable developer modeRaul E Rangel
Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01security/tpm: Add vendor-specific tis functions to read/write TPM regsTim Wawrzynczak
In order to abstract bus-specific logic from TPM logic, the prototype for two vendor-specific tis functions are added in this patch. tis_vendor_read() can be used to read directly from TPM registers, and tis_vendor_write() can be used to write directly to TPM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-01drivers/tpm/spi: Convert static functions to enum cb_err return typesTim Wawrzynczak
Instead of using raw integers to indicate success/failure, enum cb_err can be used to makes things clearer, so this patch converts most functions to return that instead of int. TEST=boot to OS on google/dratini, no TPM errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01mb/google/guybrush/var/nipperkin: update thermal settingKevin Chiu
Enable STT and decrease sustained_power_limit_mW to 12W BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-01intelblocks/cse: Skip sending EOP during S3 resumeMAULIK V VAGHELA
coreboot should skip sending EOP during S3 resume since CSE doesn't require EOP in resume path. Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage which doesn't get called during S3 resume. In case EOP is moved in earlier stage, coreboot might send EOP in S3 resume as well. This patch adds check before calling cse_send_eop. BUG=b:211085685 BRANCH=None TEST=Check by moving EOP to earlier stage. EOP sending is skipped during S3 resume. Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-01Documentation/mainboard: Move flashing instructions to common dirSean Rhodes
Move the instructions for flashing coreboot with fwupd to common directory as the process is identical across all models and variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I293acf962b32c81fdf482e0df15363e1cffa39bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-01mb/starlabs/lite: Add StarLite Mk IIISean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-01ec/starlabs/merlin: Remove unused keyboard.aslSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01ec/starlabs/merlin: Add spaces to adhere to coding styleSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e965513d5888398834cab8c8445e97372f2b115 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01mb/intel/adlrvp: Enable eMMC device for ADL-N RVPKrishna Prasad Bhat
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder Lake N RVP from devicetree. Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-01Update fsp submodule to upstream masterMartin Roth
Updating from commit id 10eae55: 2021-08-24 21:11:18 +0800 - (Elkhart Lake MR1 FSP) to commit id f4bbf5a: 2022-01-29 00:32:47 +0800 - (Apollo Lake MR10 FSP) This brings in 20 new commits: f4bbf5a Apollo Lake MR10 FSP aab8be0 Apollo Lake MR10 FSP 45b935f Apollo Lake MR10 FSP 755e782 Signed-off-by: Wong <swee.heng.wong@intel.com> da956c1 Whitley FSP 2.2.0.3A 7e3d894 Whitley FSP 2.2.0.3A 04ad3cd Tiger Lake - UP3 IoT FSP MR4 ccf7f35 Elkhart Lake MR2 FSP 4aa1275 Elkhart Lake MR2 FSP 8aa6a9a Cedar Island FSP 2.2.0.3A 2e2e740 Whitley FSP 2.2.0.3A 91a6117 Tiger Lake - UP3 IoT FSP MR3 2863499 Delete FspUpd.h df41c58 Delete FsptUpd.h 0d420eb Delete FspsUpd.h 53cc56a Delete FspmUpd.h ad51318 Tiger Lake - UP3 IoT FSP MR3 63273a4 Delete Fsp.fd ce61eb3 Tiger Lake - UP3 IoT FSP MR3 f7f77a2 Delete Fsp.bsf Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6128b9703498dd36be73c19cbbfe349c206c6cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-02-28lib/Makefile: Add ability to specify -ldflags for rmodulesRaul E Rangel
This will allow linker flag customization for rmodules. BUG=b:221231786 TEST=Build guybrush with patch train and verify ldflags are passed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28Makefile: Add a build target for .mapRaul E Rangel
We don't currently have a build target defined for .map files. This means they can't be used as a dependency. This change splits the .map creation into its own rule. BUG=b:221231786 TEST=Build guybrush and verify .map still exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1ce21902e97390aa9520670299ef08debf4458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/62399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28Makefile: Add .SECONDARYRaul E Rangel
We currently delete intermediate files. This can make it difficult to debug and is also unexpected. Setting .SECONDARY will prevent make from deleting the files. BUG=b:221231786 TEST=Build guybrush with CL stack and see .map files are preserved Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger
Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28Documentation: Fix broken link to Gerrit GuidelinesFelix Singer
Change-Id: I14084f95af122c160f287f0133017a769c249d00 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28soc/intel/common/block/acpi: Return existing Object for _DSM subfunctionTim Wawrzynczak
Currently the LPIT Get Constraints _DSM subfunction returns a package containing the path to a nonexistent device (\NULL). This is used to work around an issue with Windows, where returning an empty package will cause a BSOD. However, using this non-existent device can also cause confusion, as on Linux, it shows an error in dmesg, e.g. ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \NULL (20200925/dspkginit-438) Therefore, this patch modifies this returned package slightly to include the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on Intel platforms that use the PEP driver. Tested on google/brya0 on ChromeOS 5.10 kernel Tested with current Windows 11 ISO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
2022-02-28cpu/x86/smm: Support PARALLEL_MP with SMM_ASEGArthur Heymans
This will allow to migrate all platform to the parallel_mp init code and drop the old lapic_init code. Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28mb/google/brya/var/kano: add enable_off_delay_ms to 30David Wu
Kano changes load switch of touch screen to TPS22914C (is not with discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms to fix DUT can't enter S0ix issue. BUG=b:220811619 TEST=Boot kano to OS and run S0iX test 2500 cycles. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2022-02-28mb/google/skyrim: Enable PCIe devices in devicetreeJon Murphy
BUG=b:214414301 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Enable AP <-> D2 communicationJon Murphy
Configure D2 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for D2 device and enable the required config items. BUG=b:214414776 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28mb/google/skyrim: Add eSPI configurationJon Murphy
BUG=b:214413613 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add initial fch irq routingJon Murphy
BUG=b:214417045 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add initial I2C configurationJon Murphy
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:214414677 TEST=Build Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28mb/google/skyrim: Log mainboard events to elogJon Murphy
BUG=b:214414851 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28mb/google/skyrim: Add ACPI configuration for USB portsJon Murphy
The USB port configuration was derived from the PPR and schematics. This board has 6(some multi-purpose) ports. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras 1 Bluetooth transceiver BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28soc/amd/sabrina: Add XHCI configurationJon Murphy
Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28drivers/wwan/fm: Add support for _PTS for Fibocom 5G WWANCliff Huang
Add DPTS (device prepare to sleep) method that is to be called in mainboard's \_SB.MPTS, which is called in _PTS. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-28device/pci_device: Fix PCIe bridge detectionNico Huber
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(), it's our virtual `domain` device. Expecting a PCI device above bus 0 resulted in undefined behavior for all boards with PCI. Only boards with a PCI device 00:00.0 that looked like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake). Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe) Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28mb/google/brya/var/kano: Add wifi sar tableDavid Wu
1. Add wifi sar table for kano 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:214393458 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28sb/intel/lynxpoint: Fix up commentAngel Pons
Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-28mb/google/dedede/var/pirika: Add Wifi SAR for pasaraFrank Chu
Add wifi sar for pasara BUG=b:216411442 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-27Documentation/releases/index: Clean up documentFelix Singer
There is no reason to use lists to link the checklist and template document. Thus, link to these documents in their related flowing text. Change-Id: I9bce0dd6595f1a208e7ea2311a653f9af32530de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62412 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27Documentation/releases: Move upcoming release section to the topFelix Singer
The list of releases will grow and in the current state each release moves the section for the upcoming release more down making it less visible. Thus, switch both sections, so that the documentation for the upcoming release is at the top. Also, invert the order of the previous releases, so that the latest is at the top. Change-Id: I69987e035f38ae3ca14dbf5c7644d5292106a978 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62411 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27Documentation/releases: Move checklist and template to upcoming sectionFelix Singer
The documents for the checklist and template are related to upcoming releases. Thus, move them to the section for upcoming releases. Change-Id: Ibe6be506d2833036105b7c86445dca2a6efb7a55 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62410 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27Documentation: Rename release notes document titleFelix Singer
The release notes document also contains information about upcoming releases, not only previous releases. Thus, rename the document in the main menu and give it a proper title. Change-Id: I4480c0b6e4be6fcbcb9a00beb0be169a7eed435d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-27Documentation: Move Gerrit Guidelines to "Contributing" sectionFelix Singer
The Gerrit Guidelines are related to the contributing process and also contain documentation which goes beyond "Getting started". Thus, move them to the "Contributing" section. Change-Id: I775a79c14562a1f4a9563012aee3b690c0635cc1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-27utils/cbfstool: Fix building with `make test-tools`Felix Singer
The variable `RM` is empty and thus set it to `rm`. While executing the `clean` rule, run each `rm` command with the -f flag to ignore non-existing files. Also, disable the objutil feature locally fixing another build issue. Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27util/testing: Add cbfstool tools to tested utilsMartin Roth
Previously, cbfstool was tested as part of the coreboot build, but not tested individually. This let a change that broke elogtool slip through. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-26Documentation/mainboard/ti: Fix Markdown linksFelix Singer
Change-Id: I08351beccb5174494855eee32bccfbcef77b8346 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62385 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26Revert "util/cbfstool: Port elogtool to libflashrom"Martin Roth
This reverts commit d74b8d9c990780ba64515b36aaff79d719d71ead. This change breaks the 'make all' build of the cbfstool tools from the util/cbfstool directory unless libflashrom-dev is installed, complaining that flashrom is not installed. Even with libflashrom-dev installed, it breaks building elogtool with the public version of libflashrom-dev. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy
BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable internal graphicsJon Murphy
BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26mb/google/skyrim: Enable console UARTJon Murphy
BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: Set up FW_CONFIGJon Murphy
BUG=b:214415048 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable eSPI SCI eventsJon Murphy
Enable ESPI SCI events BUG=b:214416630 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Add smihandlerJon Murphy
BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable Chrome ECJon Murphy
BUG=b:214413613 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable variants for SkyrimJon Murphy
BUG=b:214414033 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26mb/google/skyrim: CONFIG_CHROMEOSJon Murphy
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26mb/google/skyrim: Enable ACPI tablesJon Murphy
Add GPIO initialization and ACPI generation for tables BUG=b:214415303 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik
This fixes no practical problem, especially for coreboot where only one process should access the SPI controller. It makes the code look more spec compliant. As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. Software must initiate the next SPI transaction when this bit is 0. Add non-blocking mechanism with `5sec` timeout to report back error if current SPI transaction is failing due to on-going SPI access. BUG=b:215255210 TEST=Able to boot brya and verified SPI read/write is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-26soc/amd/common/psp_verstage: Add missing post codes on S0i3 resumeRaul E Rangel
We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel
This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-25Docs/releases: Final update for 4.16 release notes before the releaseMartin Roth
- Remove arrows from google mainboard as requested in the last review. - Make Feb25 the release date. - Cosmetic markdown changes - Rewrapping, updated for lines' lengths. - Add plan to support Resource allocator V3 on the 4.18 branch. - Add plan to deprecate LEGACY_SMP_INIT after 4.18 release Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id16925918511fd2277a54faeccfa56e96c6aaae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62380 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/google/brask: Update PCH power cycle related durationsZhuohao Lee
The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25payloads/tianocore: Convert BMP at build timeSean Rhodes
Convert BMP to the correct format at build time, which removes the requirement for any runtime checks. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f1e9c8df2ca7d66f362f9fa5688d6cb443c2581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-02-25payloads/tianocore: Pass SD_MMC_TIMEOUT build optionSean Rhodes
By default, edk2 allows 1000000μs for SD Card Readers and eMMC to initialize which is excessive and causes a boot delay. This makes the value configurable and uses a default of 1000μs which is sufficient for the majority of readers. The value of 1000μs was hardcoded in MrChromeBox's fork for around 2 years with no reported issues. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I873bcddf6f37a9eaae5c84991b3996d51fb460d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-25mb/intel/adlrvp: Add support for MAX98373 codecUsha P
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macroElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>