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2018-06-04mb/jetway: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/intel: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/iei: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I750ec788b7526ee2a7aa803bffb93805cedfb2ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/ibase: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I8e21843e11498438e115f1f82f94f2944ae7a3c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/hp: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I3f85e2ef0682b808f6e99dc406bccb88badcb82c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/google: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/gizmosphere: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Iacbd72e1c60573f4bb5ffa40717141e9fbca01bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/gigabyte: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/getac: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ib7068f381971d1270b22cb03937f1e7fa30acb46 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/foxconn: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0a4b7d774db1b2b486f44bd7363555c15d464484 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/esd: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I0458e4fe08e32daf0b880e0a29752297e8159fe6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/elmex: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I085a5b7dca252943590a30c1afe6ad776dac6c97 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/cubietech: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I299c579c996da4e0e9fa1fc4d8b40706356509f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/biostar: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I15c34c65fba22c297cd26c2ee23bcf5e7b56e233 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/bap: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I8999f1603014b558a9efd3823614020ba0ecce82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/bachmann: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2022100f7d1d7b7f2667e45efc8cea074b424b65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/avalue: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2c3e44e1f7ad7dd14f62fd99fd48c485ec74b3cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/asus: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/asrock: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ie1e319375ab0f5565805557b15e0bf821dfb223e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/aopen: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I05d938add5aabe2557a5d915a54a920e7ba9f50f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mb/advansus: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I6a3df8074d874cc5f4e1ff45c422c685cc90dbb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04mainboard/adi: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I2c2e00cef28414d6beff1e37539977ee4c6e5088 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/mainboard: Add space after 'if'Elyes HAOUAS
Change-Id: Icae1983be6b8c5aebb121be8a383e2613e064122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04src/console: Fix coding styleElyes HAOUAS
Change-Id: I57724262ade87e7907d31ea66e4f1b9c382ef3db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04sb/amd/rs780: Fix invalid function declarationsKyösti Mälkki
Provide empty stub implementations for set_pcie_reset() and set_pcie_dereset(), many boards do not provide a proper one. Change-Id: Ia6811442905ef1776fa5a8e3f5d4433e86e42f88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04sb/amd/sr5650: Fix invalid function declarationsKyösti Mälkki
Change-Id: I5034debc2296352e698898c20910a2d76071e30a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04amdfam10: Fix mismatch of function declarationsKyösti Mälkki
Callsite declared returning int, which makes more sense than u8 the motherboard side code defined the functions with. Change-Id: I8ee83aa2833408ad163c9011a076e08578f3ca6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04amdfam10: Fix function declaration to staticKyösti Mälkki
Change-Id: Ifb73f51d34e179ff95b2b1e3ab28adc21717f9ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04drivers/generic/ioapic/ioapic.c: Remove unneeded includeElyes HAOUAS
Change-Id: I670702f092e49bac8d7733d6fa77861e28e09093 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04arch/x86: Remove unneeded includesElyes HAOUAS
Change-Id: I0b87e2b36a282c773e5f2f4a96c23aeadecb1300 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04src/lib: Remove unneeded 'console.h' includeElyes HAOUAS
Change-Id: Ibdda3dc52f5b61077f91f4cffb4f86b2955aab74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04sb/intel/common/spi.c: Add a SPI write protect functionArthur Heymans
Could be useful to write protect regions like for instance the MRC_CACHE region. Tested on Intel DG41WV (i82801gx) and Lenovo Thinkpad X220 (bd82x6x) to write protect the mrc_cache region. Change-Id: Id0a9a0de639c5d6761a77a56ceba6d89110a4ea1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04device: Only expose VGA_ROM_RUN on supported architecturesPatrick Rudolph
The yabel emulator depends on IO ports, that aren't available on ARM and MIPS. Add additional dependencies to fix compilation errors with the default configuration. Change-Id: If0e28b356c01cb3ae0739a54aa3531a2acedbfbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26754 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04cpu/x86/mp: Update CPU name in device structureNaresh G Solanki
Name the CPU device structure as per processor brand string. Before logs use to look like: APIC: 01 (unknown) Now logs looks like(depending on CPU on which it is tested): APIC: 01 (Intel(R) Core(TM) m3-7Y30 CPU @ 1.00GHz) BUG=None BRANCH=None TEST= Build & boot Soraka. Change-Id: I6af0e29bbbdb59406baeae32f7874ff9036a9c81 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04cpu/x86/mtrr.h: Clean up some guardsNico Huber
Move #includes to the top and remove unnecessary guards. Hopefully this prevents future surprises. Change-Id: Id4571c46a0c05a080b2b1cfec64b4eda07d793bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04arch/x86: Introduce postcar_frame_add_romcache()Nico Huber
Provide a common implementation to add an MTRR entry for memory- mapped boot ROMs. Change-Id: I9fabc6b87fb36dc3d970805eb804cd950b8849d4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04lib/cbfs: Optimise LZMA away from romstageKyösti Mälkki
If we have POSTCAR_STAGE there is no need for romstage to include LZMA decompression code. Reduces romstage by about 4 kiB on x86. Change-Id: I4c475986b2a94e5cd540c3eead433ed6c0a815ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-04Documentation/lessons/lesson1: Fix formattingPatrick Georgi
Change-Id: If4f13db2e56f1641a4e6a3069b744514e3279e3c Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04sb/intel/i82801gx: Remove unneeded includesElyes HAOUAS
Change-Id: Ibbb80cb28833131e3b02a8ff583d53c52ef2ca0f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04lib/coreboot_table.c: Remove unneeded includeElyes HAOUAS
Change-Id: I6e0d9e10d4f2ea224a19ef11481148f21d29857f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26795 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04nb/via/vx900: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I31143e1c7f1c52dec9673f75d73031632049ddbf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26529 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04src/console/vtxprintf.c: Remove unneeded 'console.h' includeElyes HAOUAS
Change-Id: I1d7caaf58b3119a9fff339df1159a6e3277fc2dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04src/commonlib/storage: Move include <console.h> to sd_mmc.hElyes HAOUAS
Non of the .c files is using a function from console.h directly. Include console.h is moved to sd_mmc.h, where sdhc_error("msg..") is defined. Change-Id: Ic9283f227a37785056b9fac216fabcac054066a0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26752 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/denverton_ns: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I15e624b40d11f61a3870a6083be82d062690498d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/skylake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26541 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04soc/intel/apollolake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id6bcf98892c1944ec9c7e637f63c4c05fe9a0c07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/braswell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/fsp_broadwell_de: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I68c455d4bc524c2dd2d3ba87ab6641e70c78521c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/fsp_baytrail: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04sb/intel/bd82x6x: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I05f23504148d934109814b8f3c1c2a334366496a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04util/inteltool: Add Pentium 4 model f6xElyes HAOUAS
Tested on Pentium 4, CPUID = 0F65 board: NEC 945G-M4. Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04util/msrtool: Add Pentium D supportElyes HAOUAS
CPUID F6x will not support all MSRs on intel_pentium4_later. Removed from pentium4_later and added as Pentium D. Change-Id: Ic6ac0593607b6f87fe921ac52738dad5ee3457dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-03buildgcc: Update IASL to 20180531Iru Cai
Change-Id: I6c14f3aad59749896816bb8789788fc513e7176f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-03soc/intel/apollolake: Add Page table mapping for System MemoryHannah Williams
Since we do not know before hand the memory range initialized by FSP memory init until it completes and as memory gets accessed from within FSP memory init to migrate FSP from CAR to memory, we need to add this mapping in coreboot. Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/26745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-03mb/google/kahlee: Remove #include <soc/smi.h>Richard Spiegel
Because of struct sci_source table of events that have to generate SCI or SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin), and therefore smi.h is now included by gpio.h. It was also added to some other files where they are not needed. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26721 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mb/google/poppy/variants/nami: Load vayne VBT binaryIvy Jian
Load vbt-vayne.bin by reading sku-id. BUG=b:80509366 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: Ia26ea4a9b7679aeb9d98f19ffaa1b686af828339 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-03pcengines/apu1: align with apu{2,3,4,5} lowercase namingPiotr Król
This change may require board_mismatch=force if mainline firmware was used. If vendor firmware was used this patch remove flashrom confusion since system product name reported by SMBIOS tables will match mainline firmware. Change-Id: Ic6942bc36df1a02db61b035ddc892585688aa27b Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26757 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mainboard/asus/am1i-a: turn on the tpmKevin Cody-Little
Along with other patches submitted for review to get the chipset parts working, this allows Linux or other OS to use a TPM module plugged into the 20-pin LPC header on the board, by exposing its presence through the ACPI and PNP tables. This patch adds to the Kconfig and devicetree.cb files. Tested with the TPM/FW 3.19 and the trousers tools. Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-02cpu/intel/car: Prepare for some POSTCAR_STAGE supportKyösti Mälkki
The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-02intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: Icc4cef468ede2c1db052850efd155b626e392dae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26744 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-02intel/e7505: Assume AGP slot disabledKyösti Mälkki
Reducing two AGP aperture windows from default 256 MiB to chipset minimum 4 MiB releases 504 MiB of unused MMIO space. Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB. Supported CPUs are 32-bit with PAE, so there is a little reason to avoid overlarge MMIO region. Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02intel/e7505: Fix domain resourcesKyösti Mälkki
Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02util/lint: Update lint-000-license-headers linterMartin Roth
- Add some directories and files to the ignore list - Add the LGPL as a recognized header. It's used in some files that were pulled into coreboot from other sources. Change-Id: I53423205f1cbf142a294ee5d24e885741a44dfcd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02src/mainboard: Add and update license headersMartin Roth
This change adds and updates headers in all of the mainboard files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all mainboard directories. Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ modeAamir Bohra
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-06-01console: Fix regression on LATE_CBMEM_INITKyösti Mälkki
Fix regression after commit 6032018 console: only allow console messages after initialization Fix it so that the two remaining platforms that are being moved to EARLY_CBMEM_INIT have chance to send board-status with non-dirty tags before and after the conversion is made. This also leaves us with a record in the repository where LATE_CBMEM_INIT was known to work on some platform. Change-Id: Ie874f986a2c474bba117d7d6ae959decec8060a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26743 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/nautilus: Add "rotation" controljimlai
The driver only supports streaming images flipped horizontally and vertically. In order to ensure that all current users will be fine if or when support for upright streaming is added, require the presence of the "rotation" control now. BUG=None BRANCH=None TEST=Verified the MIPI and USB camera function on DUT board Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792 Signed-off-by: Lai, Jim <jim.lai@intel.com> Reviewed-on: https://review.coreboot.org/26727 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01src/cpu: Remove unneeded includesElyes HAOUAS
Change-Id: I8fb03ada29b37f96fb02122462dfb8ec7faa9d31 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-01soc/intel/cannonlake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26584 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01soc/intel/broadwell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26583 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01util/lint: use a more compact output formatPatrick Georgi
It now looks like this: Check that files have license headers (lint-stable-000-license-headers): success Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success Check that C labels begin at start-of-line (lint-stable-004-style-labels): success Change-Id: I9d1f6adebae5b68a51e89c2833f8713f0ffcb616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-01mb/google/octopus: Enable RT5682 headset codec for BIP boardNaveen Manohar
Patch adds required changes for RT5682 codec enablement for the BIP board. And code clean-up nhlt blob selection method in config. BUG=b:77892150 TEST=build and boot on a BIP PO board. verify headset codec i2cdetects at address 1a. Change-Id: Iee91518c03a0e9e6ed52bc54a60fc607730a0b7d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/26211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-01drivers/intel/wifi: Add PCI ID for Intel TP2 Wi-FiFurquan Shaikh
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to pci_device_ids in Intel wifi driver. Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01mb/google/rambi: Set SMI mask using google_chromeec_events_initFurquan Shaikh
This change updates rambi ec init to perform SMI mask setting using google_chromeec_events_init. Change-Id: I7def3c07b4d7bfbe15b2d1c45381bdc31b7e3476 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01ec/google/chromeec: Initialize SMI mask in google_chromeec_events_initFurquan Shaikh
This change adds smi_events to google_chromeec_event_info and allows mainboards to set SMI mask if current boot type is not S3 wakeup. Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01superio/nuvoton/npcd378: Add PSU fan controlPatrick Rudolph
Implement method to access the SuperIO's harware monitor (HWM) IO space. Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option to all board that use NPCD378. In case no CMOS is set use the default fan level 3. The HWM space can be written to at any time, but the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied at once. Tested on HP Compaq 8200 SFF. Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01mb/google/fizz: Add USB port infoEmil Lundmark
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-06-01soc/amd/stoneyridge: Add ACPI device name lookupMarc Jones
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup function. BUG=b:80280671 TEST=Add ACPI method to specific GPP bridge. Boot and verify method with ACPI dump. Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/26698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-31util/lint: Add check that changes conform to clang-format stylePatrick Georgi
It's a white list (configured through $(top)/.clang-format-scope) with the expectation that the list will grow over time. Once everything is covered, we can turn off the white-listing and keep everything enforced. To not drive people crazy, only check the files their commit touched. Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-05-31libpayload-x86: Export keyboard modifiersPatrick Rudolph
Add function to get active keyboard modifiers. Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18601 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31libpayload: Export usbhid_getmodifiersPatrick Rudolph
Add a new method to retrieve active usb keyboard modifiers. Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18602 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31soc/intel/broadwell: decouple PEI memory struct from coreboot headerMatt DeVillier
Recent changes to field lengths in include/memory_info.h resulted in a mismatch between the memory_info struct the MRC blob writes to and the struct used by coreboot to parse out data for the SMBIOS tables. This mismatch caused type 17 SMBIOS tables to be filled incorrectly. The solution used here is to define the memory_info struct as expected by MRC in the pei_data header, and manually copy the data field by field into the coreboot memory_info struct, observing the more restrictive lengths for the two structs. Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly populated. Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/26598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31arch/x86/include/arch: Remove space after __attribute__Elyes HAOUAS
Change-Id: I7c74eff97580fbf39242f16dbdde98286678d596 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26321 Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31i210: Add additional PCI-ID to the i210 driverWerner Zeh
When the i210 MACPHY is operated in the SERDES Backplane mode (which depends on the programmed firmware image), its PCI-ID will be 0x1537. This does however not change the programming interface for the MAC address. Therefore add this new PCI-ID to the driver so that the MAC address can be programmed in this operation mode as well. Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/26683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31mb/google/poppy/variants/nocturne: configure the FPMCU interfaceVincent Palatin
The FPMCU is using the standard cros-ec-spi interface on GSPI1. Configure the GPIOs controlling the MCU too. We need to be able to wake from S3 on the MCU interrupt, re-configure GPE0 DW0 to point to GPP_C bank. BRANCH=poppy BUG=b:79666174 TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version', verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup' then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs with the flash_fp_mcu script. Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/26684 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiBNico Huber
Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000. So don't try to cache more than 16MiB of the ROM. It's also common that at most 16MiB are memory mapped. Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26567 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31soc/intel/skylake: Select common P2SB codeSubrata Banik
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB to include common p2sb code block. BUG=b:78109109 BRANCH=none TEST=Build and boot EVE. Change-Id: I3f6aa6398e409a05a35766fb7aeb3aa221dd3970 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26165 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31Remove VIA vt8237r southbridge supportKyösti Mälkki
Change-Id: I2d0400212d32c4dee71163d2f5919c290b8c0616 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove VIA C7 CPU supportKyösti Mälkki
Change-Id: Ib8c943e01ac293bdbf37f43ff72dbb636b46a8af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 12:39:26 +0000