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Metaknight has two daughter-board (DB_PORTS_1A_HDMI and
DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to
probe daughter-board to avoid USB device cannot recognize correctly.
BUG=b:184809456
TEST=build and verify USB device can recognize correctly
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch disables GSPI1 interface connected to fingerprint scanner since
no plans to enable FPS on Shadowmountain.
TEST=Verified on Shadowmountain
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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If the option is successfully read from CMOS, the code overwrites its
value with 3. Fix this issue and use the new get_int_option() function.
Change-Id: I287a348da6ece78376d9c38e96128041752b032e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Drop "error" (BIOS_DEBUG) messages as well.
Change-Id: I61954f8f893c144bbeba1530a486b389bd855ec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ia46b622c52f98d4cc5fb7d9b02e2aeb366ef3915
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I97fbbf2af76a6d4c44221000da7b36378e066ff3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I460cad0cc671be830d0fa0f68a531acaea7effcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Ibca7660ed03525903a1146a1fb2937550406bee8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Ie5cb54b171244be71848a59a788ed8d42b3e3161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: If75f307c862b24e9208568cdba0a0b05ab4009bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Icbfea8c516c42b45d689da92b7e426cb6d5112a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Ifd1f3969281e67d1a6ab7eb99dd048799c0cb17d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The {get,set}_option() functions are not type-safe: they take a pointer
to void, without an associated length/size. Moreover, cmos_get_option()
does not always fully initialise the destination value (it has no means
to know how large it is), which can cause issues if the caller does not
initialise the value beforehand.
The idea behind this patch series is to replace the current type-unsafe
API with a type-safe equivalent, and ultimately decouple the option API
from CMOS. This would allow using different storage mechanisms with the
same option system, maximising flexibility.
Most, if not all users of get_option() have a value to fall back to, in
case the option could not be read. Thus, get_int_option() takes a value
to fall back to, which avoids repeating the same logic on call-sites.
These new functions will be put to use in subsequent commits.
Change-Id: I6bbc51135216f34518cfd05c3dc90fb68404c1cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I28eb13edcded95a9a4c17bdf92da9f792883a613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The eint driver can be shared by multiple platforms so
we want to move it to common/.
BRANCH=asurada
TEST=emerge-asurada coreboot
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id8e0b631d5079e51213831ed17aa540e0afadd4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use existing functionality instead of reinventing it.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaeab5cce05ccd860bc8de3775b7d1420653497a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The name of the and_mask parameter was a bit misleading, due to the
function inverting the value. Renaming this into clear and set makes it
more obvious what those parameters will actually do.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If307ab4858541861e22f8ff24ed178d47ba70fe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We had the addrspace_32bit rdev in prog_loaders.c for a while to help
represent memory ranges as an rdev, and we've found it useful for a
couple of things that have nothing to do with program loading. This
patch moves the concept straight into commonlib/region.c so it is no
longer anchored in such a weird place, and easier to use in unit tests.
Also expand the concept to the whole address space (there's no real need
to restrict it to 32 bits in 64-bit environments) and introduce an
rdev_chain_mem() helper function to make it a bit easier to use. Replace
some direct uses of struct mem_region_device with this new API where it
seems to make sense.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Reuse `dev` pointer for SmbusEnable configuration and remove `smbus`
pointer.
Change-Id: I7ad7cdeb632eb52ae02b60ca51e7d4845dffdb0d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move the function declaration of parse_devicetree() out of the if-else
preprocessor condition.
Change-Id: I6974554711e4cc2bb944bff14fc057ef6945c888
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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parse_devicetree() just calls parse_devicetree_param(). To be aligned
with other platforms, remove it and rename parse_devicetree_param() to
parse_devicetree().
Change-Id: I1128ab709cfdb02bbdb505c3f22f5433a30cb3c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`devicetree.cb` is the default value for the Kconfig DEVICETREE
setting. Drop redundant configurations.
Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `chipset_lockdown` option defaults to `CHIPSET_LOCKDOWN_FSP` if
omitted. As most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`,
choose it here as well for consistency.
Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Fix board ID (HSI) read from BMC:
* R02 and R03 have an HSI of 2.
* R04 has an HSI of 3.
Change-Id: I987b2dd848c48e3562bcc07270c958cde3c5a962
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51920
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There was a bug in the UPDs for STAPM settings that required one UPD
field to be extended from 8 to 32 bits, so this patch is a breaking
change to the binary layout, but since the UPD struct fields for the SMU
SoC power and performance tuning parameters aren't populated by the
coreboot code yet and we added some padding after each logical section
in the UPD, this isn't expected to cause too much trouble; the only
thing that is required is that a very recent build of the FSP binaries
need to be used in combination with the new coreboot code that will
populate the struct fields in follow-up patches.
BUG=b:182297189
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This option is not mainboard-specific, and should be user-visible.
Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The uPEP device is required to support S0i3. The device has been written
in ASL to make it easier to read and maintain. The device constraints
are purely informational. We use a dummy constraint like the Intel
platforms to keep both linux and Windows functional.
In order for this device to be used by the linux kernel the
ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it
unconditionally doesn't cause any problems.
The AMD Modern Standby BIOS Implementation Guide defines two UUIDs,
one for getting the device constraints, and one for handling
notifications. This differs from the Intel specification and the linux
driver implementation. For this reason I haven't implemented any of the
notification callbacks yet.
BUG=b:178728116
TEST=Boot OS and verify _DSM is called:
[ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3
[ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful
[ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin:
[ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Intel 6-series PCHs, the GCAP register is R/WO (Read / Write Once),
and needs to be written to after the HD Audio controller is taken out
of reset. Add a Kconfig option to read and write back GCAP in order to
lock it down. Follow-up commits will select this option when switching
platforms to use common Azalia code, to preserve original behaviour.
Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This comment is most likely a copy-paste leftover from Braswell.
Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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To make the L140CU able to be selected by other OEMs, use
BOARD_CLEVO_L140CU_BASE for OEM independent options.
BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any
OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the
baseboard.
Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST#
BUG=b:182100027
TEST=ls /dev/nvme*
Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Found-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ic434c969141c67ce317a5db0c8805de02c84eb08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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The macro definitions depend on __SIMPLE_DEVICE__ and are only used in
the get_gpio_base() or lpc_get_pmbase() functions, which already guard
PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor.
Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I0d5fa4451b356970cf9843a76d0fa4d2af4307da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I2caa9cbb812e17f041c15654aef756e41fb71398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ie2f02b9934d843c29d17a72a6bf3b2bae91ce8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ic16fd74d4ddf96e29bcdada671dab0e590af74ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to
make clear that this option represents the baseboard.
Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.
Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I98d806ebf126522689b2c101b75add733825fcf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Hook up FSP-M configuration on mainboard level instead of variant level
being able to do common configuration there.
Also, hook up variant romstage.c on mainboard level for variant
specific configurations.
Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Add a new configuration low_power_probe to avoid camera privacy LED
blink during the boot.
Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52189
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to
set it here.
Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As v1 was dropped, rename v2.
Change-Id: I4dd51804e9391284c7624c42ad8180a14b1a4c84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I536a104428ae86e82977f2510b9e76715398b442
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use the same stack location during relocation as for the permanent
handler.
When the number of CPUs is too large the stacks during relocation
don't fit inside the default SMRAM segment at 0x30000. Currently the
code would just let the CPU stack base grow downwards outside of the
default SMM segment which would corrupt lower memory if S3 is
implemented.
Also update the comment on smm_module_setup_stub().
Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC
software sync needs to be enabled in payload once the EFS2 requirements
are met.
BUG=b:185277224
TEST=Build.
Cq-Depend: chromium:2829948
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit ad7c33abd21dfdde75c6ffa23c31cbe46826d2d5. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.
BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.
Cq-Depend: chromium:2832032
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I34f8433739754365c8e5a10fdf7e58e3d1e7e797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.
BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.
Cq-Depend: chromium:2832032
Change-Id: I921dc5c814e5187dce283eeff43075b59885723a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If we select scancode set #1 and keep that, it can confuse Linux
with keyboards that don't return to set #2 when asked to load the
defaults. This happens for instance with various integrated Think-
Pad keyboards but was also seen with an external PS/2 one.
The chosen configuration, scancode set #2 without translation, seems
to be the default for many systems. So we can expect other payloads
and kernels to work with it.
Change-Id: I28d74590e9f04d32bb2bbd461b67f15014f927ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of ignoring keyboards indefinitely when they failed to
initialize, we wait 5s and then start over with the hotplug
detection. As we always assume a present keyboard at first,
we'd otherwise never have a chance to hot plug a device after
the initial 30s timer ran out.
Change-Id: I8dec4921b2e932442d52b5118cdcf27090633498
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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While we assume a keyboard is attached, we send an echo command every
500ms. If there is no data coming from the keyboard within 200ms, we
assume it was detached.
Correspondingly, if we assume no keyboard is attached, we run an echo
command once per second.
Change-Id: I2c75182761729bf30711305f3d8b9d43eafad675
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4d7d9ca43316bf514bb5ebd8909f441bcfa20eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS
is selected, so non-ChromeOS targets use the default x86 FMAP.
Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Sync from guybrush.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The
concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has
a voltage rating of 3.3 V. The schematics has been updated to bridge the
gap. So enable the speaker amplifier by default and add a gpio override
table to disable the speakers before board version 2.
Also update the codec ACPI HID name for the kernel machine driver to
probe the codec successfully.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state
is high.
Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.
Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The selector component in Sound Open Firmware (SOF) can consume all the
mics and use the configuration in the Use Case Manager (UCM) to select
the right channel. Hence dmic select gpio configuration is optional.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the machine driver
ACPI object is populated without DMIC select GPIO.
Change-Id: Iba00b07c3656c487e33bab184fefee7037745e2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52393
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI_BERT_SIZE is used in the FSP driver and the fsp_m_params.c. The
latter one is planned to be deprecated though.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1a250defbd31e255df9b7a7dd8488dc3182649b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.
This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.
This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO config based on review of latest schematics:
- LAN/WLAN reset lines are NC
- SDIO lines configured via GPP_G0-G7
- DMIC lines are wired directly to codec, not PCH, so GPP_D17-20
are set to NC
- Pads GPP_H0-H3 are configured for I2S2
- Pads GPP_H7-H9 are straps for board revision, so treated as GPI
- CPU_C10_GATE# is NC
- PWRBTN# does not need an internal pull-up
- GPP_C20-23 are configured for M.2 UART
- SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups
- GPP_C6/C7 set to I2C1 for future use
- GPP_E15 changed from SCI to SMI, edge triggered
Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When a pad is configured as NC, it is set as a GPI with both
TX and RX disabled, and as the pad is internally disconnected,
no pull up or pull down is needed.
Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CRFP in devicetree and configure GPIOs.
BUG=b:182201937
BRANCH=None
TEST=Boot into OS and confirm FPMCU is responding.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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IPMI debug was extra spewy, so add a debug option as SPI and
other drivers have when they need to be debugged.
Change-Id: I788d67c242cac23bde9750aa3e95e3276c3f1fd7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The default of 32 buses per hotplug bridge is rather high. Especially
for platforms that limit MMConf space to 64 buses: they run out of
numbers if there is more than a single hotplug bridge.
Lower the default to
* 8 if MMConf is limited to 64 or less buses,
* 16 if MMConf is limited to 128 or less buses.
Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52069
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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More relational operators were added to Kconfig in 2015. Now we can
make use of them.
Change-Id: I640e5c3ee1485348f09fcb0b0d5035eb53a2c98e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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I wished there was a way to do this in smaller steps, but with
every line fixed an error somewhere else became visible. Here
is a (probably incomplete) list of the issues:
* Only one set of parentheses was supported. This is a hard
to solve problem without a real parser (one solution is to
use an recursive RE, see below).
* The precedence order was wrong. Might have been adapted just
to give a positive result for the arbitrary state of the tree.
* Numbered match variables (e.g. $1, $2, etc.) are not local.
Calling handle_expressions() recursively once with $1, then
with $2, resulted in using the final $2 after the first
recursive call (garbage, practically).
Also, symbol and expression parsing was mixed, making things
harder to follow.
To remedy the issues:
* Split handle_symbol() out. It is called with whitespace
stripped, to keep the uglier REs in handle_expressions().
* Match balanced parentheses and quotes when splitting
expressions. In this recursive RE
/(\((?:[^\(\)]++|(?-1))*\))/
the `(?-1)` references the outer-most group, thus the whole
expression itself. So it matches a pair of parentheses with
a mix of non-parentheses and the recursive rule itself inside.
This allows us to:
* Order the expression matches according to their precedence
rules. Now we can match `<expr> '||' <expr>` first as we should
and everything else falls into its place.
* Remove the bail-out that silenced the undefined behavior.
Change-Id: Ibc1be79adc07792f0721f0dc08b50422b6da88a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the SATA and SSATA REGLOCK as indicated by the Intel documentation.
Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add the SATA device to the device tree so it may be found
when trying to write SATA registers. Otherwise, it fails
on "requests hidden 00:17.0 PCI: dev is NULL!"
Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set MSR locks as indicated by the Intel documents.
The following MSRs settings are locked:
MSR_FEATURE_CONFIG AES enable/disable lock
TURBO_ACTIVATION_RATIO_LOCK
This also adds PARALLEL_MP_AP_WORK to enable running on APs to set
each CPU MSR.
Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 59626b8670da326ab725e67b01dd1025b0a34a86.
Reason for revert: Reported to cause boot-loops. Reason unknown.
Change-Id: Id7f6211aaaf0401017176f63a17763f28d2744c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52424
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MPTS is currently not executed by the AML interpreter.
Use Method (\\_SB.MPTS) instead of
Scope (\\_SB)
Method (MPTS)
ScopeEnd
Tested on Prodrive Hermes. MPTS is now executed at S5.
Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
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Since there are some differences between picasso PSP svc and cezanne PSP
svc, each platform should have their own svc wrapper.
Moreover cezanne PSP will drop unused parameters from
update_psp_bios_dir and save_uapp_data so make wrapper around it.
BUG=b:182477057
BRANCH=none
TEST=build psp_verstage and boot on zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I69f998865fc3184ea8900a431924a315c5ee9133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52307
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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psp_verstage is not specific to picasso. There might be picasso-specific
code but move everything into common as a first step. While developing
psp_verstage for cezanne picasso-specific code will move back to picasso
directory.
BUG=b:182477057
BRANCH=none
TEST=build psp_verstage on zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifb1df0d82b972f28be2ffebd476c2553cbda9810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change implements `gpio_snapshot()` and `gpio_verify_snapshot()`
callbacks that are useful for debugging any GPIO configuration changes
across FSP-S. These can be utilized by all Intel SoCs that make use of
the common block GPIO driver.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I82a1f125c490b9d6e26e6e9527c2fcd55bb9d429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Traditionally, for each Intel platform using FSP, FSP-S has at some
point configured GPIOs differently than the mainboard configuration in
coreboot. This has resulted in various side-effects in coreboot,
payload and OS because of misconfigured GPIOs. On more recent Intel
platforms, a UPD `GpioOverride` is added that coreboot can use to
ensure that FSP does not touch any GPIO configuration.
This change adds a debug option `CHECK_GPIO_CONFIG_CHANGES` to fsp2_0
driver in coreboot that makes a platform callback `gpio_snapshot` to
snapshot GPIO configuration before making a call to FSP SiliconInit
and Notify phases. This snapshot is then compared against the GPIO
configuration using platform callback `gpio_verify_snapshot` after
returning from FSP. The callbacks are not added to romstage (FSP-M)
because mainboard configures all pads in ramstage.
This debug hook allows developers to dump information about any pads
that have a different configuration after call to FSP in ramstage. It
is useful to identify missed UPD configurations or bugs in FSP that
might not honor the UPDs set by coreboot.
This debug hook expects the platform to implement the callbacks
`gpio_snapshot` and `gpio_verify_snapshot`. These can be implemented
as part of the common GPIO driver for platforms using
FSP2.0+. Platforms that implement this support must select the config
`HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT` to make the debug config
`CHECK_GPIO_CONFIG_CHANGES` visible to user.
Proposal for the GPIO snapshot/verify support was discussed in the RFC
CB:50829.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5326fc98b6eba0f8ba946842253b288c0d42c523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50989
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4c989de4d2af3e810fb0e4803d0fa2396917d93e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50829
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI code to enable the backlight when we enter the OS.
BUG=b:184198808
TEST=Backlight enabled in the OS
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kconfig value specified Intel instead of AMD.
BUG=b:184198808
TEST=Backlight enabled in the OS
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I9fbdf821591ec886f383c1a5ac197f8f213c4cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52384
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The headers added are generated as per FSP v2117_00.
Previous FSP version was v2081_02.
Changes Include:
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:184129128
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b
Cq-Depend: TBD
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I33a5f177affc3f13d091a85073499b7283f54ada
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add the following locks as recommended by the Intel docs:
DRAM_POWER_INFO_LOCK
PCU_CR3_FLEX_RATIO_LOCK
TURBO_ACTIVATION_RATIO_LOCK
PCU_CR0_PMAX_LOCK
Change-Id: I8d8211977e87109a91790a4070454fc561aa761b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Call the SMM finalize SMI. Adds SMM_FEATURE_CONTROL setting to enable
MCHK on code fetch outside SMRR and the register lock as recommended
by the BWG.
Change-Id: Ie3b58d35c7a62509e39e393514012d1055232d32
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51651
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Rocky Phagura
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the flash PRR3 and PRR4 lock to be set with SPI FLOCKDN.
Change-Id: I288eea3e0e853e5067c5af23e22eab79330c0f20
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51779
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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support audio AMP selection with fw_config.
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add AUDIO_AMP ports bit field in devicetree.
UNPROVISIONED 0
MAX98360 1
RT1015_I2C 2
RT1015P_AUTO 3
BUG=b:185082705
BRANCH=dedede
TEST=build pass
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CBFS size equals flash size, leaving no space for descriptor and ME.
Reduce CBFS_SIZE.
BUG = N/A
TEST = Build and boot Portwell M107
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Ida5a248edf4f602c4a106ae29d706e732ef8454f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TPM_INIT_RAMSTAGE needs to be enabled for measured boot only
configuration.
Remove TPM_INIT_RAMSTAGE disable.
BUG = NA
TEST = Boot possible combinations of VBOOT, measured boot and vendorcode
security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I91bde691d445d4210429c928e90e16653092f1cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Modify GPIO_D22/D23/E11 configuration for P-sensor
BUG=b:185214363
BRANCH=dedede
TEST=built storo firmware and verified P-sensor function
Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Set ACPI_FADT_LOW_PWR_IDLE_S0 flag in FADT.
BUG=b:178728116
TEST=Dump FACP and confirm Flags bits match expected.
Change-Id: I59ef762a18903135f9daa902ba8d1e40c451e96c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52035
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:178728116
Change-Id: I0d09bd4361f5f47360daf750efbc993010804902
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The darp5 has several GPIO differences to the galp3-c, which are already
accounted for in gpio.c.
Change-Id: I951e86e53e9c47b9f3038927f44e505d37200c26
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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