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2020-10-30mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHzJohnny Li
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-30{soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfgArthur Heymans
The last argument for acpi_fill_mcfg() is the last PCI bus, which is an uint8_t, not the total number of busses, which overflows the argument if CONFIG_MMCONF_BUS_NUMBER is 256. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-30vc/amd/fsp: Update bl_errorcodes_public.hMartin Roth
Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30soc/amd/picasso: Fix the PSP SMI trigger infoMarshall Dawson
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP library was implemented. The trigger address must be an SMI trigger register. Assign one of the reserved triggers to the PSP. The #define of SMITYPE_PSP 33 is still correct and is intentionally unmodified. This patch should be innocuous as the system doesn't currently support SMI-based features of the PSP. The call only exists so the PSP will honor a mailbox command during S3 suspend. BUG=b:171815390 TEST=Run SST on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30amdfwtool: Take a config file instead of command line parametersZheng Bao
To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30cbfs: Hook up to new CBFS implementationJulius Werner
This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30commonlib/bsd: Add new CBFS core implementationJulius Werner
This patch adds a new CBFS implementation that is intended to replace the existing commonlib/cbfs.c. The new implementation is designed to meet a bunch of current and future goals that in aggregate make it easier to start from scratch than to adapt the exisiting implementation: 1. Be BSD-licensed so it can evetually be shared with libpayload. 2. Allow generating/verifying a metadata hash for future CBFS per-file verification (see [1][2]). 3. Be very careful about reading (not mmaping) all data only once, to be suitable for eventual TOCTOU-safe verification. 4. Make it possible to efficiently implement all current and future firmware use cases (both with and without verification). The main primitive is the cbfs_walk() function which will traverse a CBFS and call a callback for every file. cbfs_lookup() uses this to implement the most common use case of finding a file so that it can be read. A host application using this code (e.g. coreboot, libpayload, cbfstool) will need to provide a <cbfs_glue.h> header to provide the glue to access the respective CBFS storage backend implementation. This patch merely adds the code, the next patch will integrate it into coreboot. [1]: https://www.youtube.com/watch?v=Hs_EhewBgtM [2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf (Note: In early discussions the metadata hash was called "master hash".) Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30util/docker: Add sdcc to our build nodesPatrick Georgi
core-ec will need it. Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-30.gitignore: Split into subdirectory filesPatrick Georgi
There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30drivers/soundwire/alc711: Add Realtek ALC711 soundwire deviceAnil Kumar
Bug=None Test=Enabled the device on TGLY RVP and tested that the codec is reflected in SSDT. Checked sound card binding works and soundwire drivers are enabled in kernel. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-30soc/intel/broadwell: Drop reg-script to finalize PCHAngel Pons
Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Relocate PCH finalisation codeAngel Pons
Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Get rid of `cpu_is_ult`Angel Pons
It is only used in a single file, on two functions that already check whether coreboot is running on a Haswell or a Broadwell processor. Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46708 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Inline CPUID helpersAngel Pons
These functions are small and used in various stages. Inline them. Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46707 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Move PCH code into pch subdirAngel Pons
Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Separate PCH in devicetreeAngel Pons
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30Revert "broadwell: update processor power limits configuration"Angel Pons
This reverts commit fa42d568a00e5daadd35722790c529539227130e. Reason for revert: Passes in an incompatible structure and only happens to boot by chance. Moreover, Broadwell will soon be merged with Haswell and this requires Broadwell to not depend on any Intel common SoC code. Tested on out-of-tree Acer Aspire E5-573, PL values are correct again. Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45011 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`Angel Pons
Commit 360684b (soc/intel/common: add TCC activation functionality) made Broadwell use common SoC code. However, this makes Broadwell depend on SoC code, which prevents splitting Broadwell into CPU, northbridge and southbridge, a stepping stone before merging with Haswell and Lynxpoint. Tested on out-of-tree Acer E5-573, still boots. Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/auron: Add SATA PCI device to overridetreeAngel Pons
`chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope. Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip. TEST=Sanity-check static.c and verify overridetrees override properly. Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/purism/librem_bdw: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/intel/wtm2: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/jecht: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/google/volteer: correct memory id for elemiWisley Chen
BUG=b:170604353 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into kernel. Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29hatch: Create ambassador variantMatt Ziegelbaum
Create the ambassador variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171561514 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_AMBASSADOR Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-29soc/intel/xeon_sp: Move function debug macrosMarc Jones
Move the macros for printing debug information to debug.h in the common console include directory and device include file. These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8. The macros could be used by any platform. Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-29include/device/device.h: Move resource debug macrosMarc Jones
Add general debug macros that print resource information. These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8. The macros are helpful in debugging complex resource allocation with multiple buses. The macros are moved from soc/intel/xeon_sp, where they were originally developed. Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-29mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik
List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29soc/mediatek/mt8192: Do dram full calibrationHuayang Duan
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-29mb/asus/f2a85-m_pro: Enable super-I/O LDNs 0x0f and 0x14Nico Huber
The LDNs don't have a 0x30 register to enable them. However, with the devices set to `off`, coreboot won't configure them. Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46021 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Clean up super-I/O GPIO settingsNico Huber
Drop useless writes to read-only registers and don't re-write default 0x00 values. In detail: * Don't write read-only status registers. * Don't try to write input bits in data registers (iow. mask data values: `data &= ~io`). * Don't write data registers if all GPIOs are set as inputs (`io == 0xff`). * Don't write default 0x00 for inversion and multiplex registers. Note: Both GPIO0 and WDT1 values look spurious. Maybe they were dumped with the virtual devices disabled? Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46020 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Comment and group super-I/O GPIO settingsNico Huber
Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Enable GPIO0 on the super I/ONico Huber
It is enabled by the vendor firmware. Also drop spurious `io 0x60 = 0x00` setting. It's the default anyway and the resource is kept disabled (it's controlled by the virtual LDN 2e.008). This fixes the hang in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. Fixes: 2f8192bc ("asus/f2a85m_pro: Fix superio type in devicetree") Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28payloads/filo: Set stable tag to something that buildsNico Huber
Also rename the prompt to "tested" to make it more obvious that there is no really stable version. Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-28soc/intel: deduplicate ACPI timer emulationMichael Niewöhner
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-28mb/ocp/tiogapass/dsdt: Remove unnecessary commentsMaxim Polyakov
Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28ifdtool: add "reserved" regionsStefan Reinauer
This will let you at least dump / add these regions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28mb/google/zork: Revert temp acpi backlight fixJosie Nordrum
Remove code to turn on backlight during ACPI mode because backlight has been properly enabled in ACPI. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28mb/google/zork: Generate acpi methods in mainboard.cJosie Nordrum
Generate acpi methods which enable and disable backlight during _INI, _WAK, and _PTS. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28soc/amd/picasso/acpi: Include platform.aslJosie Nordrum
Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to correctly enable backlight in OS for zork. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I702f807a5907d85d083295cf339ba9d31b246627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28soc/amd/common/acpi: Create platform.asl to define acpi transitionsJosie Nordrum
Define device _WAK, _PTS, and _INI acpi methods with callbacks into mainboard methods if provided. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I8020173a15db1d310459d5c1de3600949b173b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28sec/intel/txt/Kconfig: Remove the menu for including ACMsArthur Heymans
This is consistent with how other binaries (e.g. FSP) are added via Kconfig. This also makes it more visible that things need to be configured. Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variablesArthur Heymans
The Kconfig variables are used in the C code for cbfs file names but not in the Makefiles adding them. Change-Id: Ie35508d54ae91292f06de9827f0fb543ad81734d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28drivers/mrc_cache: Fix size comparison in mrc_cache updateTim Wawrzynczak
`mrc_cache_needs_update` is comparing the "new size" of the MRC data (minus metadata size) to the size including the metadata, which causes the driver to think the data has changed, and so it will rewrite the MRC cache on every boot. This patch removes the metadata size from the comparison. BUG=b:171513942 BRANCH=volteer TEST=1) Memory training data gets written the on a boot where the data was wiped out. 2) Memory training data does not get written back on every subsequent boot. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28mb/google/nightfury: Set internal pull-down for GPP_D19Seunghwan Kim
Add internal pull-down for GPP_D19 to improve DMIC noise issue on nightfury. BUG=b:171669255 BRANCH=firmware-hatch-12672.B TEST=Built and checked GPP_D19 voltage after booting Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-28mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scopeMaxim Polyakov
The corresponding devices and objects are already included in the System Bus ACPI scope inside uncore.asl. There is no need to do this again in the DSDT of the motherboard. Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7Morgan Jang
TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADTMorgan Jang
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/ocp/deltalake: Rename motherboard_fill_fadt()Jingle Hsu
Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/google/asurada: Pass reset gpio parameter to BL31CK Hu
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28mb/google/asurada: Configure pinctrl for SD and MMCWenbin Mei
The pins for SD and MMC must be configured properly so we can access them in payloads. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-28security/vboot: fix policy digest for nvmem spacesAndrey Pronin
This CL fixes the policy digest that restricts deleting the nvmem spaces to specific PCR0 states. BRANCH=none BUG=b:140958855 TEST=verified that nvmem spaces created with this digest can be deleted in the intended states, and cannot be deleted in other states (test details for ChromeOS - in BUG comments). Change-Id: I3cb7d644fdebda71cec3ae36de1dc76387e61ea7 Signed-off-by: Andrey Pronin <apronin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46772 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/octopus/var/garg: Disable XHCI LFPS power management by skuKevin Chiu
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/octopus/var/garg: fix LTE power sequence in reboot stateKevin Chiu
invoke LTE power off function to meet LTE power sequence while DUT is in reboot state. BUG=b:167565015 BRANCH=octopus TEST=build and verify on the DUT with LTE Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27device: Rephrase bus master Kconfig optionFelix Singer
Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-27util/testing: Allow what-jenkins-does to skip lint testingMartin Roth
The linters touch every file under src and probably util. This makes it difficult to see what files have been accessed by the builder. The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins build that looks for unused files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/testing: Update test-abuild output directoriesMartin Roth
This matches the what-jenkins-does target. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update atime mount point options for jenkinsMartin Roth
- The ccache files don't need atime. - Enable strict atime for the git repos. This will help find unused files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update agent-root to node-root for jenkinsMartin Roth
Jenkins has changed the name of the build directory, so it's not currently building out of memory, it's writing to the SSD. This changes the build back to tmpfs. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Add tests to coreboot-sdk build processMartin Roth
This tests some of the basic targets that coreboot-sdk needs to be able to run. I was running most of these tests manually after creating the sdk image, but adding it into the Dockerfile makes sure they get run. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update coreboot-sdk consolidate coreboot buildMartin Roth
Because docker saves a container for every run command, by breaking the coreboot build into 3 commands, it greatly increased the size of the docker containers needed. When combined as one run command, the coreboot repo that is downloaded, along with the coreboot test build are deleted before the container is created. Since those directories are deleted in a later run command, they don't even make it into the final container, and just force coreboot-sdk users to download extra data for no reason. While splitting the build may help with debugging failures when creating the docker container, that debugging can be done locally by splitting up a working copy. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update coreboot-sdk to set python2 as defaultMartin Roth
Even though both python2 and python3 are now installed to the SDK, the default python program is not. This sets the default to python2. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update coreboot-sdk with additional toolsMartin Roth
- cscope: Run cscope targets - ctags: Run ctags targets - pbzip2: Allow compression on all cpu cores Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27mb/google/auron: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27util/testing: Remove test for util/broadcom/secimageMartin Roth
util/broadcom/secimage was removed in commit aea00f496b1, so don't try to test it anymore. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27mb/google/dedede/var/magolor: Configure I2C high and low timeRen Kuo
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDENJonathan Zhang
Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: CID 1435825 and 1435826 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/kukui: change Jacuzzi followers LCMID to fixed valueKevin Chiu
The LCM ID is not really used on Jacuzzi followers and the reference design expects ADC to return 0. However, there were hardware design issues so the returned value became unexpected numbers. - Juniper and Kappa returns 1. - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot. - Cerise and Stern usually returns 0, and sometimes 1. To fix that, we are changing LCM ID to fixed value for Jacuzzi followers. BUG=b:170916885,b:171365301 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. check burnet/esche skuid correctly Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-26mb/google/volteer: Add a DPTF policy for EldridNick Chen
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Follow thermal validation and update PL2 max_power to 51 BUG=b:167931578, b:170357248 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26lib/edid: Add missing name descriptor presence flagJakub Czapiga
EDID parser internal flag c->has_name_descriptor was never set. It was causing decode_edid() function to return NON_CONFORMANT instead of CONFORMANT even when EDID frame was correct. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26cbfstool: Don't build unneeded commonlib sourcesJulius Werner
These sources are built but not used by cbfstool. The only .c file in commonlib/ it really needs is fsp_relocate.c. Get rid of the others. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46253 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26vboot: Disable vboot functions in SMMJulius Werner
SMM does not have access to CBMEM and therefore cannot access any persistent state like the vboot context. This makes it impossible to query vboot state like the developer mode switch or the currently active RW CBFS. However some code (namely the PC80 option table) does CBFS accesses in SMM. This is currently worked around by directly using cbfs_locate_file_in_region() with the COREBOOT region. By disabling vboot functions explicitly in SMM, we can get rid of that and use normal CBFS APIs in this code. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-26libpayload/keyboard: Use `bool` as return typeNico Huber
Use `bool` whenever `0` was used to indicate an error. The mixing of different types for return values was mildly confusing and potentially dangerous with the i8042 API close by that uses `0` for success. Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26libpayload/curses: Use <stdbool.h>Nico Huber
Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26libpayload: Add <stdbool.h>Nico Huber
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26ectool: Don't ignore fgets return codeStefan Reinauer
Change-Id: I12dc449e06dee31b4b0811ab23c6e8635cf31512 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26ectool: Add newline to warning messageStefan Reinauer
Cosmetic fix: $ sudo ./ectool -p Cannot get EC ports from /proc/ioports, fallback to default.EC RAM: Change-Id: Icc2b5bbbbfe7685e4fe512af029ce00b33a26daa Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26inteltool: Only use real graphics devicesStefan Reinauer
Right now IGD is hard coded to 0:2.0 and if that device is there, it is blindly used, even if it is not a graphics device. Look at the PCI class to make sure we're not using the wrong device. Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26inteltool: initial Hewitt Lake supportStefan Reinauer
Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26soc/amd/picasso/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26tests: Add lib/imd-test test caseJakub Czapiga
Implement unit tests for src/lib/imd.c module. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Signed-off-by: Anna Karas <aka@semihalf.com> Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I3902f8638669440144064ce0e3756918338f4068 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46457 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26tests: Add test region and symbol macros to <tests/test.h>Jakub Czapiga
Some modules require and operate on memory regions and symbols. This macros systematize how they are defined in testing code. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I314028c201732416bb3d5446a4c8585e055073e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-26Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"Karthikeyan Ramasubramanian
This reverts commit 5acea15d63e821a1bc416d206162ed030cd5d57c. This change got accidentally merged. There is no need for mainboard to override chip configuration. BUG=None TEST=Build and boot Drawlat to OS. Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"Karthikeyan Ramasubramanian
This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc. CB:45857 overrides the GPIO PM configuration if Cr50 does not support long interrupt pulse width. More recent Cr50 Firmware versions support long pulse width and hence the GPIO PM can take the default configuration. BUG=None TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of suspend/resume sequence, warm and cold reboot cycles each are successful. Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2020-10-26ec/google/chromeec: Update ec_commands.hTim Wawrzynczak
This change copies ec_commands.h directly from the Chromium OS EC repo at SHA edd8b73e8, with the exception of changing the copyright header to SPDX format. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45937 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26sconfig: Split up sconfig-generated static.hTim Wawrzynczak
Currently sconfig generates a `static.h` to accompany `static.c`. However, some payloads may decide they would like to consume the FW_CONFIG macros as well. The current state of `static.h` makes this impossible (relying on `device/device.h`). This patch splits up `static.h` into 3 files: `static.h, `static_devices.h`, and `static_fw_config.h`. `static.h` simply includes the other two `.h` files to ensure no changes are needed to other code. `static_devices.h` contains the extern'd definitions of the device names recently introduced to sconfig. `static_fw_config.h` contains the FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a payload which wishes to use FW_CONFIG. Also refactor the generation of all these output files, as the code was getting messy. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-26arch/x86/smbios: Populate SMBIOS type 7 with cache informationMorgan Jang
SMBIOS has a field to display the cache size, which is currently set to UNKNOWN unconditionally, multiply the cache size of L1 and L2 by the number of cores. TEST=Execute "dmidecode -t 7" to check if the cache information is correct for Deltalake platform Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26sb/amd/*/*/pci_devs.h: Reduce the differenceElyes HAOUAS
Also add missing <device/pci_def.h> Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26sb/amd/*/*/smbus.h: Make 'smbus.h' uniformElyes HAOUAS
Reformat 'smbus.h' files and add missing <stdint.h>. Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26mb/ocp/deltalake: Override coreboot log level via VPDJohnny Lin
Tested=On OCP Delta Lake, log level can be changed via VPD. Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-10-26cpu/intel/common: implement the two missing CPPC v2 autonomous registersMichael Niewöhner
This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt Delco <delco@chromium.org>
2020-10-26soc/intel/icl: enable common CPU codeMichael Niewöhner
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26soc/intel/skl: replace conditional on dt option reading CPUID for CPPCMichael Niewöhner
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel: drop unneeded ISST configuration codeMichael Niewöhner
The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26util/intelp2m: Fix typosBenjamin Doron
Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26console/init: Drop CONSOLE_LEVEL_CONSTNico Huber
We limited the configurability of the debug level to stages that have a `.data` section. This is not really a requirement, because a `.bss` section should suffice and we always have that now. We want to make the debug level configurable early but also want to avoid calling get_option() early, as an error therein could result in no console output at all. Hence, we compromise and start using get_option() from the second console init on. TEST=Booted QEMU once with `debug_level=Debug` and once with `debug_level=Notice`. On the second boot, most messages vanished for all stages but the bootblock. Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWRSheng-Liang Pan
Enable front camera power in ramstage. BUG=b:169170677 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2020-10-26security/tpm/tspi/crtm: Add line break to debug messagesFrans Hendriks
Add line break at debug messages. Tested on Facebook FBG1701 Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46659 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/google/octopus/var/fleex: Add goodix touch pad supportEric Lai
Add goodix touch pad as below: HWID : GXTP7288 CID : PNP0C50 I2C address : 0x2C I2C speed : 400Khz HID Descriptor Address : 0x20 BUG=b:171351666 BRANCH=octopus TEST=build image and verify goodix touch pad working. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel/common/block/smbus: Add define for I2C_ENPatrick Rudolph
Change-Id: Iecccc363f492985555019f2390bd53472a000ba9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 18:02:41 +0000