summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-09-03mb/google/dedede/var/bugzzy: Configure DDI port A as MIPI DSISeunghwan Kim
Override DdiPortAConfig as MIPI DSI BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS fileFelix Held
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends on both, so also check if both are selected in the Makefile where it tries to add the FSP-T to the CBFS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03vc/mediatek/mt8195: Remove unused codeRyan Chuang
Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03soc/qualcomm/common: clock: Add support for common clock driverTaniya Das
The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7180: Clean up drivers with common clockTaniya Das
As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to KconfigSubrata Banik
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M (internal and external EC SKUs) hence, select those Kconfigs from mainboard Kconfig rather Kconfig.name. Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order. TEST=No changes are seen while the .config file is getting auto generated. Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-03skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-HAngel Pons
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H. Remove now-redundant mainboard code to set the `UserBd` UPD. Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03mb/prodrive/hermes: Do not overwrite `IedSize` UPDAngel Pons
SoC code already sets this UPD to `CONFIG_IED_REGION_SIZE`, which defaults to 0x400000 for soc/intel/cannonlake. Change-Id: I6587e17a4a3425c561cffe6e3df0d932a2458168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03mb/prodrive/hermes: Use `BOARD_TYPE_SERVER` defineAngel Pons
Change-Id: I291dc71bb6e3888b71ebce315f9ad09ccbc4a9a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-02mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe checkMartin Roth
variant_has_pcie_wwan() was always coming back as disabled because find_dev_nested_path() couldn't find the device until the domain was added to the array. BUG=b:193036827 TEST=Boot guybrush with PCIe & USB WWAN devices. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-02Documentation: add Intel BroadwellIru Cai
Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-02mb/google/brya: reduce RW_MRC_CACHE size to 64KNick Vaccaro
The RW_MRC_CACHE only needs to be 64K for Brya. BUG=none TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 to kernel. Change-Id: I74365b795e184b92f483ae2bf862791e235c5362 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S
Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for wifi time average SAR configSugnan Prabhu S
Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for per-platform antenna gainSugnan Prabhu S
Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S
Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the legacy SAR file format. Following is the format of the new binary file. +------------------------------------------------------------+ | Field | Size | Description | +------------------------------------------------------------+ | Marker | 4 bytes | "$SAR" | +------------------------------------------------------------+ | Version | 1 byte | Current version = 1 | +------------------------------------------------------------+ | SAR table | 2 bytes | Offset of SAR table from start of | | offset | | the header | +------------------------------------------------------------+ | WGDS | 2 bytes | Offset of WGDS table from start of | | offset | | the header | +------------------------------------------------------------+ | Data | n bytes | Data for the different tables | +------------------------------------------------------------+ This change supports both the legacy and the new format of SAR file BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabledMeera Ravindranath
GPIO PM was disabled for brya to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. All devices currently tested on brya support 4us long pulses. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brya to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02drivers/mipi: Make orientation a property of the mainboard, not panelJulius Werner
It doesn't make sense to store the orientation field directly in the panel information structure, which is supposed to be reuseable between different boards. The thing that determines orientation is how that panel is built into the board in question, which only the board itself can know. The same portrait panel could be rotated left to be used as landscape in one board and rotated right to be used as landscape in another. This patch moves the orientation field out of the panel structure back into the mainboards to reflect this. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02mb/google/brya/variants/brask: Enable PCIE port 7 for EthernetDavid Wu
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet BUG=b:193750191 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16Tim Crawford
TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02mb/system76/*: cmos.layout: Reserve century byteTim Crawford
Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-02mb/google/guybrush/nipperkin: update DRAM tableKevin Chiu
MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR BUG=b:194031783 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I71ceaf0a2738584d316a5b7cc51539821b430128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-02mb/google/zork: correct MST probesPeter Marheine
It turns out that putting a device ref in an overridetree at a different point in the tree will generate a duplicate device definition, such that the change introducing this support was ignoring the device presence specified by overridetree.cb and only using the baseboard configuration. I believe testing of that change was not redone after the baseboard was changed to disable the MST, so that conflicting behavior was not noticed. The incorrect behavior generated a disabled device for the MST at the location specified by the baseboard, and one with the probe as a child of the soc. At runtime this did a fw_config probe of the "I2C 00:4a" device, and later probed a different "I2C 00:4a" which was already disabled. As the disabled one came later, it seems to have completely disabled the MST, discarding the results of the variant-specific probe. BUG=b:185862297 TEST=10EC2141 device is now present on a Dali berknip BRANCH=zork Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02util/cbftool: Fix the bug in parsing Uefipayload with extended headerDun Tan
The patch is to fix "Not a usable UEFI firmware volume" issue when creating CBFS/flash image. This issue is caused by adding FvNameGuid in UefiPayloadEntry.fdf in EDKII. There is an ext header between header of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header causes the UefiPayloadEntry to be found incorrectly when parsing Fv. Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585 Signed-off-by: Dun Tan <dun.tan@intel.com> Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296 Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02tests: Add lib/cbfs-verification-test test caseJakub Czapiga
This commit adds test case for lib/cbfs verification mechanisms. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01cbfs: Make sure all cases of single file header corruption are isolatedJulius Werner
The new CBFS stack was written to try to isolate cases of single file corruption as far as possible and still make other files avaialble (at least as long as verification is disabled and they can still be found at all). For most cases of header corruption, it will just continue trying to parse the next file. However, in cases where parts of the file extend beyond the end of the rdev, we have been relying on the range checking of the rdev API rather than doing it explicitly. This is fine in general, but it causes the problem that these errors cannot be distinguished from I/O errors, and I/O errors always make the whole cbfs_walk() fail. That means we will not return a successful result from cbfs_mcache_build(), and leads to an odd discrepancy in how certain kinds of corrupted CBFSes are treated with and without mcache. This patch adds an explicit range check to make the behavior consistent. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice2b6960284bd0c19be35b0607e5e32791e7a64c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-09-01tests: Improve test output readabilityJakub Czapiga
When running multiple tests, e.g. by using unit-tests target, it is hard to differentiate, which output comes from which file and/or configuration. This patch makes the output easier to analyze and understand by using new wrapper macro cb_run_group_tests(). This macro uses __TEST_NAME__ value (containing test path and Makefile test name) as a group name when calling cmocka group runner. Example: Test path: tests/lib/ Makefile test name: cbmem_stage_cache-test Test group array name: tests Result: tests/lib/cbmem_stage_cache-test(tests) Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01soc/amd/cezanne: Increase the FSP_M_SIZE configurationKarthikeyan Ramasubramanian
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is greater than the size allocated in DRAM. Increase the allocated size for FSP_M binary in DRAM to handle both debug and release FSP_M binaries. Also adjust the verstage load address accordingly. BUG=None TEST=Build and boot to OS in guybrush with both debug and release FSP_M. Perform warm, cold reboot and suspend/resume cycling for 10 iterations. Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01libpayload: Move EXTRA_CFLAGS to enable option overrideJakub Czapiga
Before this patch EXTRA_CFLAGS were placed before many other options. This made overriding impossible even, when necessary. This patch moves EXTRA_CFLAGS to be placed after original CFLAGS, thus making option overriding possible. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/goog/brya: Add probed fw_configs to SMBIOS OEM stringsWisley Chen
Enable this feature, and it can use the probe statement in devicetree to cache of fw_config field as oem string. BUG=b:191931762 TEST=With CBI FW_CONFIG field set to 0x8, set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree dmidecode -t 11 OEM Strings AUDIO-MAX98390_ALC5682I_I2S_4SPK Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01util/sconfig: Compare probe conditions for override device matchFurquan Shaikh
When the override functionality looks for device match, check that the probe list for both the devices matches exactly if probe list exists for the base device. This ensures that if there are two devices with same identity (e.g. I2C address or USB port #) but using different properties (registers) controlled by different probe statements, then the two devices are not incorrectly matched as the same device. The check for base device having a probe list is performed before comparing the probe lists because a base device might not really have any probe requirements at all. So, when overriding such a device, there is no need to check for the probe list match. BUG=b:187193527 TEST=Verified by adding two I2C devices in the override tree with the same I2C address and chip but different probe statements and confirmed that both the devices are present in generated static.c file. Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01mb/google/volteer: Move hda device enabling to override treeFurquan Shaikh
This change moves the hda device enabling from baseboard device tree to override tree for the variants that did not provide any hda specific nodes. This ensures that the probe statements are correctly selected by the variant depending upon the configurations it supports. Change-Id: Ib7b36468f17fbd65eb3d7d9355fcf78148aeb44a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57123 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/google/volteer: Fix USB4 enabling for volteer familyFurquan Shaikh
volteer baseboard was currently enabling TBT(USB4) devices in baseboard devicetree and also selecting the Kconfigs required for resource allocation above 4G for the USB4 controllers. However, not all volteer devices have USB4 support. This change fixes USB4 enabling for volteer family by making the following udpates: 1. TBT devices are moved from baseboard devicetree to individual override trees for the variants that actually support USB4. 2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as on instead of hidden for all variants other than volteer reference. This is because volteer reference is the only device that has an asymmetric support for USB4 (i.e. does not support USB4 on C0 port). 3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for these variants. Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01mb/google/brya/var/redrix: adjust uid for Maxim ampWisley Chen
DEV0 - 0x3a i2c-MX98390:00: Right Speaker DEV1 - 0x3b i2c-MX98390:01: Left Speaker DEV2 - 0x38 i2c-MX98390:02: Right Tweeter DEV2 - 0x39 i2c-MX98390:03: Left Tweeter This is to consist with other 2 speakers configs, and m/c driver design. uid0/1 = regular speakers. uid2/3 = tweeter BUG=191931762 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.hJohnny Lin
It would be easier for people to find the defined variables. Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-01drivers/intel/fsp1_1/romstage.c: Remove MCU updateArthur Heymans
On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-01soc/amd/common: Change default spi speeds to 33MHzMartin Roth
In CB:56884 we discussed changing the default fast_read speed from 66MHz, which some platforms may not be capable of running, to 33MHz, which should be generally suitable for all platforms. This same change has been applied to the default for all SPI speeds. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31cbfstool: add buffer_end() to common.hRicardo Quesada
Add buffer_end() function to common.h. This function returns a pointer to the end of the buffer (exclusive). This is needed by elogtool util. (See the next CL in the chain). BUG=b:172210863 Change-Id: I380eecbc89c13f5fe5ab4c31d7a4fef97690a791 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-31arch/x86: Implement cpu_info in C codeArthur Heymans
Change-Id: Ic7396b8429e29739e18a189dacea3a76e571cd58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57049 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/google/dedede/var/cret: Modify Wifi SAR conditionIan Feng
Using tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:194163604 TEST=build and test on cret and cret360 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ie94c2a07ad43fe1cb426e543dd97ed0434c42f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-31soc/amd/*/include/soc/gpio: remove GPIO_2_EVENTFelix Held
commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special GPIO_2 override soc_gpio_hook) removed the workaround that needed those definitions, so remove the now unused GPIO_2_EVENT definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31smbios.c: Move function definition near call-siteAngel Pons
The `smbios_get_device_type_from_dev()` function is only called once from the `smbios_walk_device_tree_type41()` function. Put the former function's definition above the latter function's, instead of having them a thousand lines apart. Change-Id: Idc6175324ca8a14841eaf7d6904712efb75f2d26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57205 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/google/brya/var/gimble: Include SPD for K4UBE3D4AA-MGCRMark Hsieh
Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31mb/razer/blade_stealth_kbl: Disable UART #0 in devicetreeAngel Pons
FSP-S disables UART #0 as per the `SerialIoDevMode` settings. Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de>
2021-08-31mb/google/caroline: Enable I2C #2 in devicetreeAngel Pons
Commit 98ec53bdf15ff79369307862e71142d4606f9e5a (mb/google/caroline: Re-enable I2C2 / fix digitizer) enabled I2C #2 in the `SerialIoDevMode` array, but left the device disabled in the devicetree. Enable it. Change-Id: I67eec1c753bfd2a78ed0c1e0a78057cd4a3d4153 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-31mb/google/poppy: Do not let FSP-S init UART 0Angel Pons
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao
This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Copy string in a safer wayZheng Bao
The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/cezanne/fch: implement and use fch_clk_output_48MhzFelix Held
Make sure that the 48MHz clock output that is typically used as a clock source for an I2S audio codec or a Super I/O chip. TEST=On Guybrush before and after this patch the final state of MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/(amd,google): Remove spi configuration from devicetreeMartin Roth
Now that the SPI configuration has been moved into Kconfig, it is no longer needed in devicetree. BUG=b:194919326 TEST=Build & boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/common: Show current SPI speeds and modesMartin Roth
This patch adds code to print the current SPI speeds for each of the 4 different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays the SPI mode and whether or not SPI100 mode is enabled. BUG=b:194919326 TEST: Display the speed, change speeds, show that new speeds are the expected values. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/cezanne/early_fch: Perform early SPI initializationKarthikeyan Ramasubramanian
Add the fch_spi_early_init call in fch_pre_init to perform early SPI initialization which enables SPI ROM and setting the speed & read modes. BUG=b:194919326 TEST=Build and boot to OS in Guybrush. Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/common: Update SPI based on Kconfig & EFS instead of devtreeMartin Roth
Get the settings for fast-read and mode from EFS, and reprogram those. Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings. BUG=b:195943311 TEST=Boot and see that SPI was set to the correct speed & mode Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-30soc/amd/common: move GPIO register state save struct to gpio_banks.hFelix Held
The common_i2c_save struct isn't specific to the I2C code and since it contains the state of the GPIO control & status register and the state of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and rename it to soc_amd_gpio_register_save. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-30soc/amd/common/fsp/Makefile: drop strip_quotes call in FSP-M size checkFelix Held
No need to strip the quotes of the FSP-M file path in the size check and it's always a good idea to not remove the quotes around file paths that will get passed as parameters to shell programs so that spaces in the path can't cause malfunction. TEST=All cases still behave as expected for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-30mb/intel/adlrvp_m: Fix to Enable PCIe x1 SlotCliff Huang
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs. The BDF for this PCIe slot is pci is: 0000:00:1d.0 TEST = show device command: $ lspci -s 00:19.0 expect this: 00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/brya/var/felwinter: Update gpio tableEric Lai
Based on latest schematic to update the gpio table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya/var/felwinter: Update device treeEric Lai
Based on latest shcematic to update the device tree. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya: Enable TCSSDeepti Deshatty
Enable flag SOC_INTEL_COMMON_BLOCK_TCSS. BUG=b:187385592 TEST=type-C pendrive/Gen-2 SSD detected as Super speed. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54090 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure thermal sensor settingFrank Wu
According to schematics, TSR2 thermal sensor is not present in driblee. BUG=b:191732473, b:197180925, b:195868075 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure audio settingFrank Wu
Update the combination audio CS42L42 and amp. MAX98360. BUG=b:195619349, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-29soc/amd/cezanne/chip: add functionality to power down eMMC interfaceFelix Held
Power down the eMMC controller via the AOAC interface when it's not enabled in the devicetree. BUG=b:184978118 TEST=On guybrush the unused eMMC controller is disabled in AOAC after applying this patch. Before this patch it was enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-08-29superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASEBill XIE
NCT6776's data sheet does say that the virtual LDN of GPIO base should be 0x308, and most mainboards using it usually correctly config it in devicetree.cb under the path 2e.308, but in nct6776.h it used to be defined as 8 from the beginning (an ancient commit 1e3a22649a9, lately revived in commit f95daa510d6), identical to the LDN of WDT, which eliminates the definition of value 2e.308, and makes related resource allocations unable to take effect. (in log we can find "PNP: 002e.308 missing read_resources" if 2e.308 is enabled and assigned with resources) In this commit, NCT6776_GPIOBASE is set to a value consistent with the data sheet. With this commit, resources under 2e.308 of NCT6776 can be allocated successfully. Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-28mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cbMariusz Szafrański
This change follows other Intel SoCs common way to support SKUs with bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and allowing its detection at boottime. It completes support for HCV/DNV after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 soc/intel/denverton_ns: Ensure CPU device has a valid link Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11 Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-28soc/amd/common/fsp/Makefile: check if CONFIG_FSP_M_FILE is definedFelix Held
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size call evaluates to an empty string, so the file-size call will run "cat | wc -c" which will cause make to get stuck in there. Also print a message when no FSP-M file is specified that the resulting image won't boot successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-28mb/google/{dedede,hatch}: Remove unneeded documentationFelix Singer
This documentation doesn't add any more value. Thus, remove it. Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28mb/google/brya/variants/primus: update USB 2.0 controller Lane ParameterCasper Chang
Modify USB 2.0 port5 parameter to improve SI diagram measurement. BUG=b:187992881 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1eff05a7ad6563898744c24f9657e28625319873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:194356991 TEST=ALC5682-VD/ALC5682-VS audio codec can work Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/dedede/var/boten: Generate SPD ID for supported partstanley.wu
Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the boten board. Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya/var/anahera: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:197850509 TEST=build pass Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/driblee: Configure I2C ports and touchpadFrank Wu
Update the I2C ports and touchpad based on the schematic. BUG=b:195622489, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/driblee: Configure USB port settingsFrank Wu
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Add two sensors for DPTF functionalitySumeet Pawnikar
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28mb/intel/adlrvp_m: Enable touchscreenBernardo Perez Priego
This will add ACPI information to enable WACOM touchscreen. TEST=Boot DUT and issue command: $ ls -al /sys/bus/i2c/devices WACOM PWB-D893 device should be listed and touchscreen should be functional. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-28mb/google/dedede/var/corori: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Corori. Here is the ram part number list: DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR BUG=b:196744958 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure thermal sensor settingIan Feng
According to schematics, TSR2 thermal sensor is not present in corori. BUG=b:197281317 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure I2C ports and touchpadIan Feng
1. Support Elan touchpad. 2. Follow schematic to disable I2C1, I2C2 and I2C3. BUG=b:197052531 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure audio settingIan Feng
Select the drivers for ALC5682 codec and MAX98360A spk amp BUG=b:197037090 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure USB port settingsIan Feng
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:196998272 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure GPIO settingsIan Feng
Updated the GPIO pins based on the latest schematic. BUG=b:196867404 BRANCH=keeby TEST=FW_NAME=corori emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Create anahera variantWisley Chen
Create the anahera variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:197850509 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANAHERA Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/google/butterfly: Put braces around `else` branchAngel Pons
Ensure braces are consistent on all branches of a conditional statement, as per the coding style. Tested with BUILD_TIMELESS=1, Google Butterfly remains identical. Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Broadwell boards: Do not assign unused SPD addressesAngel Pons
The `pei_data` struct is already zero-initialised. Change-Id: If539cddc007f32a04389bc3b3b06c43cb5c86e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55804 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/auron: Refactor memory-down SPD handlingAngel Pons
Variants only need to provide the SPD index and whether said index corresponds to a dual-channel configuration, which can be achieved without using `pei_data`. Add two functions that return the values and use them in `spd.c` at mainboard level. Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-27mb/google/brya/variants/primus: Enable SaGv supportAriel Fang
This patch enables SaGv support for primus. BUG=b:196286180 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I00074e348dd6347602c18dcfd231a890153b4685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27soc/intel/denverton_ns: Ensure CPU device has a valid linkFurquan Shaikh
This change calls `add_more_links()` in `denverton_init_cpus()` if `dev->link_list` is NULL. This condition can occur if mainboard does not add any APIC device in the device tree. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/intel/adlrvp: Enable SaGv supportV Sowmya
BUG=b:187446498 TEST=Boot and verify memory trains at all the SaGv points through FSP debug logs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-27mb/google/cherry: Support audio codec RT1011Trevor Wu
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011. Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can spearate code for the specific codec by config. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I18939a2a2caae0444ce17f4712764647975121ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27libpayload: cbgfx: Clear screen by sequential accessYu-Ping Wu
Currently clear_screen() calls set_pixel() to set all pixels. However, the actual order of pixels being set depends on the framebuffer orientation. With NORMAL orientation, the framebuffer is accessed sequentially; with LEFT_UP/RIGHT_UP orientation, it is accessed back and forth, leading to performance drop (>1 second on bugzzy). Therefore, ensure sequential access to the framebuffer, regardless of the orientation. BUG=b:194967458 TEST=emerge-cherry libpayload BRANCH=dedede Change-Id: Iecaff5b6abc24ba4b3859cbc44c0d61b2a90b2d9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57104 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Doc/mb/ocp: Update Delta Lake documentation for RAS featuresJohnny Lin
Change-Id: I71b97930f1a1ca4a60f830a90d80af6ca0236c8e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-08-27mb/google/dedede/var/driblee: Configure GPIO settingsFrank Wu
Updated the GPIO pins based on the latest schematic. BUG=b:191732473, b:195619827 BRANCH=keeby TEST=FW_NAME=driblee emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>