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2015-02-06TPM: Fix whitespaceKyösti Mälkki
Change-Id: I2d00a2964b16436356c5e02764897e37ef610efc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8343 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05mainboards/asus/kfsn4-dre: Enable native VGA initializationTimothy Pearson
Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05drivers/xgi/z9s: Port Linux framebuffer initialization to corebootTimothy Pearson
Add native XGI Z9s framebuffer support to coreboot XGI initialization code largely taken from Linux 3.18.5 TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS with SeaVGABIOS enabled. Text appeared correctly on screen and interaction with graphical comboot menu was successful. However, Linux cleared the framebuffer on boot, rendering the screen useless until Linux loaded its native xgifb driver. Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05southbridge/amd/pi: write_hpet requires additional config optionDave Frodin
This copies what was done in southbridge/amd/agesa in: commit 56f46d8 agesa/family15tn: Switch to per-device ACPI TEST: amd/lamar. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8288 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05southbridge/amd/pi: Update Kconfig and makefiles for boltonDave Frodin
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8287 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05southbridge/amd/pi: Add the bolton definitionsDave Frodin
This adds the PCI and interrupt related definitions for the bolton specific features. Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8286 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05AMD HyperTransport: Drop unused link optimisationKyösti Mälkki
Change-Id: Ia4398f6eb013c69838487bdd02d094f97d7224b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8342 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05AMD K8: Remove some excessive preprocessor useKyösti Mälkki
Tests on CPUID are valid regardless of revision. Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05newisys/khepri broadcom/blast: Drop duplicate entry in KconfigKyösti Mälkki
Keep the value that is listed first, it also the one with a more recent change. Change-Id: I0336c962544d75f94512563c08f280aa43c7a175 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8336 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05AMD8131: Remove obsolete directoryKyösti Mälkki
Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8335 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-04superio/fintek: Add required changes so F81216H can be usedDave Frodin
The amd/lamar mainboard is the first mainboard to use the f81216h. These changes are needed to fix up commit 27a63d77 so the Super I/O builds and functions correctly. - Wrong #include name - Removed global variable in romstage - Missing "case" in switch() Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8255 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03cpu/amd (non-AGESA): Remove terminator from microcode blobKyösti Mälkki
Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selectionKyösti Mälkki
Include microcode updates in CBFS for every CPU revision the platform can support, as changing to different CPU revision should not require a coreboot rebuild. This increases CBFS usage from 2 kB to 14 kB. Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4521 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-03cpu/amd (non-AGESA): Load microcode updates from CBFSKyösti Mälkki
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4502 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03cpu/amd/model_10xxx: Remove UPDATE_CPU_MICROCODE optionAlexandru Gagniuc
This option is now deperecated by loading microcode updates from cbfs. Remove this option in anticipation of implementing CBFS loading for AMD cpus. Removing it beforehand results in less patch overhead. Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8322 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03nvidia/ck804: make Message Signaled Interrupts workJonathan A. Kollasch
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable HT MSI Mapping so that MSIs work. Prior to this change PCIe devices downstream of the CK804 with MSI enabled would fail to actually assert their interrupt. Tested on msi/ms7135 and winent/mb6047 running Debian GNU/Linux 7.0 (wheezy). Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8276 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-02src/arch/*/include/stdint.h: Provide definitions for bool typeAlexandru Gagniuc
Although bool normally belongs in stdbool.h, for our use cases, providing these definitions in stdint.h is acceptable. Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8279 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-01winent/mb6047: switch to CAR version of ck804 early_setup.cJonathan A. Kollasch
Change-Id: I9b45b7fbd862a5600ead7ad4e623a8a87ae364aa Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8319 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01winent/mb6047: clean up includes in acpi_tables.cJonathan A. Kollasch
Change-Id: I63bdc856fa4232cd66ff2e48e39c2cdb97bb88d3 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8316 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01winent/mb6047: use correct ACPI SCI interrupt triggerJonathan A. Kollasch
Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8315 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-02-01winent/mb6047: drop inaccurate comment in acpi_tables.cJonathan A. Kollasch
Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8314 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.Vladimir Serbinenko
Fixes USB3 ports degraded to USB2 speeds. Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/8313 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-02-01bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.Vladimir Serbinenko
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/8312 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSPYork Yang
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/8107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-31FSP platforms: Clear area in CAR for cbmemMartin Roth
This patch clears the CAR area. The FSP loads the entire CAR area with a pattern instead of clearing it. At least the cbmem area needs to be cleared or cbmem will not use it. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8195 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devicesTimothy Pearson
Test: Single Opteron 2419 with 1GB RAM in slot A1 Booted Ubuntu Linux 14.04 and verified all 6 cores were visible Brief stress test of all 6 cores simultaneously Verified proper ACPI power states for all 6 cores Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8311 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-31cpu/amd (non-AGESA): Fix AP crash during microcode version lookupTimothy Pearson
Move mapping tables to struct and prevent OOB array access that was crashing the APs during CAR initialization. Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-31amd/amdfam10: Update name table with Opteron 2400/8400 series codesTimothy Pearson
Change-Id: I52587c0c0dffd814d39087475b8f14c500a68933 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8309 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-31vendorcode/amd/agesa/f14: update microcodeNicolas Reinecke
05000028 -> 05000029 tested on asrock E350M1 05000101 -> 05000119 Change-Id: Iccb096eb55a4a789c1e810f68c8c8eacfd5f8a0b Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8296 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31mainboard/lenovo/t420s/Kconfig: select NO_UART_ON_SUPERIONicolas Reinecke
same as 37130ebdabe44989787aadeafbe79524970dec75 Change-Id: I73feed3a077dfcc61634147775df1e05fdb97e8b Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8278 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31intel/model_2065x: update microcodeNicolas Reinecke
Change-Id: I6c13518d2217bc823d409ab800bca011e76e9f25 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8277 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31southbridge/intel/bd82x6x native usb init: replace some magic valuesNicolas Reinecke
Some magic numbers are documented in the PCH datasheet so use them. Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8307 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31lenovo/t530/romstage.c: add usb port description and missing oc configNicolas Reinecke
OC2 at port 4 was missing. Verified with RCBA dump. Change-Id: Ide5701d53aeee28619204c7ac408662626aa11e4 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8304 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31lenovo/t5x0: Make version look like something thinkpad_acpi would acceptNicolas Reinecke
thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. same as http://review.coreboot.org/4650 / 63acd22dc5366c72a7165138f5030df9523824dc Change-Id: I82d7a2b9f2ec56557b3a9c26d1af57ed39e31850 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8302 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-30devicetree: Search PnP device node from the tree by pathKyösti Mälkki
Copied from device_util.c with added ROMSTAGE_CONST. Change-Id: If872631ed96a79b9a0b15e09382d6f81098c8db3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8297 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-29asus/kfsn4-dre/Kconfig: Enable power on after power fail by defaultTimothy Pearson
Change-Id: I655843c78d31cc69a007ddaf9b51cde063c48c79 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8299 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-29drivers/intel/fsp: Add find_saved_temp_mem()Martin Roth
Add a function to retrieve the location of the CAR temporary memory that was saved by the FSP into the HOB structure. Change-Id: I2635de5207cd699740721d333a7706425b837651 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8194 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-28mainboards: Add support for the Asus KFSN4-DRE series of motherboardsTimothy Pearson
Status: Tested with KFSN4-DRE PCB v1.04G Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work. Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank). Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1. AMD PowerNow! functions correctly via ACPI. Video, network, USB, SATA, and serial have received thorough testing. Tested with KFSN4-DRE PCB v1.05G Single Opteron 2419 CPU tested with 1GB RAM in slot A1. Booted to PXE configuration menu; not tested further. Known issues: RAM initialization is a bit flaky with multiple high-density modules; this could be a generic MCT training issue but is probably bad hardware. The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device works after Linux boots and initializes the device. Suspend/resume functions at the S1 level but sometimes hangs on resume. Wake on LAN can be flaky; the strap(s) needed to have WoL work on power application were not physically installed by ASUS so the board needs to boot at least once after power application before it will work. Change-Id: I0709f822eea8ed877f55db9443143028a5400472 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8270 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-28amd/amdfam10: Allocate the lower DRAM region up to TOMTimothy Pearson
This fixes the resource allocator locating the PCI register space below 0xe0000000 thereby causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems. Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8261 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-28nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objectsTimothy Pearson
Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8285 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28nvidia/ck804: Add ability to override CK804 base unit IDTimothy Pearson
Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8273 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-28amd/amdfam10: Add runtime ACPI _PSS generationTimothy Pearson
Skeleton and ACPI generator interface taken from model_fxx powernow_acpi.c Small portions of FIDVID MSR code taken from model_10xxx fidvid.c Nearly completely rewritten for the P-state-based K10 CPU TEST: KFSN4-DRE with dual Opteron 8356 CPUs Verified CPU per-core dynamic state change with system load Verified reported P-state count and frequencies Stress-tested each CPU (all cores simultaneously) to verify proper P0 transition and configuration. Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8284 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28nvidia/ck804: Fix FTBFS with AMD Family 10h systemsTimothy Pearson
The build failure stems from a missing function being called via a chain including setup_ss_table(), set_ht_link_ck804(), and st_ht_link_buffer_counts_chain(); the latter function is only available in the AMD K8 code. It appears that a bunch of K8-specific code snuck into the CK804 and MCP55 southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0. Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8269 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28nvidia/ck804: Add ability to enable/disable PCIe PME# wake eventsTimothy Pearson
Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8283 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28nvidia/ck804: Fix cosmetics in KconfigTimothy Pearson
Change-Id: Ic675911f534f07516c838b52c9463e89448d4353 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8291 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28nvidia/ck804: Add ability to bypass register 0x78 initializationTimothy Pearson
On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost immediate soft reset. Leaving the register at its power-on default value appears to have no ill effect on that same board. Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8272 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-28amd/amdfam10: Enhance resource debugging when enabledTimothy Pearson
Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8266 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-28northbridge/amd/amdht: Initialize variable `currentBUID`Timothy Pearson
Fix uninitialized variable when manual non-coherent BUID selection is used. Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8267 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-28amd/amdfam10: Serialize mutable ASL methodsTimothy Pearson
Fix three IASL warnings in ASL utility code by making the methods `GWBM`, `GWEM` and `GIOR` serialized. TEST: Built and booted on ASUS KFSN4-DRE. Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8264 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEMTimothy Pearson
Remove declaration of unused variable `io`. Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8265 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INITKyösti Mälkki
We can now create CBMEM with dynamic allocation even if CBMEM location is resolved late in ramstage. Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7861 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Change some types to uintptr_tKyösti Mälkki
Change-Id: Ib2158c866067f9e2e9bfcf4b117eb8b7a2a819c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8191 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Tidy up CAR migrationKyösti Mälkki
Move the CAR migration call to arch -specific part of CBMEM init, it is truly a x86 specific thing. Change-Id: I715417e54f197b8745e0670d6b900a5660178141 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7860 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Tag chipsets with LATE_CBMEM_INITKyösti Mälkki
In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7850 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM console: Fix and enhance pre-RAM supportKyösti Mälkki
Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Add timestamp_reinit()Kyösti Mälkki
This avoids the need for separate timestamp_reinit() calls made via CAR_MIGRATE() that is not implemented for ARM. Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8033 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM console: Fix CAR migration stepKyösti Mälkki
With the change it becomes irrelevant if memcpy() car.global_data or cbmemc_reinit() is done first. Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8032 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Implement cbmem_run_init_hooks() stubKyösti Mälkki
Until we completely can unify early_variables, use these to handle CBMEM update hooks for both romstage and ramstage. For x86, CAR_MIGRATE serves the purpose of romstage hooks. Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7876 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27intel: Drop romstage handoff via scratchpadKyösti Mälkki
If HAVE_ACPI_RESUME ever gets implemented, use CBMEM handoff instead. Change-Id: I77463988fa5324c729579902f4796be4da15d551 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8182 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27drivers/intel/fsp: Add HOB tools to work with GUIDsMartin Roth
Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27southbridge/amd/pi: Clean up whitespace in KconfigDave Frodin
Change-Id: I4dbccc7d132a14a71107f24124814d30d93d6ece Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8252 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27southbridge/amd/pi: Rename Avalon to HudsonDave Frodin
To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27northbridge/amd/pi: Correct the path to an #includeDave Frodin
Change-Id: Ibf0bd494b2022272cb2d5c4ddb1bdf82ea70ca50 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8250 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27southbridge/amd/pi: Correct several path namesDave Frodin
Change-Id: I247c17516cd06970185e271eccb78528a8de01c1 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27southbridge/amd/pi: Correct several yangtze/avalon typosDave Frodin
These were probably accidentally missed when the move from southbridge/amd/agesa/hudson to amd/pi/avalon occured. Change-Id: I4cf6e2f8b25899d6d342452cb1b15e694dae35c8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27AMD Bald Eagle: Add binary PI vendorcode filesBruce Griffith
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. This fix changes the makefile so that the AGESA dispatcher is built using its own rules rather than generic library generation rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA source files are initially copied from whereever they live into coreboot/build/agesa. They are compiled from there. The binary PI directory now has a mandatory structure that places the AGESA BLOB into the same directory as the support headers. These will nominally be placed in the amd directory in SageBIOS or the 3rdparty directory in coreboot.org. Change-Id: I56788cd197159939b64c7d16c1d32418f8cc2197 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27amd/amdht: Compile in multiprocessor support when selectedTimothy Pearson
Fix multiprocessor support not being compiled in when selected via Kconfig on AMD systems. Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8268 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systemsTimothy Pearson
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 Reviewed-on: http://review.coreboot.org/8259 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-27rmodule: Correct the typecast with proper parenthesisFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I67801f96ec63a3150263ce3d6a4a7556092c6be5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209505 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 71cd62740e150cb5b5adc1b20c7f13fa8c51b7e3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0c3f5f10a3af7028728dadca539681a081d858e0 Reviewed-on: http://review.coreboot.org/8237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-27vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integrationDaisuke Nojiri
vboot2 abtracts tpm storage as some 'secure' space. Thus, it's firmware's responsibility to handle vboot specific operations with tpm. This CL just copies related files from vboot_reference so that we can see how code was modified in the next CL. Note rollback_index.c/h were renamed to antirollback.c/h. TEST=none BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I1792a622058f70a8fcd3c4037547539ad2870420 Original-Reviewed-on: https://chromium-review.googlesource.com/206462 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 2ae188b29242bf09c5e79e31f98b330a30bf7b93) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5fa5a636003e8472127194e961fea4309489b1d9 Reviewed-on: http://review.coreboot.org/8164 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot_wrapper: handling VBERROR_TPM_REBOOT_REQUIRED from VbInit().Kevin Cheng
Doing reset while VBERROR_TPM_REBOOT_REQUIRED occured. BUG=chromium:389568 TEST=Manual force VBERROR_TPM_REBOOT_REQUIRED returned from VbInit() and system will reboot. Original-Change-Id: I9d7c4b3a380a931a728f792b4013b3b9bf65dfae Original-Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206337 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 32728dd9fc43a95d6f763a85f9cc7a660a66b175) Original-Reviewed-on: https://chromium-review.googlesource.com/206948 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 1ea5e233386d236ce20f3d1695fac3a1bc49d4bd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib93fdf7b22918f563d3e29207a75fc831bee186a Reviewed-on: http://review.coreboot.org/8163 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: read dev and recovery switchDaisuke Nojiri
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa Original-Reviewed-on: https://chromium-review.googlesource.com/206064 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1 Reviewed-on: http://review.coreboot.org/8162 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: implement vb2ex_read_resourceDaisuke Nojiri
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I633f9dddbf8b2f25797aacc246bcebaafb02bea4 Original-Reviewed-on: https://chromium-review.googlesource.com/206063 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 1f215672de31847cc647e83d2c04633b7f8dfa33) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I57f449b052132b300f7bca4351871c539a7a8694 Reviewed-on: http://review.coreboot.org/8161 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri
This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 Reviewed-on: http://review.coreboot.org/8160 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27nvidia/ck804/lpc.c: Fix power restoration controlTimothy Pearson
Control bits located by changing tristate power restoration value in proprietary BIOS, booting into Linux, dumping the entire CK804 configuration space, then comparing values against those dumped earlier. "Last state" control bit(s) are unknown at this time. TEST: Boot ASUS KFSN4-DRE with both coreboot power on and power off after power failure settings, then pull power plug / reinsert power plug and verify mainboard behaviour matches setting. Change-Id: I737bdd35632fe786968a1cb8458e56c785363cfa Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8258 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-26rush: Add support for rush boardFurquan Shaikh
Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Reviewed-on: http://review.coreboot.org/8041 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-26tegra132: Add support for tegra132 socFurquan Shaikh
Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Reviewed-on: http://review.coreboot.org/8040 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26arm64: Prepare ARM64 for buildingMarc Jones
There were a number of issues with the ARM64 build files. This patch ports the following changes from ARMV4/V7 to ARMV8: - make armv8 Kconfig options consistent with armv4/v7 - fix build include issues in boot.c, tables.c, and early_variables.h by matching armv4/v7. Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iacd95d336559c45458784d1da67bde62a0956620 Reviewed-on: http://review.coreboot.org/8236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26xcompile: Rename aarch64 to arm64Marc Jones
coreboot toolchain.inc uses the ARCH_SUPPORTED variable set by xcompile. This change allows for consistent naming in the toolchain.inc generated variables. Change-Id: Iafed06cf2d19a533f99e10b76aca82adc3e09fa8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8235 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-26toolchain.inc: Check toolchain is installed before running itMarc Jones
Toolchain.inc fails with strange shell errors if the CC_$(stage) doesn't expands correctly. The cause is that the ARCH_SUPPORTED doesn't have the required toolchain for the stage. Change-Id: Id284ce281546b2b1b166f2b13d087bc6b114440e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-25northbridge/amd: Add Kconfig options for ECC redirectionTimothy Pearson
Change-Id: I83e7605650b13e82a2e6c2822cbd237b4e473b5d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8271 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-25northbridge/amd: Add Kconfig options for ECC scrub rateTimothy Pearson
Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8263 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-24device/hypertransport.c: Fix typo in commentTimothy Pearson
Change-Id: Ib63a8b6e7f4663926104426992f6dea9ee3510b0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8262 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-20device/oprom/realmode/x86: Fix memory corruptionZhuo-Hao Lee
The length of the memcpy is incorrect and this will cause the destination buffer to corrupt the following 2 bytes of data. BUG=none BRANCH=All TEST=build and boot on rambi, system boot up without error Change-Id: I96adf2555b01aa35bb38a2e0f221fc2b2e87a41b Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee@intel.com> Reviewed-on: https://chromium-review.googlesource.com/237510 Reviewed-by: Ryan Lin <ryan.lin@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> [Remove usage of macro `FIELD_SIZEOF(t, f)`.] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8227 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-01-19samus: Update indices of ramstage and refcode blobsRandall Spangler
This must be committed at the same time as the corresponding depthcharge change which updates the fmap. BUG=chrome-os-partner:30079 BRANCH=none TEST=Build samus firmware. dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and PD_MAIN_B sections. Boot samus. 'crossystem mainfw_act' -> A As root, 'crossystem fwb_tries=1' Reboot samus. 'crossystem mainfw_act' -> B CQ-DEPEND=CL:208984,CL:*169850,CL:208989 Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208899 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837 Reviewed-on: http://review.coreboot.org/8219 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Delay bringing SSD out of resetDuncan Laurie
In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Disable self refresh and MRC cache on broadwellDuncan Laurie
Add workarounds for power and/or lpddr3 issues on Broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208154 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3 Reviewed-on: http://review.coreboot.org/8214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-19samus: Enable keyboard backlightDuncan Laurie
- Turn on keyboard backlight early in boot (not resume) path as a sign of life for the system - Add ACPI device for keyboard backlight so the kernel can find and make use of it BUG=chrome-os-partner:30586 BRANCH=None TEST=build and boot on samus Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208152 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4 Reviewed-on: http://review.coreboot.org/8213 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-19samus: add acpi resource for supporting RT5677 codecKane Chen
Add codec acpi resource for supporting RT5667 codec. BUG=chrome-os-partner:29649 TEST=emerge-coreboot successfully checked codec device is probed Original-Change-Id: I739c0dbfdbfa221b06f99c3d934825b640096c6b Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207707 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit f9698c45a47efe7fd2a1f5432640f3db5e4bd3f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib14b27421613d747e02037ecd2311d9966a5d813 Reviewed-on: http://review.coreboot.org/8212 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-17asrock/e350m1: Fix PCIe slot for x4 cardsKyösti Mälkki
Configuration for GNB GPP was incorrect, only PCIe x1 cards worked. Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8229 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-163rdparty: Update to latest commit in blobs repositoryDave Frodin
'blobs' now contains the update for the BaldEagle binaryPI. Change-Id: I7ed423b17cee926205792223d6355277bedad552 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen
Due to some projects don't have the correct settings in devicetree.cb so put this change in case those projects without are setting in devicetree.cb BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly even there is no setting in devicetree Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209051 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 713f809952a2d8da434d619d48cb7ddce1991925) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede Reviewed-on: http://review.coreboot.org/8218 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16rambi: configure USBPHY_COMPBG by the setting in devicetree.cbKane Chen
USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly CQ-DEPEND=CL:208557 Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208731 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75 Reviewed-on: http://review.coreboot.org/8217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen
USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208557 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795 Reviewed-on: http://review.coreboot.org/8216 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16rmodule: Fix 64-bit related typecast errorsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I5687c24fcecd26e7656317eb8dde0f1f798e49fc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209335 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 707cb3e274aa7eabc8e1792fc09d05b4c9e95913) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a40acbb14a5ba5c6e4d552b67a331256567d5b4 Reviewed-on: http://review.coreboot.org/8220 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-16coreboot tpm: Fix printk format specifiersFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I828776724dce287d9a7eb732f2c9ecccf8d68229 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209336 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b50c9441ddaeabc5aa039f2141853ed7ba7a9d5b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6e81312609448c531345e592ee371ea53dc0916c Reviewed-on: http://review.coreboot.org/8221 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 17:30:12 +0000