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2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/nissa: Create joxer variantMark Hsieh
Create the joxer variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:236086879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_JOXER Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2022-06-17soc/intel/denverton_ns: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-17soc/intel/xeon_sp: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-06-17soc/intel/skylake: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I40294339c79f5db1850ccd546292c67169890b2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65161 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/nissa/var/pujjo: Generate SPD ID for supported memory partLeo Chou
Add pujjo supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP, K3LKCKC0BM-MGCP 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6E 3. Micron MT62F512M32D2DR-031 WT:B BUG=b:235765890 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I929527a219452082e416803f7a74d470be5a188c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65100 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCPLeo Chou
This adds support for Samsung K3LKCKC0BM-MGCP LP5 chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=None BUG=235664831 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I49cea0594f8a94aa7efbb375ea1c28b5d1136498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/brya/var/agah: Remove stop pin declaration for LANTony Huang
Currently, the system fails to enter S0ix as the stop pin declation for LAN device will prevent system from entering suspend. So remove the stop pin declaration. Also add device_index=0 for the first NIC to get correct MAC from VPD setting. BUG=b:210970640 TEST=Build and suspend_stress_test -c 20 pass Check LAN works fine after resume Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17cpu/Makefile.inc: Fix rebuilding a new targetArthur Heymans
When switching to different board, 'make clean' needs to happen because not everything gets properly regenerated. Microcode updates are among those. You could end up with the microcode updates from the previous build which can be incorrect. Adding $(DOTCONFIG) as a dependency which gets updated when you change something in Kconfig fixes this. TESTED: swap between boards that use different microcode and see that the size changes. Change-Id: Id1edecc28d492838904e3659f1fe8c9df0a69134 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65148 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-17mb/supermicro/x9sae: Correct mapping of HDMI portsBill XIE
The two HDMI ports on x9sae(-v) prove to be wired to HDMI2 and HDMI3. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I07870fd70612c9ed01a833f173b18053807ad2b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-17mb/google/nissa/var/craask: Enable Elan touchscreenTyler Wang
Add Elan touchscreen support for craaskvin. BUG=b:235919755 TEST=Build and test on MB, touchscreen function works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I18e0be688705942647c42ee532fcd32e862fe78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Add ALC5682I-VS codec supportTyler Wang
Add ALC5682I-VS related settings. And add codec/amplifier space in fw_config. BUG=b:229048361, b:235436515 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I567d3567318c810e19ae9e9ba5e0dc8332517866 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa/var/craask: Disable SD card based on fw_configTyler Wang
Use fw_config Bit 5 to control whether to disable SD card: Bit 5 = 0 --> enable SD card Bit 5 = 1 --> disable SD card BUG=b:229048361 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17mb/google/brya/var/banshee: Update gpio configurationFrank Wu
Update gpio configuration based on GPIO_0610b.xlsx. BUG=b:226182106, b:226182090 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I2b447629645690e5e97a17fff25860838f4f3344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-06-17payloads/LinuxBoot: Use wildcardsArthur Heymans
If no directory is found then no harm is done either. Change-Id: I0842ec106f11eca80bf01fd4771e1dfc4588b3fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-16util/cbfstool/common.c: Deduplicate buffer_create() logicEdward O'Callaghan
BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: Id7d9b6f5254b08720eebb37151e12ee68ed7f8d7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65145 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16util/cbfstool: Decouple elogtool from vboot_ref flashrom codeEdward O'Callaghan
Currently elogtool sub-proccesses flashrom as calling libflashrom requires a missing function from the previous flashrom release. Pending a new release of flashrom we must continue to use subprocess. However the current subprocess wrapper implementation lives in vboot_reference which is a git sub-module of coreboot. This causes all sorts of grief keeping a subprocess ABI stable from vboot_reference when the rest of vboot_reference builds of HEAD of the flashrom tree (i.e., using unreleased libflashrom functions). In order to not keep finding ourseleves in a bind between the two separately moving trees with different build environments, decouple elogtool with its own mini copy of flashrom subprocess wrapping logic. Squash in, util/cbfstool/elogtool.c: Convert args into struct in flashrom helper vboot signatures for flashrom r/w helpers changed in the upstream commit bd2971326ee94fc5. Reflect the change here to allow vboot ref and coreboot to realign. BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: I04925e4d9a44b52e4a6fb6f9cec332cab2c7c725 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-16libpayload/libcbfs: Fix file hash checkYu-Ping Wu
Fix the buffer pointer passed to cbfs_file_hash_mismatch(). Add a test case with LZ4 compression, which would catch the bug we are fixing. Change-Id: I36605e2dbc0423fa6743087512f2042b37c49d35 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-16mb/google/peach_pit: Select BOOT_DEVICE_NOT_SPI_FLASHYu-Ping Wu
CPU_SAMSUNG_EXYNOS5420 has its own boot device implementation (src/soc/samsung/exynos5420/alternate_cbfs.c), so BOOT_DEVICE_NOT_SPI_FLASH should be selected. Change-Id: I0a9f96ad68b28773ede4e99510bd33867789e185 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65109 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16mb/google/brya/vell: Implement variant_devtree_update() for audioeddylu@ami.corp-partner.google.com
Different board versions have different audio layouts, therefore support both layouts by enabling only the appropriate devices in the devicetree via board_id(). BUG=b:207333035 BRANCH=none TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991 Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124 Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16mb/intel/adlrvp: Add 5G WWAN ACPI support for ADL-P RVPCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. PCIe root port: 6 (1 based) clock source & request: 5 (0 based) GPIOs: WWAN_PERST_N: GPPC_C5 WWAN_RST_N: GPPC_F14 WWAN_FCP_OFF_N: GPPC_F15 WWAN_WAKE_N: GPPC_D18 WWAN_PWREN: GPPC_F21 WWAN_DISABLE_N: GPPC_D15 CLKREQ5_WWAN_N: GPPC_H23 TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I10902245e3a5e05cd2af9030394933e936c25396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63941 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/common: support for configurable memory regions claimed by SAEran Mitrani
see https://review.coreboot.org/c/coreboot/+/65072/8 BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary MSR definitionJeremy Compostella
MSR_VR_MISC_CONFIG2 is not used by AlderLake code. TEST=compilation check Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/alderlake/Kconfig: Unselect IPU for ADL-SMichał Żygowski
Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15ec/google/chromeec: Add property to denote mux mode switchPrashant Malani
On some systems, the Chrome EC controls both the USB Type-C mux as well as the retimer. Introduce a boolean property "mode-switch" to denote switches which act as a mode-switch. BUG=b:235834631 TEST=None BRANCH=None Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15libpayload/Makefile.payload: Fix CFLAGSNico Huber
GCC_CFLAGS_<arch> contains only the flags that are GCC specific, iow. flags that don't work with Clang. CFLAGS_<arch>, OTOH, contains all flags that should be used and auto- matically includes GCC_CFLAGS_<arch> if GCC is selected. Change-Id: I5ec15f169d51c7a32ca86e54a98a2ce0e3b51e6d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62248 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15libpayload/Makefile.payload: Include libpayload's .configNico Huber
It's required to tell xcompile what compiler to use. Change-Id: I9f1ddef96a20df1d83bfd4883b2e006ba78ce7c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2022-06-15libpayload/Makefile.payload: Revise config strategyNico Huber
Payloads often just use one of the defconfigs for libpayload. When the `Makefile.payload` was introduced, it also added dependencies to pass a `make oldconfig` or `make defconfig` for the payload on to libpayload. Turned out, this creates some dependency madness when, for instance, `make oldconfig` gets called without a libpay- load `.config` available, or when we try to include the `.config` in the `Makefile`. To make things worse, Kconfig's `Makefile` that is imported from Linux contains some rarely used paths that are generally incompa- tible to our environment. So let's get rid of the hard-to-control automatism. Payloads that don't want to use a libpayload defconfig need to clear the `$(LIBPAYLOAD_DEFCONFIG)` variable and manually run the respective config target to generate a `.config`. To fully support this, the rule to create a `.config` via `defconfig` is guarded by `$(LIBPAYLOAD_DEFCONFIG)`. Otherwise we'd have a spurious, broken recipe when the variable is unset. We keep the option to call libpayload targets with an `lp-` prefix for convenience. The existing, explicit targets `lp-defconfig` and `lp-oldconfig` are replaced with a pattern match, so all config and other targets should work. Change-Id: Ie3fcce58d98e248c7182cd47f2a797fe066dd18a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2022-06-15soc/intel/common/acpi: Fix warning in ASLVarshit B Pandya
Warnings are treated as errors in build. UBAR is declared inside APRT method which throws warning as follows "Static OperationRegion should be declared outside control method" Move UBAR outside APRT method to fix warning. TEST=build brya with following changes without any warnings 1. Select ACPI_CONSOLE 2. Include <soc/intel/common/acpi/acpi_debug.asl> 3. Add APRT function in any asl file. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I40c676fd0bbd529bcbded18dd248b918f47324d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-06-15mb/google/brya/var/crota: Enable VNN_1.05v_bypass railTerry Chen
Some SKUs of crota have VNN 1.05v bypass rails for additional power savings in S0ix states. This patch uses FW_CONFIG to enable that feature when run on the applicable SKUs. BUG=b:233175019 BRANCH=none TEST=emerge-brya coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15cpu/x86/smm/smm_module_loader.c: Fix formatted printElyes Haouas
This fixes following errors when building GA-945GCM-S2L with clang 14.0.5. CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:180:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), i); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:184:20: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] __func__, region_offset(&cpus[0].stub_code), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:185:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), size); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:349:52: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] printk(BIOS_DEBUG, "%-12s [0x%lx-0x%lx]\n", name, region_offset(&region), ~~~ ^~~~~~~~~~~~~~~~~~~~~~ %zx src/cpu/x86/smm/smm_module_loader.c:350:9: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_end(&region)); Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I59f20aacf91cb50fb194a84082a643b34c6c1ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65154 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/brya/var/brya4es: Enable CNVi ddr rfimVarshit B Pandya
enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature needs to be enabled for all brya variants. Currently, it's not enabled for brya4es. BUG=b:201724512 TEST=Build, boot brya4es and check function 3 in _DSM method under \_SB.PCI0.WFA3 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/nissa: Increase I2C bus frequency to around 390 kHzReka Norman
- Set the speed to I2C_SPEED_FAST in each speed_config so that the speed_config is actually applied. Currently, the speed_config isn't applied, so the hcnt/lcnt calculation falls back to rise_time_ns and fall_time_ns, which are 0 since they're not set. This results in frequencies around 300 kHz. - Move the data hold time to the speed_config, ensuring that the resulting sda_hold value remains the same. - For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to give a frequency around 390 kHz. - In the baseboard, keep default scl_lcnt and scl_hcnt values. These work well for buses with a rise time around 100 ns, and can be used as a starting point before tuning them for a specific variant. BUG=b:229547183 TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks and nereid and check they meet the spec. nereid clock frequencies: I2C0 - 387.9 kHz I2C1 - 392.7 kHz I2C3 - 386.3 kHz I2C5 - 383.6 kHz nivviks clock frequencies: I2C0 - 387.67 kHz I2C1 - 380.47 kHz I2C2 - 388.51 kHz I2C3 - 384.03 kHz I2C5 - 389.09 kHz Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15mb/google/dedede/var/shotzo: Generate SPD ID for supported partsTony Huang
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: - MT53E512M32D2NP-046 WT:E - H9HCNNNBKMMLXR-NEE - K4U6E3S4AA-MGCR - MT53E512M32D1NP-046 WT:B - H54G46CYRBX267 - K4U6E3S4AB-MGCL - K4U6E3S4AA-MGCL BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com>
2022-06-15mb/prodrive/hermes: Add BIOS menu control via EEPROMLean Sheng Tan
Introduce a new field in the board settings EEPROM region to control whether BIOS menu is to be enabled. This field will be used in EDK2 payload. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I0af81c9e70a0088caea6bc7e2b81eab9a123c0f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-06-14mb/google/brya/var/agah: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A2 | | A0 C2 | | C0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/google/brask/variants/moli: change clk_src and clk_req for LAN_I225VRaihow Shi
change clk_src and clk_req to 4 for LAN_I225V based on ADL_Moli_SC_MB_20220601.pdf. BUG=b:235768639 TEST=emerge-brask coreboot and check LAN_I225V can connect. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: Remove the cnvi_bt_audio_offloadRaihow Shi
Remove the cnvi_bt_audio_offload because it is already probed in variant.c for moli. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/google/brask/variants/moli: enable use_custom_pldRaihow Shi
enable use_custom_pld to match the custom physical location define. BUG=b:235426221 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I62d133eed02faf4e5ad054a0901f73b1196c4c6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-14mb/hp/snb_ivb_laptops/Kconfig: move common option to commons sectionPeter Lemenkov
Apparently all nine HP Sandy/Ivy laptop variants select MAINBOARD_USES_IFD_GBE_REGION. So let's move it to the COMMON section. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I48e0d03c59d3ba013b479b59df8a15a0f8d23c50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-14soc/intel/cmn/cpu: API to initialize core PRMRRSubrata Banik
This patch implements API to sync between core PRMRR(Processor Reserved Memory Range Registers). Read PRMRR base and limit value from BSP and apply it on the rest of the cores. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-14mb/intel/adlrvp: Add new upd setting for ADL RVP with Raptor LakeBora Guvendik
Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only upd for adlrvp with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-14mb/amd/chausie/Kconfig: enable PCIe power managementFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24a502994d24f3341273c5e6f768687ad20baf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65113 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/amd/chausie/devicetree: add PCIe clock output configurationFelix Held
The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2Ronak Kanabar
In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) provides more granular information regarding Die, package etc. coreboot uses V2 to in order to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and observe system boots (no hang). Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-14external/LinuxBoot: Fix cleanup mechanismPatrik Tesarik
`make clean` never thoroughly removed LinuxBoot build artifacts. This change checks for kernel directories present in the project directory and deletes all of them, if found. Signed-off-by: Patrik Tesarik <patrik.tesarik@9elements.com> Change-Id: Ia056ac6608e3631dfc270ba5c2f32216c3e1ac50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65098 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14external/LinuxBoot: Kconfig defaults to systembootPatrik Tesarik
In addition to change CB:40316 this commit proposes a change of default behavior inside of the LinuxBoot toolchain. Currently the defaults build a LinuxBoot payload which boots into the u-root shell and waits for input. In fact it does not deliver any bootloader with it, but the build image is on the other hand rather small. This commit changes the defaults in a way that the LinuxBoot bootloader will actually be able to boot a local or remote system image. In consequence the build payload size is rather big, but accepted for a working out-of-the-box startup behavior. See discussion on that topic in the above mentioned change. Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Change-Id: Ieaba7e523aef10c467a8bea29ae323e22324b225 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40527 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14util/mb/google: add support for nissaShou-Chieh Hsu
Add the file template for creating a new variant of Nissa. BUG=b:229550821 Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com> Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-13mb/google/volteer: Fix wrong Type-C port for retimerDerek Huang
This change fixes wrong type-C port number for voxel. Voxel uses tcss_usb3_port1 not tcss_usb3_port3. BUG=b:231344977 BRANCH=volteer TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64022 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-13util/liveiso: Update to NixOS 22.05Felix Singer
Update configs for NixOS 22.05. pulseaudio-modules-bt has been abandoned, and is superseded by pulseaudio's native Bluetooth functionality. Thus, remove it. Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-13soc/amd/sabrina: only make the available clock outputs configurableFelix Held
Sabrina only has 4 PCIe clock outputs with corresponding clock request pins available, so only make those 4 configurable in devicetree and disable the rest unconditionally. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-13payloads/external/LinuxBoot: Adopt u-root changePatrik Tesarik
The u-root toolkit dropped the original uinit bootloader in the master branch and respectively the systemboot-option in templates.go. In consequence the LinuxBoot builds will boot into the u-root shell and waiting for input. This commit enables the reuse of the -uinitcmd flag to specify a command, which runs after the u-root init-process. Systemboot as a bootloader wrapper will mimic a BIOS/UEFI boot device selection. Other preselections, i.e. stboot and boot2 are implemented as well. Custom strings or programs can be set as well, but they cannot contain program flags. E.g. 'fbnetboot -class linuxboot' will not work, because they aren't symlinkable. This commit and its respective LinuxBoot builds with systemboot, none and one custom option have been tested successfully on a UP squared single board computer with the intended behavior. Change-Id: I4ac3409040ea77a1836f90f43fba07d2cd05a952 Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-13external/LinuxBoot: Deprecate GOPATH in u-rootPatrik Tesarik
This is a breaking change for now when using latest u-root main, which is the default behavior in LinuxBoot. u-root switched to golang modules and therefore `go get` is not the standard behavior anymore. The workaround for this is to pull the repository and build directly in the directory for now. Another apporach would be to use `go install $pkg@latest` to install the binary at that particular version into the golang binary path. Currently missing is a control structure to enable the build process for legacy versions <v0.8.0. Signed-off-by: Patrik Tesarik <patrik.tesarik@9elements.com> Change-Id: Ifa03504da6fa321ffc6d2506b27ebd2e3ed9961b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65090 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-06-13mb/google/dedede/beadrix: Update SoC gpio pin of I2C cameraTeddy Shih
Update SoC GPIO setting of unused I2C camera pins according to beadrix schematics. GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA) GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL) BRANCH=dedede BUG=b:235005592 TEST=on beadrix, validated by beadrix's camera still working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12soc/intel/lpc: Set up default LPC decode rangesArthur Heymans
Intel LPC devices have generic and fix IO decode ranges. This CL is smarter about using generic ones, by using the fixed ones first. Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/dedede/beadrix: Update probe daughter LTE mainboard SARTeddy Shih
Update FW_CONFIG probe for daughter board LTE and mainboard SAR according to beadrix schematics. BRANCH=dedede BUG=b:226910787, b:213549229, b:233983127 TEST=on beadrix, validated by beadrix LTE working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-12mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByteFelix Held
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so it won't fit in the flash and makes soc_update_apob_cache return early before writing the APOB data from DRAM into the flash with this warning: [WARN ] RAM APOB data is too large 1db18 > 18000 Increasing the RW_MRC_CACHE size to 120 kByte fixes this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/corsola: Fix PS8640 power-on T6 sequenceRuihai Zhou
The T6 of PS8640 power on sequence should be larger than 0ms, but it's -0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640 power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx". BUG=b:235448279 BRANCH=None TEST=The sequence T6 is larger than 0ms when power on. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-12soc/mediatek: pass access mode to the payloadWenbin Mei
Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready state by sending CMD1 twice. If it is in the ready state, then the payload (for example, depthcharge) will not send CMD1, but the access mode is only available from the response of CMD1. Therefore, we need to pass the access mode to the payload by defining the following types: - MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode. - MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector mode. BUG=b:234672726 BRANCH=cherry TEST=boot ok Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-10mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0John Su
The TBT device can't be recognized after we re-plug it at DB type-c port. Intel found that tbt_pcie_rp0 has mapping error after each re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this problem and take this as short term solution. Intel will implement re-mapping mechanism in ACPI for long term solution. BUG=b:230141802 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61429033dfe64d67916167bb901bdd8246db953e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10soc/amd/sabrina: Update fw.cfg for new names and blobsMarshall Dawson
Make the config file reflect reality instead of using the old cezanne copy. TEST=Build chausie BUG=b:220848549 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10soc/amd/sabrina: Adjust whitespace in fw.cfgMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I591c6a69f0971c3f4fdb8bb54a7f54c948caa648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10soc/amd/sabrina: Update firmware config for soc nameMarshall Dawson
Modify the config file, consumed by amdfwtool, to use "sabrina" and "SBR" named files. TEST=build chausie using updated amd_blobs BUG=b:220848549 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-103rdparty/amd_blobs: Advance submodule pointerMarshall Dawson
This contains the following commits: * 89fae13 sabrina: Add placeholder blobs * 3c5b627 cezanne: Upgrade PSP to 00.11.0D.75 * 8966a32 cezanne: Update ABL to 0x23216071 * 50cb4af cezanne: Upgrade ABL to RABLCZN1C276070 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib92ac995eadd53b7c392790e8e36bab3dbb8a982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10mb/intel/adlrvp: Add 5G WWAN ACPI support for adlrvp_rpl_ext_ecCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/google/brya: Select SOC_INTEL_RAPTORLAKE for skolas variantsBora Guvendik
BUG=b:229134437 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: Select SOC_INTEL_RAPTORLAKE adlrvp_rpl_ext_ec variantBora Guvendik
BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I12eab0fe2a3c21011f50c72718514fbc90cbe658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10soc/intel/alderlake: Add Kconfig for Raptor LakeBora Guvendik
Until FSP for RPL and ADL align, mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP header with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10soc/amd/sabrina: change MAX_CPUS to 8Felix Held
The Sabrina APU has a maximum configuration of 4 physical cores with 2 threads each, so a total of 8 CPU cores. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10soc/amd/sabrina/mca: update MCA bank names to match the hardwareFelix Held
The MCA bank names were checked against PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b947e686a0306d4468203103f91107c15ececc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-10soc/amd/sabrina/Makefile: Support new Ucode patch namesFred Reitberger
Sabrina slightly changed the names of microcode patches. Adding a wildcard to support the new name without breaking current builds that are using the placeholder CZN binaries. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I86caf0ba5c15f64a9a1f0e76a3186919e5e761a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65069 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/chausie/ec: Set MS bit in SW02Fred Reitberger
Set the MS bit in EC SW02 register to enable s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10crossgcc/gnat.patch: Add additional gnatlib object filesNico Huber
Newer host versions of gnatbind miss these when building the cross gnat1 and gnatbind. Tested with the following host compilers with and without bootstrapping that the resulting coreboot images of three boards stay the same: * GCC 4.9.2 (Debian) * GCC 6.3 (Debian) * GCC 7.4 (Debian) * GCC 8.3 (Debian) * GCC 9.4 (Debian) * GCC 10.2 (Debian) * GCC 12.1 (ArchLinux) Change-Id: I09c6b3cc7b15f1c505acd3ec2c1959b101d6dfb7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65000 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10crossgcc/gnat.patch: Never treat warnings as errorsNico Huber
We used to disable individual warnings that are expected when building our GCC version with a newer one. Not all warnings can be disabled indvidually, though, and it's much easier to simply allow warnings. As a plus, we get the warnings in the log (in case anybody would ever look into it). Partially fixes building with host GCC 12.1. Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10soc/intel/apollolake: Let coreboot set the VendorID and Subsystem IDSean Rhodes
Set all FSP S UPDs that set IDs to 0, which allows them to be set by coreboot. Tested on StarLite Mk IV and LPC now has the correct device ID of 0x31e8, where previously it had 0x7270. The UPDs differ APL and GLK, but the ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I034c9dc9d81c4d775dfff0994c9a6be823689b1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-10mb/google/brask/variants/moli: correct ddi_ports_configRaihow Shi
1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let tcp0 and tcp2 can display 2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to enable DDC BUG=b:234521799 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/google/brask/variants/moli: enable USB retimerRaihow Shi
Enable USB retimer in moli overridetree. BUG=b:233869074 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVPCliff Huang
In Adl-P RVP, those interfaces are used as USB ports. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVPCliff Huang
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-10ec/google/chromeec: Add support to report fan speed via ACPISumeet Pawnikar
Add fan speed rpm control for DPTF based Active2 policy as per document #626708, by utilizing existing FAN0 variable from src/ec/google/chromeec/acpi/emem.asl#18. There is no corresponding EC change required for this policy support because EC fan code already exporting this rpm value using EC_MEMMAP_FAN for FAN0. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system and verify the fan speed in rpm under sysfs path cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm. Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09soc/amd/sabrina/acpi: Correct VID decoding on SabrinaFred Reitberger
Sabrina uses the SVI3 spec for VID tables which is incompatible with the SVI2 spec used on PCO/CZN. Move the defines from common to soc and update the decoding for sabrina. See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables TEST=timeless builds on mandolin/majolica for PCO/CZN build chausie and verify pstate power is correct in ACPI tables Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I915e962f11615246690c6be1bee3533336a808f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-09payloads/tianocore: Allow custom build parametersMichał Żygowski
Currently, custom TianoCore builds are allowed, but those may need different parameters. Add a Kconfig option to specify additional parameters to be appended to build command. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/google/dedede/var/shotzo: Deselect BASEBOARD_DEDEDE_LAPTOPTony Huang
Shotzo is not a laptop (it is a Chromebase), therefore deselect BASEBOARD_DEDEDE_LAPTOP. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/dedede: Create shotzo variantTony Huang
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-06-09mb/google/brask/variants/moli: remove mainboard_vbt_filename in ramstageRaihow Shi
mainboard_vbt_filename() is to decide which VBT to return, but moli only has one VBT, so it doesn't need this function. BUG=b:234521809 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
This patch provides an option for CPU programming where coreboot expected to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor LakeSrinidhi N Kaushik
Add header files generated from FSP 2173_00 source build for Meteor Lake platform. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/apollolake: Correct the maximum number of Heci devicesSean Rhodes
Both APL and GLK have 3 Heci devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09mb/google/brya: Create ghost4adl variantJack Rosenthal
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-09mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portIvy Jian
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`. The change is required to detect USB2 device on type-C port of Agah boards. BUG=b:233554817 TEST=build and test USB2 hub could be detected on both the Type-C ports. ================================================================= usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00 usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 3-3: Product: USB 2.0 Hub hub 3-3:1.0: USB hub found hub 3-3:1.0: 4 ports detected ================================================================= Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 20:51:43 +0000