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Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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If a board supports FW_CONFIG or ChromeEC CBI, the options should be
selected by the mainboard. These are not something that need to be a
choice to enable or disable in Kconfig.
The defaults are pointless, so remove them. The symbols default to no.
Correct the descriptions of FW_CONFIG_SOURCE_CBFS and
FW_CONFIG_SOURCE_VPD. They come after CBI and do not override any other
options.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icf170dc2ef790d6f5a897a9c7c2ea64033bf1dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83118
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fill in ec.h according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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The generated dsdt.asl and early_init.c files contained 2 consecutive
blank lines, so remove one of them.
Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI
table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can
only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is
being reused, without a size check, which works fine on the first boot.
However after reboot the XSDT pointer seems to be valid, even though the
checksum isn't. Since the XSDT then isn't reserved again on reboot, the
memory it's pointing to is reused by other tables, causing the
payload/OS to see an invalid XSDT.
Instead of corrupting the smaller existing RSDP, allocate a new RSDP
structure and properly fill it with both, existing RSDT and XSDT.
In addition return the correct length of allocated ACPI tables to the
calling code. It was ommiting the size of the allocated XSDT and SSDT.
TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine.
With this patch applied XSDT is always valid from the OS
point of view.
Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set PsysPL2 and PsysPL3 in addition to making adjustments
to PL2 and PL4 in order to prevent brownouts when we don't
have a battery or have an empty battery at boot time.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=flash
Able to successfully boot on a SKU1 with 45W, 60W+ adapters
and SKU2 with a 60W or higher type C adapter.
30W is still being worked on.
Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This commit simply adds support for a Do Not Disturb key. HUTRR94 added
support for a new usage titled "System Do Not Disturb" which toggles a
system-wide Do Not Disturb setting.
BUG=b:342467600
TEST=Build and flash a board that generates a scancode for a Do Not
Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux
kernel with patches[0] that add this new event code using `evtest`.
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb
Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
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Add support for an Accessibility key. HUTRR116 added support for a new
usage titled "System Accessibility Binding" which toggles a
system-wide bound accessibility UI or command.
BUG=b:333095388
TEST=Build and flash a board that contains an accessibility key. Verify
that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0]
that add this new event code using `evtest`.
```
Testing ... (interrupt to exit)
Event: time 1718924048.882841, -------------- SYN_REPORT ------------
Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1
Event: time 1718924054.062428, -------------- SYN_REPORT ------------
Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0
Event: time 1718924054.195904, -------------- SYN_REPORT ------------
```
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a
Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
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This patch creates a new tereid variant, which is a Twin Lake platform.
This variant uses Nereid board mounted with the Twin Lake SOC and
hence the plan is to reuse the existing nereid variant code.
BUG=b:346442939
TEST=Generate the Tereid firmware builds and verify with boot check.
Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SATA controller is configured to AHCI mode by default. Drop the
setting from the devicetree.
Change-Id: I027b393300e2cbad827e176afddc197007314f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In commit 854dd9a5d1153fbb7ace2a7619bb98d024e284ce
(Makefile.mk: Put site-local path first) the inclusion of
site-local/Makefile.inc was moved to the first place. Unfortunately,
the very next line where subdirs-y is modified resets the variable
instead of extending it which overwrites the inclusion of
site-local/Makefile.inc. This breaks setups where
site-local/Makefile.inc is required.
This patch fixes it.
Change-Id: I36ad1aca5742869c84e2fb556f898f896c6f037a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83190
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
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Configure GPP_R2 as input, no pull according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The southbridge/intel/bd82x6x/pch.h header was previously used to
configure a few registers in SPIBAR, but these have since been moved to
PCH code and the devicetree, making it unnecessary in mainboard.c
Change-Id: I904c95394b4fea73b4990342e647595b5f10335f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82601
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0b49ff8b6275fdde326c79ec21c34faa03094f9e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add 64 bit encode/decode functions to libpayload, since it is required
in the patch that moves device_tree to commonlib.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5dba9a7f41147a511ba1250786e7c51ce623e70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83082
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"site-local" Makfile(s) may need to override some of the macros/paths
used elsewhere in src/* Makefiles. If we include it last src/*
Makefile.mk will have already been processed. MAINBOARD_BLOBS_DIR is
an example where the path needs to be overwritten in site-local
requiring it to be included first before src/mainboard/* Makefile.mk
is processed.
Change-Id: I8ea865cd73aba5092a628b0422e5c4121b32fb4d
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Set a pointer in lib_sysinfo for CSE_BP_INFO and CSE_INFO.
BUG=b:343022317
TEST=Verified CBMEM data in depthcharge on Screebo
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I3aa64d1e439a0596e732a3c0608d60913cefd19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Remove m4 as an explicity installed package as it will be
installed automatically by flex and bison.
Change-Id: Ic4f1c5e6f3324429914bf593047d802dfcc0cb30
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82512
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory part in mem_parts_used.txt, then generate.
H54G56CYRBX247
BUG=b:199645942
TEST=run part_id_gen to generate SPD id
Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
The original include/ec_cmd_api.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit simply updates the input-event-codes.h to the HID
maintainers' tree at SHA c412e40267dd4ac020c5f8dc8c1cccc04e796ff4.
Change-Id: Ic1fb9b18ced37866b84230929cd5c785d0dde9ba
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82993
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The generator inserts into the gpio.h an unnecessary blank line in
front of the list of macros in the table. Let's remove this from the
template to make the code cleaner. These changes have no effect on the
configuration of macros.
Change-Id: I1141ca630cb6d9a46be5bce2b434762ef8e6fdd0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83003
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This error does not affect the generated files as the tests are
running [1, 2, 3]. However, this once again confirms the need to
work on updating the utility.
[1] CB:67132
[2] CB:67133
[3] CB:67134
Change-Id: I91e74d65977bd5e10589530258d1709ea33f1af5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83002
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage.
The remaining Qemu code can already handle the bigger TSEG region.
TEST: Increased TSEG to 8MiB.
Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add support for PE32+ binaries which can be found on X64 UEFI
builds.
TEST: Able to relocate and boot a X64 FSP.
Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With commit 101098c41a ("sdm845: Combine BB with QC-Sec for ROM boot"),
most files from ipqheader were moved to the qualcomm directory.
Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Currently, the payload cannot create new CBMEM entries as there is
no such infrastructure available. The Intel CSE driver in the payload
needs below CBMEM entries -
1. CBMEM_ID_CSE_INFO to -
a. Avoid reading ISH firmware version on consecutive boots.
b. Track state of PSR data during CSE downgrade operation.
2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition
information on consecutive boots.
The idea here is to create required CBMEM entries in coreboot so
that later they can be consumed by the payload.
BUG=b:305898363
TEST=Store CSE version info in CBMEM area in depthcharge on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the Northbridge ASL to conditionally include a
QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS`
is above 4 GiB.
If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the
PCH reserved range, the existing handling of `SM01` remains unchanged
(as a DWordMemory resource).
TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB,
verified ASL output.
Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:347669091
TEST=Able to build ifdtool.
Change-Id: Id261898932f11f4c9066453bce18fd889996e171
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Since BL31_MAKEARGS is already handled in arm64/Makefile.mk, remove the
duplication from mt8188/Makefile.mk. In addition, reserve the memory
range for running OP-TEE only if ARM64_BL31_OPTEE_WITH_SMC is enabled.
BUG=b:347851571
TEST=emerge-geralt coreboot
BRANCH=geralt
Change-Id: I88a9a07a685a6c9fe9739b6101ccb8a5ce23fd8b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add a new Kconfig option ARM64_BL31_OPTEE_WITH_SMC to control whether to
build the OP-TEE dispatcher for BL31. This config also enables the BL31
build option OPTEE_ALLOW_SMC_LOAD, which allows loading the OP-TEE image
after boot via a Secure Monitor Call (SMC). For ChromeOS devices,
CROS_WIDEVINE_SMC is also enabled to allow passing secrets from firmware
to OP-TEE.
BUG=b:347851571
TEST=emerge-geralt coreboot
BRANCH=geralt
Change-Id: I4dcf82d47b537146d71ce3cd2050ec597ed0734f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Adds 64-bit (x86_64) support to libpayload's exception handler,
previously limited to x86_32.
Ensures `exception_init_asm` is called when building with
LP_ARCH_X86_64 Kconfig.
BUG=b:336265399
TEST=Successful build and boot of google/rex and google/rex64 on
ChromeOS.
Verified correct x86_64 exception handling by triggering "Debug
Exception" using firmware-shell as below:
firmware-shell: mm.l -0
Debug Exception
Error code: n/a
REG_IP: 0x0000000030023e9f
REG_FLAGS: 0x0000000000000046
REG_AX: 0x0000000000000009
REG_BX: 0x0000000000000000
REG_CX: 0x0000002000000000
REG_DX: 0x0000000000000001
REG_SP: 0x0000000034072ec0
REG_BP: 0x0000000000000009
REG_SI: 0x0000000000000029
REG_DI: 0x0000000034072eef
REG_R8: 0x0000000000000009
REG_R9: 0x0000000000000000
REG_R10: 0x0000000000000000
REG_R11: 0x0000000034072d70
REG_R12: 0x0000000000000004
REG_R13: 0x0000000000000001
REG_R14: 0x0000000034072ee6
REG_R15: 0x0000000000000004
CS: 0x0020
DS: 0x0000
ES: 0x0000
SS: 0x0018
FS: 0x0018
GS: 0x0050
Dumping stack:
0x340730c0: 3003c32e 00000000 ... 00000000 00000000
0x340730a0: 30034bc6 00000000 ... 0000002a 00000000
0x34073080: 34073234 00000000 ... 00002e65 00000000
...
...
0x34072ee0: 340730ed 30300000 ... 34073000 00000000
0x34072ec0: 34072ed8 00000000 ... 00000000 00000008
Ready for GDB connection.
Change-Id: I8f0aa1da8d179a760e8d49c3764dfd5a69d06887
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83036
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On x86_64 romstage can contain page tables and a page table pointer
which have an larger alignment requirement of 4096. Instead of
hardcoding it, read if from the ELF phdrs.
Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82102
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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According to the vendor spec, I2C1 hold time needs > 100ns.
System needs to adjust the I2C1 sda_hold value from 7 to 13,
the system will change the I2C1 hold time from 70ns to 126ns.
BUG=b:347157276
TEST=built bootleg and verified test result by EE team
Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Lotso's WIFI_BT is same design as brox, copy from brox.
BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
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eval_rst isn't a valid directive. Use eval-rst instead. Also, add curly
braces where necessary since the MyST parser requires them.
Change-Id: I68337354e9bd4de4b2c29d4e42c3bb22337fbe06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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The SPDX parsers can find the SPDX identifiers in the scripts and
makefiles if they aren't broken up. This unnecessarily confuses things
when we're doing license parsing.
Change-Id: I215ed047397f342c912f1a969315fa184a124f6a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
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Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update verb table provided by Realtek on 20240614.
BUG=b:344471736
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC257
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek
Headphone detection:
Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633625.743663, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 1
Event: time 1718633625.743678, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 0
Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Disable LTE, stylus and WFC related GPIOs based on fw_config.
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.
BUG=b:328147465
TEST=Build and check S0ix function and verify FAFT sleep funciton.
Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.
BUG=b:335312655
TEST=Build and check S0ix function and verify FAFT sleep funciton.
Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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I am the one who takes care of end to end DPTF (Thermal Management)
related coreboot things across various X86 based platforms.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I08a1ae48bd5b66ee2f7903615e64d0bab5e0d7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:346930334
BUG=b:346930334
TEST= built bootleg and verified test result by thermal team
Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:346932306
BUG=b:346932306
TEST= built bootleg and verified test result by thermal team
Change-Id: I6a529365249a5372dd87ef28cb9ea8d540b9cac0
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83078
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922
Renoir is similar to Cezanne with only differences in CCX count.
Cezanne has one Zen3 CCX with 8 cores per CCX compared to
the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side
Cezanne SOC code should be mostly compatible with Renoir and
can be leveraged.
Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following variables have been renamed:
* PDPE_table -> PDPT (Page Directory Pointer Table)
* PDE_tables -> PDT (Page Directory Table)
This change improves the consistency and clarity of the code
as per AMD Architecture Programmer's Manual document.
PML4 -> PDPT -> PDT -> 2MB Physical Page
TEST=Able to build and boot google/rex64.
Change-Id: Ib57d1d54c2c1f4fcce2315b508ed7643251a20c5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
|
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This commit fixes an incorrect variable name in the page table setup
for 1 GiB pages.
The label PDE_table was used when it should have been PDPT, as it
represents a "Page Directory Pointer Table (PDPT)", not a "Page
Directory Table (PDT) or PDE_Table".
This change ensures correct nomenclature and consistency in the code.
PML4 -> PDPT --------> 1GB Physical Page
As per x86-64 specification, 1GB pages bypass the Page Directory Table
(PDT) level of the page table hierarchy, mapping directly from the
Page Directory Pointer (PDPT) Table to the physical page.
Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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This reverts commit 0e0bc618e3ed1888ac140010057dc7485443c3c2.
Reason for revert: Merged out of order, breaks tree
Change-Id: I22bd85a2008db471177257a8b779c06898b1010c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM.
Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add initial override devicetree for riven based on
the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).
1. Add eMMC DLL tuning value (copy from craask)
2. Configure I2C frequency (copy from craask)
3. Add audio codec and speaker amp settings
4. Add Elan touchscreen settings (copy from craask)
5. Add WFC and usb settings (copy from craask)
6 Add Elan and Synaptics touchpad settings (copy from craask)
7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration
8. Add LTE settings (copy from craask)
BUG=b:337169542
TEST=Local build successfully.
Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation for introducing other yes/no prompts, factor out the
logic into a common function.
Change-Id: Iff1f0c6c665a5352013122fb791121a116c434f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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device/device.h provides the definition of struct device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c3c09665e3eedec6055f4a0586016c5a5537bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83083
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Elan touchpad driver in newer linux kernels (>= 5.15) no longer
explicitly configures the touchpad as a wakeup source for devices
not using device tree. It is now assumed this information should be
extracted from ACPI, therefore we need to update drallion's devicetree
so that the device regains its lost capability.
TEST=update drallion FW and verify touchpad can cause wake up from
suspend
Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae
Signed-off-by: Angela Czubak <aczubak@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within
the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR.
To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set.
If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then
ensure that the GpioInt is flagged as ExclusiveAndWake (vs just
Exclusive) so that the CREC device is still able to wake the device
as needed.
TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio
and wake_pin both enabled.
Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables ACPI brightness controls to be generated, and display
brightness controls to be functional under Windows.
TEST=build/boot Win11 on google/brya (craaskin), verify display
brightness controls present and functional.
Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Boards using the brya baseboard already generate ACPI brightness
controls via their use of the gfx/generic driver, but need the
default brightness steps in order for display brightness control
to be functional under Windows.
TEST= build/boot Windows 11 on banshee, verify brightness controls
functional.
Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lotso's WIFI_BT is same design as brox, copy from brox.
BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure GPIOs according to schematic_20240607.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus.
BUG=b:328580882
TEST=Local build successfully.
Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I3cb0a39c83d6c92d604f1190538db88d97a81693
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I26f7d5155f73bcf3cb3872f206c946da5029bda8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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If both CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE are not
set, compilation will fail with errors indicating redefinitions of
various console methods.
When BOOTBLOCK_CONSOLE is not set, the __CONSOLE_ENABLE__ macro in
include/console/console.h evaluates to zero when compiling the
bootblock, resulting in various console methods being defined as stubs
in the header. In a typical build with a separate bootblock and
romstage, this will not cause a conflict as the non-stub definitions
found in the console/*.c files are added conditionally to the bootblock
depending on CONFIG_BOOTBLOCK_CONSOLE.
When SEPARATE_ROMSTAGE is not set, the list of romstage objects gets
added to the bootblock. Since the console sources were unconditionally
added to romstage, the non-stub definitions were able to slip into the
bootblock, causing a redefinition of the stubs.
Avoid this by conditionally adding these sources to romstage depending
on CONFIG_SEPARATE_ROMSTAGE. If SEPARATE_ROMSTAGE is set, the non-stub
definitions are handled in the same way as they were before. If it is
not set, the union of bootblock and romstage objects will only include
the non-stub definitions based on CONFIG_BOOTBLOCK_CONSOLE, which uses
existing console/Makefile.mk rules for the bootblock.
TEST=qemu-i440fx builds successfully with all possible settings of
CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE.
Change-Id: I59b3f0c52a4338b1573e0a647bc16cec4943fd7f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83088
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change also drops a duplicated config default line, which might be
why this was omitted.
Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: Ia4a9a5c5897fe78a1243e4c42a7d8753cfe039c0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I20aca1a63306b0f39f97fd0b85d61cd957cb2150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83094
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I00473e44fce9197f818f5a8d131e9be31e8b0f69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6026498c2853f5951227ace57b7198579f342647
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree) and earlier commits, the USB port configuration
should be located in the devicetree instead of the mainboard_usb_ports
array, typically located in the boards early_init.c.
TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and
USBOCM2 RCBA registers in the inteltool dump did not change between
an E6430 build before and after the sb/intel/bd82x6x that moved the
usb config to the devicetree.
Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of using a relative path for the submodules, specify the sub-
module URLs as pointing at coreboot.org, using https.
While the relative path works well for coreboot itself, when the repo
is forked and fetched from from anywhere other than review.coreboot.org,
this file either needs to be modified, or all the submodules need to be
checked out as well.
Change-Id: Ie4f95c70a7f194d1073dc561c9f33dcc108060cc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The components listed in the documentation work in this port.
The MXM structure of the vendor firmware is added, which is
used by the VGA option ROM with int15h functions.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Though coreboot only supports Arrandale, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It's in particular useful for working with variables that contain 64-bit
pointers, like CapsuleUpdateData* global variables defined by UEFI
specification.
Change-Id: I4b46b41cdc5f69d4ca189659bef1e44f64c0d554
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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These data types were added during review of CB:79080 but they weren't
added to the help message.
Change-Id: I6e79d65c80c292c3f5d2a2611e602db5cc6cf374
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82610
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
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TEST=Build and boot on intel/archercity CRB
Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn off camera power during s0ix to improve power consumption.
BUG=None
BRANCH=brya
TEST=built and verified GPP_A17 went to low during s0ix with a scope.
[Measurement of s0ix power consumption - 1 hour avg]
Before this: 301.4 mW
After this: 299.8 mW
Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Trying to probe RAM space to figure out top of memory causes an
exception on RISC-V virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.
A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in RISC-V QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.
Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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The OpenTitan HW implements the same firmware interface as the Ti50
H1D3C hardware variant; it just has a different DID_VID. Allow this new
DID_VID to be recognized correctly.
BUG=b:324940153
Change-Id: Iaacf6d88bc6067948756c465aac1cd8b24ecae1f
Signed-off-by: Jett Rink <jettrink@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83033
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Every now and then we have discussions about blobs and how and if they
should be introduced or handled. This patch adds a clear statement on
the project's view on this topic to avoid unclear situations in the
future.
Change-Id: I20bc0b345c129ecd59aa1190647d89f6d4e07d46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.
This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).
1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates.
ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.
BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.
Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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While both APL and GLK load the CPU microcode from FIT, only GLK
supports the PRMRR/SGX feature. When this feature is supported, the
FIT microcode load will set the msr (0x08b) with the patch id/revision
one less than the revision in the microcode binary. This results in
coreboot attempting (and failing) to reload the microcode again in
ramstage. Avoid the microcode reload attempt for GLK by using a SoC-
specific microcode update check which accounts for the off-by-1 when
comparing versions.
Implementation is based on the one used for SKL and CNL, but modified
based on feedback in comments on Gerrit.
TEST=build/boot google/reef (electro) and google/octopus (ampton),
verify in cbmem console log that CPU microcode update in ramstage is
skipped due to already being up to date, and that GLK uses the
SoC-specific check and APL uses the non-specific/general one.
Change-Id: Iab97f23d4388d5057797bb13f585db821c735bd0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83037
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Physical DP ports are DP2/DP3 (HDMI2/HDMI3 for DP++)
- VGA port is Analog
- DP1 is not connected
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I8ed79167d5445d607acbee491c3382ff2585583f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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When dynamically generating the DOD (Display Output Device) device
address (_ADR), don't set the DOD constraint flags; only set them when
using the address value to generate the DOD package.
This fixes ACPI brightness control functionality under Windows 11.
Before: Name (_ADR, 0x80010400)
After: Name (_ADR, 0x00000400)
TEST=build/boot Win11 on google brya (banshee), ensure display
brightness controls present and functional.
Ref: ACPI Spec 6.5 Appendix B.6.1 - _ADR
Change-Id: I1d710c6e55e6cb1d20d580bd784221ee1482b871
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83025
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Removed an extra space character from the `printf` format string in
`dump_exception_state` to ensure proper alignment of register values
when printed during exception handling.
BUG=b:336265399
TEST=Built and booted google/rex64 successfully.
Verified correct alignment in exception state dumps.
Change-Id: I8ff92775e32ee754967b1b0a43cd68971b4aadfc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83047
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RAM region so that the payload can be placed in there without
coreboot complaining that the payload doesn't target a RAM region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81909
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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OpenSBI often breaks if you update it. This should ensure that jenkins
keeps an eye on it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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OpenSBI got bigger and doesn't fit anymore in 128K which causes coreboot
to not compiler anymore because the region overlaps with ramstage
This patch simply increases the size and uses the OpenSBI linker macro
instead.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If1ccaafbf91dae986c470020faf9c0b4fba448e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enable the fixed boot mode option in the VBT and set it to 1920x1080,
so that drobit boards equipped with 4K screens are legible at boot.
TEST=build/boot drobit w/4K screen using edk2 payload, verify boot
resolution set to 1080p and UEFI menus readable without a magnifying
glass.
Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Generate RAM IDs for
K3KL6L60GM-MGCT
H9JCNNNBK3MLYR-N6E
K3KL8L80DM-MGCU
MT62F1G32D2DS-023 WT:C
H58G56BK8BX068
BUG=b:333494257
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
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Based on lotso EVT schematics update gpio settings.
GSPI0_CS0_L -> NF7
GSPI0_MISO -> NF7
GSPI0_MISO -> NF7
GPP_F18 -> EDGE_SINGLE
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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Update autoport for:
1. Commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree")
2. Commit 94625d2aae76 ("sb/intel/bd82x6x: Allow actual USBIRx values
for native USB config")
As a side effect of #2 above, no more (broken anyway) FIXME comment
will be written for usb_port_config.
Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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