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Without the PCH UART GPIOs set early, there is no serial console
output until ramstage. Add them to the early GPIOs for all puff
variants.
TEST=build/boot google/puff (wyvern) with serial console enabled,
verify console output starts in bootblock.
Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move following definitions to common/
1) the definition of the bit fields for domain remap
2) the definition of the structure for the permission of all domains
Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brya queries the TPM in early ramstage (pre-device init) to determine
if the CR50 has support for long-pulse interrupts. If the TPM (and
underlying I2C controller) hasn't already been setup in verstage, it
will fail to do so in ramstage since the I2C controller has not yet
been initialized. To work around this, initialize the TPM in bootblock
for the non-vboot case, to ensure the I2C controller is set up when
needed in early ramstage.
TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem
console when initializing TPM in early ramstage.
Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds ACPI entries for SAR Proximity Sensors as below
SAR1 Sensor:
- SAR1_INT_L : GPP_E00
- I2C5 7-bit address 0x28
SAR2 Sensor:
- SAR2_INT_L : GPP_E08
- I2C 7-bit address 0x2c
BUG=b:297977526
TEST=Able to build and boot google/rex.
w/o this patch:
Total 6 devices are listed below:
> ls -lt /sys/bus/iio/devices/iio:device*
/sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/
LNXSYBUS:00/PNP0A08:00/device:07/
/sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
w/ this patch:
Total 8 devices are listed below:
> ls -lt /sys/bus/iio/devices/iio:device*
/sys/bus/iio/devices/iio:device6 -> ../../../devices/pci0000:00/
0000:00:19.1/i2c_designware.4/i2c-
/sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/
LNXSYBUS:00/PNP0A08:00/device:07/
/sys/bus/iio/devices/iio:device7 -> ../../../devices/pci0000:00/
0000:00:19.1/i2c_designware.4/i2c-
/sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
Change-Id: I0a518d58915f9f4dbe58a45c4dc5875abbfda135
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78045
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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The primary branch changed names. To remain robust, just use HEAD,
which will point to whatever is authoritative.
Change-Id: I809ea748a5e51f4eea6bc227fa1fc5c8b07fe2ef
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78015
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel Meteor Lake QS silicon provides better size optimized pre-x86
reset blobs.
This patch creates a new flash layout (FMD) for QS to accommodate those
optimizations, and renames the existing FMD for ES (pre-prod) silicon.
Comparative analysis between QS and ES flash layout is here:
For QS silicon:
- SI_ALL reduced from 9MB to 8MB.
- SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI
layout.
- ME_RW_A/B reduce from ~4.5MB to 4MB.
- Ensure RW-B slot is starting at 16MB boundary.
- Unused space increased by 1MB.
For ES silicon:
- SI_ALL: 9MB
- SI_BIOS: 23MB
- ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH).
- Unused space 3MB (for release) and 2MB (for debug) layout.
Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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I didn't have enough time, so it's reasonable to remove myself.
Change-Id: I8f7d87f70916f3d0697b6c38ca6d75f3375bd374
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I590b7fb5f5f52cbf1a61c65f8fac757e36feac5e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75028
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I866333a234203dc2da3d4dd8c4f87e4cfa332787
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Ia4ed3491e6a32659b957285ab20ad47c9085083c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75025
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I097d50a7af7c8ea48369806e8bb73734a8e84470
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75024
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id7f9b598cc9df51ddf664b851172cc96a710c580
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75023
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I3f4965b8b253983ad1f8db77e1b91860a270c305
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The options in conf.py for the following build targets are either
commented out or contain example values, which suggests that there was
no interest in them recently. Their comments also seem more like
generated examples.
* LaTeX
* man pages
* Texinfo
In order to clean up our configs and scripts for the documentation,
remove the configuration options from conf.py for these build targets.
Also, remove the build targets responsible for generating a PDF file
from Makefile. Don't touch Makefile.sphinx for now though as we usually
wrap around it.
We may bring these build targets back if there is real interest in
them, but it seems only the HTML target was really used.
Change-Id: I7df8ea886f94d9b25e8eeb0ccbc2a7392b96a575
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77439
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: If2c9c52f1e2866082df8e534b1a074639bb62db2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75020
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Idf4a566af3853636945709c88c03fb8e777211c2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Iaa73bf7f85f840299c467b7d712546d3f72a4e75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id1b0d375670f9e59047eff737bc17e61bf93175e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75016
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I1033a974a818308b31e1334cad5869d2cd81bd9e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75017
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I207e25059a9fb9e6a951018e954662931b3f8b93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75018
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No drivers exists or are needed, so use devicetree hidden keyword to
set the ACPI status to hidden to prevent unknown devices from showing
in Windows Device Manager.
TEST=build/boot Win11 on morphius, verify unknown devices for the
fingerprint reader and stylus detection are no longer shown.
Change-Id: I992c0ec8d97c6041e3a268445613bfa42dd8b279
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Allows device to be hidden from OS (Windows) via devicetree 'hidden'
keyword.
TEST=tested with rest of patch train
Change-Id: I81482bd19e24627cab80deed2b9057f45b6ac0a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78037
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since all non-CAR AMD SoCs have the same mp_init_cpus implementation,
factor it out and move it to a common location.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Enable wake-on-DP by adding USB mux events to the wake mask. The EC
wakes the AP with these events for DP connect/disconnect.
BUG=b:294307786
TEST=DP connect/disconnect wakes the DUT appropriately.
Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently MP2 Firmware is not built into RO firmware section but the
soft fuse bit to disable MP2 firmware loading is not set. This causes
the device to boot loop during recovery mode. Set the bit to disable MP2
firmware loading in RO.
BUG=b:259554520
TEST=Build and boot to OS in Skyrim under both normal and recovery
modes.
Change-Id: I9e4cf4f72e2d36ad3cc33629ddb501ecdbf5eda9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78023
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Karis uses PIXA touchpad, update related settings.
BUG=b:294155897
TEST=(1) emerge-rex coreboot
(2) Test on karis, touchpad function works
Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This board is similar to x11ssm-f but has a proprietary form factor with
NVMe and a single x16 slot (potentially bifurcated to 2x x8) and a x4
slot.
Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3
Signed-off-by: Kieran Kunhya <kieran@kunhya.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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CONFIG_HAVE_ACPI_SUPPORT does not exist. Replace it with
HAVE_ACPI_TABLES.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icc7c00dc19cae4be13e6c8cc0084a69aed8fb8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Change the name of msr_a and msr_m to the more descriptive msr_base and
msr_mask.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6e0010f6d35ccf4288f4e0df8f51ea5f17c98b0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78007
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead adding 1 to the result of MTRR_PHYS_BASE(index) to get the
variable MTRR's mask MSR number, use the MTRR_PHYS_MASK macro.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieecc57feb25afa83f3a53384e5a286f2e4e82093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Now that no local union definitions are used any more, pass the msr data
to display_mtrr_fixed_types as an msr_t type parameter instead of a
uint64_t parameter. Also rename the parameter from msr to msr_data to be
more specific that this parameter is the MSR contents and not the MSR
number.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iafde64129acc4bf9f01816de21c7793edfc1a799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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In the functions the local MSR variables are only written once by rdmsr
calls at the beginning of the function and then only read, so those can
be made const.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1be6a5158c0c06abe128e9394d6001c40a8d4cbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Commit 407e00dca06e ("include/cpu/msr.h: transform into an union")
changed the msr_t type to a union that allows accessing the full 64 bit
via the raw element, so there's no need to wrap it again in another
union for the full 64 bit access.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I750307297283802021fac19e2cdf5faa12ede196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Hook up the OC watchdog common block and initialize it if requested.
TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reduce the OC WDT integration code footprint by consolidating
multiple API calls into a single function to be called by SoC.
Change-Id: Iba031cd8e0b72cabc4d0d8a216273d763231c889
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77574
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:299374763
TEST=emerge-rex coreboot
Change-Id: I40fc768522e8679337c3b9f5497278e9f4639c3e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77888
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fails to build on musl libc as pci/types.h expects "POSIX types", which
are not implemented, instead of stdint.h when using pre-C99 versions.
Change-Id: Id1cf5bd72a0b4d76c87dc62c443d02df18ddd3fe
Signed-off-by: Nicholas Sudsgaard <devel@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77791
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
This patch ensures that the
`DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` config is enabled if
the underlying platform is built with a pre-production SoC (aka
`SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config is enabled).
BUG=b:300652989
TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is enabled
for google/rex4es aka all variants with ES silicon.
Change-Id: Ieda39427915fa3973b832376ec20fc414ac2bedd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77993
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
|
|
The tree contains engineering sample boards, that ship with
pre-production Meteor Lake SoC. These boards are not sold.
BUG=b:300652989
TEST=Ensure mainboards like google/rex4es and screebo4es have
`SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config enabled.
Change-Id: I1a875a0f1d2c38582f35250ebe645e53599f62de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77992
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
Certain Intel Meteor Lake specific features are only enabled in
production silicon (not available in early SoC aka pre-production
silicon).
- SPI usage for production SoC is much optimized compared to pre-
production silicon.
- MIPI driver requires a way to identify between pre-prod vs prod
silicon.
This patch adds config options to select the Pre-Production
aka Engineering Silicon (ES). The mainboard users can specify which
underlying SoC is being used for the target platform.
BUG=b:300652989
TEST=No change in the functionality, just added new configs.
Change-Id: I60fe11c1151a3a6c290cd0105eb570cb78e81797
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
|
|
Enable SOC_INTEL_CRASHLOG and SOC_INTEL_IOE_DIE_SUPPORT Kconfig
options.
BUG=b:262501347
TEST=Able to build google/rex. Able to trigger and decode crashlog.
Change-Id: I4beef7393090889fde8d67827035c3b57a3dbb34
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add the eMMC MMIO device to the devicetree and make it use the common
AMD eMMC driver. Since there is now a device for this in the devicetree,
also use this device to determine if the FSP should be told if the eMMC
controller is supposed to be disabled.
TEST=On Mandolin the eMMC controller both disappears in the Windows 10
device manager and in dmesg on Ubuntu 2022.04 LTS
TEST=Morphius with NVMe SSD still works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5453b69df776d2ce1f3be11e37cd26c8c64f0cd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
When the eMMC MMIO device is enabled in the devicetree, it needs to be
exposed in ACPI in order for the OS driver to be able to attach to it.
The Cezanne eMMC controller isn't used in google/guybrush, so this the
code path where the eMMC MMIO device is enabled in the devicetree can't
be easily tested.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69ff79b2d1c6a08cf333a2bb3996931962c2c102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Change-Id: I6a64015326c6ec7e14a0465fe081a2cb4606cdc8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77734
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic3e9570c110d8cded8c00e74fff29cc3a711582e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
GPP_C06 is the report pin of the touchpanel and has no actual function.
Disable this pin to solve the leakage problem.
BUG=b:298529441
BRANCH=none
TEST=Test success by EE.
Change-Id: I13f25788c0258639da4e277e7a15454a08d1599b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77716
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a separate Kconfig option for adding np_region.c to the build. Only
the code for Picasso, Cezanne, Mendocino, Phoenix and Glinda call
data_fabric_set_mmio_np which is implemented in that file, so only
select the new SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION Kconfig option
for those.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic49ce039462b52e2c593c7d2fef43efc50901905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77987
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Make naming convention consistent across all functions return values.
BUG=b:296439237
TEST=Boot to OS on Skyrim
BRANCH=None
Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add the TPM return code to the vboot fail call to provide additional
context.
BUG=None
TEST=builds
Change-Id: Ib855c92d460d1e728718b688ff71cdc6e1d9a84a
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
tis_init calls into tis_probe and returns an error or success, simplify
the call stack by removing the current tis_init implementation and
renaming tis_probe to tis_init.
BUG=None
TEST=builds
Change-Id: I8e58eda66a44abf5858123cf9bcf620626f1b880
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
If LP_VBOOT_CBFS_INTEGRATION is enabled, then libcbfs will reboot with
vboot failure in non-recovery mode on CBFS file hash mismatch.
BUg=b:197114807
TEST=Build with VBOOT_CBFS_INTEGRATION enabled and boot on
google/ovis4es device
Change-Id: Ic0f62212b7217b384e8c4cbd9535fe4243301f8c
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77726
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Patch adds:
- vboot_fail_and_reboot() for vboot failures handling.
- reboot() weak implementation for payloads to implement, used
by vboot_fail_and_reboot().
- vboot_recovery_mode_enabled() to check if recovery mode flag is set in
vboot context. Implemented for future libcbfs implementation
of VBOOT_CBFS_INTEGRATION in libpayload.
BUG=b:197114807
TEST=none
Change-Id: I53d1955573d54bc56d05f7780c18dcc8ac1fd399
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Factor out data_fabric_set_mmio_np and the helper functions it uses into
a separate compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I58625c5a038f668f8e30ae29f03402e1e2c4bee3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
To fully and easily implement fallback/recovery in libcbfs with vboot
support the codebase requires access to vboot context. Moving context
management to libpayload allows to avoid unnecessary overhead and code
complication and still allows payloads to access it in a way it was
designed. Access to this codebase will also allow implementation of e.g.
vboot_fail_and_reboot() and other helpful utilities used by coreboot and
depthcharge.
BUG=b:197114807
TEST=make unit-tests
TEST=Build and boot on google/ovis4es with CL:4839296 and
VBOOT_CBFS_INTEGRATION enabled
Change-Id: Id719be7c4f07251201424b7dc6c1125c6b5756d8
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Use data_fabric_get_mmio_base_size in data_fabric_print_mmio_conf
instead of open coding the functionality. This will fix the printing of
the MMIO config in the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
case which wasn't handled properly before.
TEST=Console output from this function doesn't change on Mandolin:
=== Data Fabric MMIO configuration registers ===
idx base limit control R W NP F-ID
0 fc000000 febfffff 93 x x 9
1 10000000000 ffffffffffff 93 x x 9
2 d0000000 f7ffffff 93 x x 9
3 0 ffff 90 9
4 fed00000 fed0ffff 93 x x 9
5 0 ffff 90 9
6 0 ffff 90 9
7 0 ffff 90 9
=== Data Fabric MMIO configuration registers ===
idx base limit control R W NP F-ID
0 fc000000 febfffff 93 x x 9
1 10000000000 ffffffffffff 93 x x 9
2 d0000000 f7ffffff 93 x x 9
3 fed00000 fedfffff 1093 x x x 9
4 0 ffff 90 9
5 0 ffff 90 9
6 0 ffff 90 9
7 0 ffff 90 9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If602922648deca0caef23a9999c82acdd128b182
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Since vboot_extend_pcr() returns vb2_error_t, the return type of
extend_pcrs() should be vb2_error_t too.
Also fix an assignment for vboot_locate_firmware(), which returns int
instead of vb2_error_t.
Change-Id: I1a2a2a66f3e594aba64d33cfc532d1bd88fa305e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I63bbac225662377693ad5f29cc8911494c49b422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Linux v6.3.5 is able to detect and use ACPI tables on an out of tree
target using hacked version of u-boot to pass ACPI through UEFI.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
data_fabric_disable_mmio_reg and data_fabric_find_unused_mmio_reg are
only used by data_fabric_set_mmio_np in the same file, so make them
static and drop the prototype from the header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bf7a868aae2fd01b8adecd3e4cba6ff6d5119af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
coreboot offers two vboot schemes VBOOT_SLOTS_RW_A and
VBOOT_SLOTS_RW_AB. When VBOOT_SLOTS_RW_AB is not selected then the
resulting image is rather not expected to have the FW_MAIN_B FMAP
region. When only RW_A region is used, vboot does additional full_reset
cycles to try RW_B, even though it does not exist / the build was not
configured for two RW partitions. To avoid it, a new vboot context
flag has been introduced, VB2_CONTEXT_SLOT_A_ONLY, which can be set
right after context initialization to inform vboot about absence of
slot B. This will result in less full_reset cycles when vboot runs
out of available slots and cause vboot to switch to recovery mode
faster.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie123881a2f9f766ae65e4ac7c36bc2a8fce8d100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data
section support for pre-memory stages"), this comment is not correct
anymore and should be removed.
Change-Id: I61597841cd3f90cebe7323a68738f91d6d64b33d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
|
|
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data
section support for pre-memory stages"), the libhwbase and libgfxinit
.data symbols can be moved to the .data section.
Change-Id: I302391e7bc8cb4739e5801d360c57776b0e3eff6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data
section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION'
flag and its derivatives can now be removed from the code.
Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit dc7cc5bc6edf ("mb/google/skyrim: Disable
USE_SELECTIVE_GOP_INIT") but limits the default enablement to Skyrim
variant only, to allow for continued testing.
BUG=b:271850970
BRANCH=skyrim
TEST=build/boot ChromeOS R117+ on google/skyrim, verify no display init
failures with feature enabled on cold/warm boots or S0i3 resume.
Change-Id: I21c70111a5f407a7e8dd1ad1f2c2759ddb91893e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add support for moving the console cursor horizontally and vertically.
BUG=b:300405745
TEST=Tested using firmware shell on Rex.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I585add120b559396bc0e28aa972b0ae2a33f1fa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77900
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Update an invalid error message printed when the timer expires.
BUG=None
TEST=None
BRANCH=None
Change-Id: If6d35290e9cb8281cd33892dc052f49277474a59
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Added Raptor Lake U graphics device ids.
Renamed Raptor Lake U graphics device ids that were marked as
Raptor Lake P.
Added Raptor Lake P graphics device ids.
References:
RaptorLake External Design Specification Volume 1 (640555)
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update PLDs to match the port layout:
Front (left to right):
A4, A3, A2
Back (left to right):
C0, A0, A1
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port7/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port7
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4
Change-Id: I682a153d6b757e1b66373c622a6fcfbf389184e3
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77877
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update PLDs to match the port layout:
Front (left to right):
C0, A1, A0
Left side:
C1
Also enable the usb 3.1 device.
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
(Ports 5 and 6 are not used on boxy but are peered by default)
Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
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Change-Id: I9a9926a7298bca0ca5b67a59124b1e0471e179c4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77729
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Ia4b142a5eac2aab7e4fa6e32ed68c96934ec6c32
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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cpu_cl_cleanup() function checks if the SOC supports storage-off
feature. This feature allows to turn off PUNIT SSRAM to save power.
Enable the storage-off if it's supported. Enabling it also clears the
crashlog records from PUNIT SSRAM.
cpu_cl_rearm() function rearms the CPU crashlog.
BUG=b:262501347
TEST=Able to build google/rex. Verified both features get asserted.
Change-Id: Id9ba0f5db0b5d2bd57a7a21f178ef1e86ca63fae
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77239
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add more details in CPU crashlog header structure, such as
storage off status and support, re-arm status etc. These fields
are used to check of particular feature is supported or not and
if supported what is the status of the feature.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: I4242b6043b8f8ad9212780f44ca0448cd2b6b9f8
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77562
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Introduce cpu_cl_cleanup() and cpu_cl_rearm() functions
for CPU crashlog flow. Also add default weak implementations.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: Iad68d3fdaf7061148b184371f7ef87d83f2b2b38
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77238
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Not all SOC follow the same programming to clear crashlog
data. So make common implementation of cpu_cl_clear_data()
weak.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: Ic2b4631d57703abff0ab1880fb272ef67bb1b8e9
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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relanding original commit 5013c60a871af8fbce8c38a1c342c454e5b8452f
("soc/intel/meteorlake: Generate new TME key on each warm boot") which was previously reverted by commit 19e66b7c951ce71a1b9bc20158af56e559f8a58f
(Revert "soc/intel/meteorlake: Generate new TME key on each warm boot")
due to consecutive reboot post warm reset issue.
The consecutive reboot post warm reboot issue has been fixed with
commit ba7a9eefcf4e571bc73d4be1141f676fc5547057 ("soc/intel/common: Fix
invalid MADT entries creation"), hence, reattempting to land the original TME key related patch.
BUG=299294328
TEST=Boot up the system, generate kernel crash using following
commands:
$ echo 1 > /proc/sys/kernel/sysrq
$ echo "c" > /proc/sysrq-trigger
System performs warm boot automatically. Once it is booted,
execute following commands in linux console of the DUT and confirm
ramoops can be read.
$ cat /sys/fs/pstore/console-ramoops-0
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5d45d265ccef1a7d37669ea22a74b52e2f3ae20d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch eliminates the need to maintain separate FMD files for rex
variants and rex variants with ISH. It does this by using the
BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW
layout sizes.
TEST=Able to build and boot google/rex and google/rex_ec_ish.
Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This reverts commit 449c6d981c216e05d5238056f03c7794e43600ec.
Reason for revert: (EVT board build does not exhibit shutdown followed
by warm reboot)
This commit reverts the workaround that limits the TCC activation
temperature. The original issue that was reported (shutdown followed
by warm reboot) was not seen in the EVT board build, so this change is
likely unnecessary.
Change-Id: I22adcdee6512e57ad0b6d531f2611e22a95c863e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Boot to OS, check camera LEDs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera
driver to extend the same support for all SoCs, so removing this config
from Alderlake SoC code.
BUG=None
TEST=Build rex and brya to check if the build passes without an
error.
Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
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Some of our documentation still points to the wrong branches
Change-Id: Idb72e4f44f294f64eb01c588027d300a53d6fb41
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77875
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn
for HDMI.
BUG=b:296791122
TEST=build and check HDMI function works on craaskana
Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
|
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Change-Id: Icc7974931a9b3f5b5c7a2ed4df2c668dac0cd684
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Change-Id: Ib365a17652b8531e865fa16eae837c68cbedbca8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
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Move the existing FSP 4221.00 headers for Raptor Lake to a
subdirectory called 4221.00_google, and select this if the
vendor is Google.
Add the standard FSP 4301.01 headers to a separate directory,
from Intel download #686654, and select this for all other
vendors.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add some noop device_operations for devices below chip drivers/pc80/tpm
in the case CONFIG_TPM is unset. This avoids the warning "... missing
read_resources" when probing all devices for resources.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ibc37642a8b5f37b95c648141e03025a04ffa36bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77386
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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There are going to be skus without stylus and fingerprint module.
Disable stylus and fingerprint module based on fw_config.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I047aae06c4a915d0392edc836757b882a261c178
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77647
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update fw_config settings for karis:
| | | 0 --> STYLUS_ABSENT |
| Bit 2 | STYLUS | 1 --> STYLUS_PRESENT |
| | | |
| Bit 3-5 | AUDIO | 0 --> ALC5650_NO_AMP_I2S |
| | | |
| Bit 8-9 | MIPI_CAM | 0 --> UF_CAM_HI556 |
| | | |
| | | 0 --> FP_ABSENT |
| Bit 10-11 | FP_MCU | 1 --> FP_MCU_NUVOTON |
| | | |
| | | 0 --> WIFI_CNVI |
| Bit 13 | WIFI_TYPE | 1 --> WIFI_PCIE |
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I1df30ad32d212a36b8a5bd7324f3eb8045b2795c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port5
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4
Change-Id: I5fe8066e361da62b747464b2ec09bcc6e7dda0fe
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77867
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
BUG=b:264960828
TEST=On dibbi, ACPI tables contain entries for USB 3.4 and 3.5
Change-Id: If3266d356a2deaf42aa0943f85593416d80637ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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UWB on Rex will have 2 options to connect to the SoC:
1. Through GSPI1 (muxed with FP)
2. bit-bang over GPP
This CL adds GSPI1 option. BB may be added later.
BUG=b:263413448, b:263499898
TEST=UWB ranging works on Rex with this CL
Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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1. WIFI_SAR_ID_4: AX211
2. WIFI_SAR_ID_5: AX203 (without WiFi-6E)
BUG=b:293360900
TEST=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6c4705d25d927aaefbc8814ea1df3b4c36b30968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77790
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Kuldax-refresh use USB Hub, add fw_config probe for USB Hub.
BUG=b:275335023
BRANCH=brya
TEST=Built and check firmware log.
Change-Id: Ib983ca527a891718f317336597faad66d076247f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based
on doc 619362 rev 2.2.
Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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This patch addresses the increased boot time issue that occurs when ISH
store is enabled, such as in the "rex4es_ec_ish" variant.
During a cold reboot, the CBMEM memory resets and loses the stored
firmware versions. This causes the firmware versions to be fetched again
from the CSE, which increases the boot time by about 200 ms. This patch
stores a backup of the firmware version in CMOS and updates the CBMEM
memory during a cold reboot.
BUG=b:280722061
Test=Verified the changes on rex board.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements APIs to access the CSE FW partition versions in
CMOS. The get API allows users to retrieve the current version from
CMOS memory. The set API allows users to set the version in CMOS
memory.
BUG=b:280722061
TEST=APIs verified on rex board.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Remove the check to follow the new flow that commit 9c348a7b7ea3
("soc/intel/alderlake: Fix processor hang while plug unplug of
TBT device") introduced.
Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie822b8e1fd7592a31275db8455519c4cc6ac02ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: Ibf28fbdf791e7aa2faa41f3059150bf5ff5d21d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77735
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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