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2022-11-21util/abuild: Add --name option to set name of abuild runMartin Roth
Previously, the testclass variable was only updated with the chromeos or Kconfig option values, and the output directory and xml file names were updated independently. With the --name option, all of these can be set simultaneously. This also prevents jenkins from seeing clang and gcc tests as the same because the testclass variable wasn't updated. If --name is not set, all behavior is as it was previously. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-tools target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-tools target, make test-tools from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Update ABUILD_OPTIONS with long option namesMartin Roth
It's hard to tell what is what with the short option names, so use the long options here. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1371e098bba1077dedfaffa56287a28656197b40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-abuild target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-abuild target, make test-abuild from what-jenkins-does. The test-abuild target had not been updated to use the ABUILD_OPTIONS variable, so update it with the commands from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-lint target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-lint target, make test-lint with the --junit argument from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Unify cleanup in all targetsMartin Roth
Instead of having the what-jenkins-does target clean up before building, have it call the test_cleanup target. Clean the tegra targets. Remove distclean from test_cleanup target - I don't think that's expected, and people might be upset by having their .config deleted. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21soc/amd/mendocino: Increase CBFS_MCACHE sizeKarthikeyan Ramasubramanian
CBFS_MCACHE is currently experiencing overflow with CBFS verification enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB. This reduction along with the available free space in PSP shared buffer (32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required 14 KiB. BUG=b:259342909 TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS mcache overflows. FMAP: area COREBOOT found @ 80a000 (8347648 bytes) VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640 VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled Ensure that firmware_CbfsMcache FAFT test is successful. Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21cpu/intel/socket_*: Clean up Kconfig filesElyes Haouas
Remove SSE when SSE is already selected by supported CPUs. Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig. Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-21util/abuild: check for PASSED_BOARDS before trying to show itMartin Roth
If no boards are tested by abuild, an error is currently shown because no boards failed, but no boards passed either. Account for this possibility. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21src/superio: Remove unnecessary space after castsElyes Haouas
Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69814 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-21include/memlayout.h: update comment about VBOOT2 work buffer sizeFelix Held
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in vboot/firmware/2lib/include/2constants.h, so update the comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21soc/intel/common: Add support to read CPU and PCH Trace Hub modesSridhar Siricilla
The patch parses CPU and PCH Trace Hub modes from the debug area in the Descriptor Region. The modes can be updated in the debug area in order to configure the CPU and PCH Trace Hub modes. The debug area's offset starts from the SPI Flash offset:0xf00. For runtime debugging, the OEM Section in the Descriptor Region is being used as debug area. The OEM Section details are documented in the SPI Programmer Guide of CSE Lite kit. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-11-21mb/google/brya/var/marasov: update field STORAGE of fw_configFrank Chu
field STORAGE 30 31 option STORAGE_UNKNOWN 0 option STORAGE_NVME 1 option STORAGE_UFS 2 end BUG=b:254365935 TEST=emerge-brya coreboot. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69786 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-20mainboard/msi/ms7d25: Configure NCT6687D pin for PECIMichał Żygowski
One register configuring multi-pin functions was outside of the Global Configuration Registers space and skipped in the initial port patches. Replicate the vendor configuration and set the Super I/O pin for PECI functionality. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20device/pciexp: add pcie_find_dsn()Jonathan Zhang
Add pcie_find_dsn() to detect and match PCIe device serial number. In addition, vendor ID is matched when provided. Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20acpi: Add initial support for CEDTJonathan Zhang
Add initial CEDT (CXL Early Discovery Table) support based on CXL spec 2.0 section 9.14.1. Add functions to create CEDT table (revision 1), and create CEDT CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows Structure (CFMWS). TESTED=Create CEDT table on Intel Archer City CRB, dumped the CEDT table and examined the content. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20util/kconfig: Add patch to move Kconfig deps to build/configMartin Roth
The change being reverted [1] caused all the Kconfig dependency files to be generated at the top level of coreboot's build directory. This reverts that behavior and puts the dependencies back where we're used to them being. [1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20Docs: Add SPDX headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id229fb22d20c489db3dd7a59f29e7ac10174fd85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-20drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed commentJan Samek
There is a note about the default I2C speed of this being 400 kHz despite the logic in rx6110sa.c sets the fallback (correctly) to 100 kHz. This information originally comes from the fact the dw_i2c bus controller default speed is 400 kHz. This is irrelevant to the default speed of this device as it can be used with any bus controller. BUG=none TEST=coreboot builds correctly (no functional changes). Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-19security/tpm: make log format configurable via KconfigSergii Dmytruk
This commit doesn't add any new format options, just makes selecting existing format explicit. Ticket: https://ticket.coreboot.org/issues/422 Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-19mb/google/rex: Enable TCSS DisplayPort detection at prebootzhaojohn
This change enables the DisplayPort detection at preboot for Rex board. BUG=b:247670186 TEST=Built image and validated DisplayPort feature at preboot on Rex. Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19soc/intel/common: Fix the TCSS DisplayPort detection flowzhaojohn
After DisplayPort is plugged into type-C port, its hpd signal instantly presents and EC has mux_info for dp and hpd. This change fixes the DP detection flow to avoid the 1 second delay while no DP is connected. If DP is present, there will be requests towards PMC through the sequence of connect, safe mode, dp and hpd mode. BUG=b:247670186 TEST=Built image and validated the DisplayPort preboot feature on Rex. Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19vc/amd/fsp/glinda/platform_descriptors.h: Update for glindaFred Reitberger
Update definitions on glinda used by birman. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I03065011581489b5345c16e225edc341e1d7811c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19vc/amd/fsp/morgana/platform_descriptors.h: Update for morganaFred Reitberger
Update definitions to match morgana FSP. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic893526789c05a298965702114d4a814466a5742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGERCaveh Jalali
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreenTyler Wang
BUG=b:235919755 Test=Check error message "Exposing GPIOs in Power Resource and _CRS" not show in firmware log. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I21a47adde48555098d041b94d483cad308bdb717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-11-19soc/intel/meteorlake: transition full control over PM Timer from FSP to corebootKapil Porwal
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Port of commit 0e905801f8ff ("soc/intel: transition full control over PM Timer from FSP to coreboot"). NOTE: This will have a huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. BUG=none TEST=Boot to OS on google/rex. Excerpt from google/rex coreboot log: [SPEW ] EnableTcoTimer = 1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-18mb/google/rex: Disable `ACPI PM timer`Subrata Banik
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that ACPI PM timer remains disabled. The PM timer (by PMC IP) consumes more power and blocks S0ix so the timer is emulated by ucode to save power and unblock S0ix. TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc BIT 1 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18mb/google/skyrim: Enable STB Spill-to-DRAM by defaultMartin Roth
BUG=b:231291430 TEST=See STB Spill-to-DRAM enabled Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib60b7fc2ba85c7a8025c9f8c6495e94049499f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69707 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18build: List all Kconfigs in CBFS `config` file, compress itJulius Werner
The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can remove all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-18drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistentJan Samek
Set the logging message prefix to the device name instead of the device path in order to make the output consistent with other logging messages in this and other drivers. Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69718 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c ↵Jan Samek
device Instead of creating a dummy I2C device in order to force Linux to decrease the I2C bus speed, use the own 'bus_speed' field of RV3028 device config structure. Linux should always set the bus speed to the speed of the slowest device sitting on the bus. Hence the dummy device is not needed here anymore. BUG=none TEST=See if the RV3028 RTC is visible and working (date/time can be set/read) in Linux. At the time, a driver modification is needed to add a match table for the "MCRY3028" ACPI HID. A proper kernel patch is pending. Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18drivers/i2c/rv3028c7: Add ACPI generation callbacksJan Samek
Add ACPI generation callback to the driver after obtaining the ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY"). Also add I2C bus speed field to the device config structure, which is a required ACPI entry. BUG=none TEST=Disassemble the SSDT table and see whether the device entry "MC28" is generated correctly. Also check whether the RV3028 driver in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding an ACPI match table to it containing the HID. A proper kernel patch is pending. Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-18lib/malloc.c: Fix log messagesElyes Haouas
It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69624 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for AlibEricKY Cheng
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles. User can use these profiles for dynamic thermal table switching support. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-18soc/mediatek/mt8188: Enable and initialize EINTJohnson Wang
Issue: Device can't wake up using power key. Root cause and solution: EINT event mask register is used to mask EINT wakeup sources. All wakeup sources are masked by default. So we add a driver here to unmask all wakeup sources. BUG=none TEST=wake the device up by power key on MT8188 EVB. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-18soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUsShelley Chen
On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. BUG=b:254281839 BRANCH=None TEST=build firmware image and boot and make sure we can boot up Tested on villager, which does not have NVMe and made sure that it boots still. Check cbmem dump to make sure that device configuration entry is still low since it's not initializing PCIe devices: 40:device configuration 730,203 (1,295) Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18mb/google/herobrine: Implement mainboard_needs_pcie_initShelley Chen
Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-18soc/intel/meteorlake: Add Meteor Lake MCH device IDSridhar Siricilla
Add Meteor Lake MCH device ID 0x7d15. TEST=Build and verify boot on MTL RVP With patch, coreboot log: `[DEBUG] MCH: device id 7d15 (rev 00) is Meteorlake P` Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18mb/google/nissa: Modify FMD to redistribute bufferKrishna P Bhat D
Modify the chromeos FMD file for nissa variants to redistribute the buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS region. 1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME is 3708K. 2. Modify SI_BIOS region to 12672K. This results in an addition of 32K buffer each to FW_MAIN_A/B regions. BUG=b:228936671 BRANCH=firmware-nissa-15217.B TEST=Verify CSE FW update with new FMD and ME RW blobs on craask. Cq-Depend: chrome-internal:5094491 Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18mb/google/brya/variants/crota: Configure TDC current for VR domains.Johnny Li
+-----------+-------+-------+---------+-------------+----------+ | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +-----------+-------+-------+---------+-------------+----------+ | IA | 2.8 | 2.8 | 80 | 43 | 28000 | +-----------+-------+-------+---------+-------------+----------+ | GT | 3.2 | 3.2 | 40 | 23 | 28000 | +-----------+-------+-------+---------+-------------+----------+ - IA TDC current from 20A to 43A. - GT TDC current from 20A to 23A. BUG=b:256754175 TEST=Build test image and use PTAT to check IA and GT value Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69135 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-11-18Makefile.inc: Remove workaround ACPI warningsArthur Heymans
No boards now have a missing dependency so remove the workaround. Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69514 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17util/kconfig: Move Kconfig deps back into build/configMartin Roth
revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1] The above change caused all of the enabled kconfig options to be written into the top level build directory. We don't want that, so go back to the old behavior for the coreboot tree. [1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17soc/amd: Use ioapic helper functionsKyösti Mälkki
Calling setup_ioapic() was only correct for the IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs. Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17{ec/superio}/acpi: Remove _PRS if no _SRS is implementedArthur Heymans
_PRS only makes sense if _SRS is implemented. Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17superio/acpi/pnp_generic.asl: Add _PRS for each deviceArthur Heymans
Simply return the current resource settings in the _PRS method. This means that coreboot has to correctly set up the resources on the device. This won't result in any regression as without _PRS the ACPI OS would not know what resources settings are valid, so it would never use _SRS. Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64218 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17arch/x86/smbios: Add SMBIOS Type 39Jonathan Zhang
Read FRU product info of PSU to get Type 39 required information. Further development needed if multi-record info of PSU FRU is required. For now, the read_fru_areas() only read product chassis and board info. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Signed-off-by: ziang <ziang.wang@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I18d056cba1a79b0775c8a42b3a879e819887adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-11-17mb/prodrive/atlas: add unique DIMM locators in smbios type17David Milosevic
This patch adds unique device-locators, bank-locators and asset-tags to the smbios type17 tables by making use of a DIMMs controller-ID. This way we avoid name clashes when, for example, two DIMMs share the same channel-ID and DIMM-ID but have a distinct controller-ID. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I8aef79faa43f2475485f581c675ee152e580f678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-17soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/google/skyrim/var/winterhold: Update touchscreen devicetree settingEricKY Cheng
Update touchscreen setting. Change hid as panel team request to fix touchscreen with no function. The panel team verification result is on b/251378772 comment#17. BUG=b:251378772 TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is functional. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I07d446111b1c18bfe15d00b6eacff23382cd461a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-17soc/intel/broadwell: Fix out() parameter orderKyösti Mälkki
Change-Id: I0897acddd00bad89a5fd784f82380ed0d0d2c06e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69703 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17sb/intel/i82801dx/bootblock.c: Include "i82801dx.h"Elyes Haouas
Change-Id: I58ff31ab98c4310478cf3bbe8aecce4000ac8205 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69717 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17soc/intel/meteorlake: Implement report_cache_info() functionDinesh Gehlot
Make use of deterministic cache helper functions from Meteor Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 32768 Cache size = 24 MiB Port of commit 55f5410fcd78 ("soc/intel/alderlake: Implement report_cache_info() function") BUG=none TEST=Build and Boot verified on google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I561658c8da0136d6c3d9578f22f5d320e542457d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69681 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17intel/haswell,lynxpoint: Fix out() parameter orderKyösti Mälkki
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-11-17nb/intel/ironlake,sandybridge/gma: Fix out() parameter orderKyösti Mälkki
Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17mb/google/rex: Add `disable_gpio_export_in_crs` for rexSubrata Banik
None of the touchscreens (over I2C) used in the rex program requires exporting GPIOs in the ACPI _CRS method. This can cause i2c devices to malfunction or cause timing sequence violations if ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS. BUG=none TEST=Able to build and boot Google, Rex platform. Without this patch: [ERROR] I2C: 00:10: Exposing GPIOs in Power Resource and _CRS With this patch: None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69612 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/google/nissa/var/pujjo: Tune timing on SD device RTD3Leo Chou
Tune timing between power on and reset on SD device RTD3. BUG=b:250746988 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I1ea77ec8381000249229653f1c0b9044bdf7866d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-11-17arch/{arm64,riscv}: Remove "CRIT: " from log messagesElyes Haouas
It is no longer necessary to explicitly add "CRIT: " in front of BIOS_CRIT message. Change-Id: I506c1d278960c91d1283e9b1936c9c1678a10e17 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17commonlib/storage/sdhci.c: Remove "ERROR: " from log messageElyes Haouas
It is no longer necessary to explicitly add "ERROR: " in front of BIOS_ERR message. Change-Id: I36e2785ae567d82339212140c1bde0876dfd450d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17drivers/uart/Kconfig: Drop unused Kconfig symbolElyes Haouas
Change-Id: I43e6b57477cb4fd2c8ab399e9cc74591b0a44684 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17cpu/x86/Kconfig: Drop unused Kconfig symbolElyes Haouas
Change-Id: Id50ebecdaddcce426b15d535afcc3e755f2c5a35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17nb/amd/pi/Kconfig: Drop unused Kconfig symbolElyes Haouas
Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69333 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/intel/common/block/sgx/Kconfig: Add missing default symbolElyes Haouas
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB. Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/amd/common/pi/def_callouts.c: Fix log messagesElyes Haouas
It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing modeReka Norman
As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, 1 and 2 are already checked. Add a check for 3 as well. Also add logs for each individual criteria so it's easy to tell why the overall Manufacturing Mode is set or not. BUG=b:255462682 TEST=On a nivviks which has not gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO After: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO On an anahera which has gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES After: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES [DEBUG] ME: FPFs Committed : YES [DEBUG] ME: Manufacturing Vars Locked : YES Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69324 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/alderlake: Update ME HFSTS register definitionRizwan Qureshi
Update Alder Lake CSME HFSTS registers definitions as per Intel doc #627331 revision 1.0.0, section 3.4.8. Follow up CLs will use the bit definitions for performing various checks. TEST=build and boot nivviks platform Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/starlabs/starbook/kbl: Drop redundant option codeAngel Pons
Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake: Hook up FSP hyper-threading setting to option API") already hooks up the `hyper_threading` CMOS option in SoC code, so there's no need to do it from mainboard code. Change-Id: I602452266a8465cced12454f800ea023f382ba6f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/supermicro/x11-lga1151-series: Fix CMOS optionsAngel Pons
The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17sb/intel/i82801dx: Improve LPC device early initKyösti Mälkki
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17sb/intel/common: Fix GPE0 related register conflictKyösti Mälkki
When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be. For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT. On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS. Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-17sb/intel/common: Drop duplicate smi_set_eos()Kyösti Mälkki
We have equivalent southbridge_smi_set_eos(). Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17mb/emulation/qemu-q35: Split smm_close() and smm_lock()Kyösti Mälkki
Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEGKyösti Mälkki
If TSEG is not enabled, smm_region() should not reserve the region, so add a test for T_EN flag in ESMRAMC. For the SMM_ASEG case this moves CBMEM immediately below top-of-ram. Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17soc/intel/meteorlake: Enable FSP multiphasezhaojohn
This patch changes the UPD EnableMultiPhaseSiliconInit to enable the Meteor Lake FSP multiphase flow. BUG=b:247670186 TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable. [SPEW ] Executing Phase 1 of FspMultiPhaseSiInit [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/ fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] port C0 DISC req: usage 1 usb3 1 usb2 2 [DEBUG] Raw Buffer output 0 00000211 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded [DEBUG] port C1 DISC req: usage 1 usb3 3 usb2 4 [DEBUG] Raw Buffer output 0 00000431 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-17Revert "mb/google/herobrine: Remove NVMe from device tree"Shelley Chen
This reverts commit d164feb72602da958b644643b44e754f04a1f281. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17Revert "soc/qualcomm/sc7280: Remove NVMe init"Shelley Chen
This reverts commit 1b07797a7b79ea6c11421b61b9cf14b92cb91c66. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VDIan Feng
ALC5682-VS/ALC5682-VD use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682I-VS: _HID = "RTL5682" ALC5682-VD: _HID = "10EC5682" BUG=b:246491349 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing modeSridhar Siricilla
As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, #1 and #2 are already checked. Add a check for #3 as well. TEST=Build and boot MTL RVP Snippet from coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-17soc/intel/meteorlake: Update CSE firmware status registersSridhar Siricilla
The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs the firmware status details as per the new register definition. TEST=Build and boot the coreboot on Rex Snippet from coreboot log with the patch: [DEBUG] ME: CPU Debug Disabled : NO [DEBUG] ME: TXT Support : NO Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/meteorlake: Hide PMC and IOM devicesKapil Porwal
Hide these ACPI device so Windows does not warn about missing device drivers. Port of commit 907c85ad48dd ("soc/intel/alderlake: Hide PMC and IOM devices"). BUG=none TEST=Verified _STA method from ACPI tables in OS. USB-C drive is detected in OS. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic62172bee9120d260a3cd60770ef780cb7dce860 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69576 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00vjadeja-intel
Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/nissa/var/yaviks: Enable ISH driver and firmware nameWisley Chen
Enable ISH driver and set firmware name as "adl_ish_lite.bin" BUG=b:242291814 TEST=boot into kernel, and check dmesg "ISH firmware intel/adl_ish_lite.bin loaded" Change-Id: I4badabba1a0cfceb77fc91f21953496152f19615 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69606 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16util/testing: Move check of intel-sec-tool to separate targetMartin Roth
Testing for the presence of intel-sec-tools doesn't need to happen inside the what-jenkins-does target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6faa5bd5292ac5cceba9a64fe81939c0e25b9f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16mb/google/brya/var/agah: Add Power Limits for RPL SKUTarun Tuli
Add power limits for the RPL SKUs of Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-16mb/google/brya/variants/volmar: Update ELAN touchscreen timingRen Kuo
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the volmar's delay time to follow the requiremnet. BUG=b:257073343 TEST=Build firmware and measure the T3 timing of resume and boot up on volmar DUT. Run Suspend/Resume with UI test and got pass. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-16mb/aopen/dxplplusu: Iterate CPUs for ACPI MADTKyösti Mälkki
Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-16cpu/x86/smm: Use common SMM_ASEG regionKyösti Mälkki
Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16arch/x86: Disable clang build if using verstage_before_bootblockMartin Roth
Clang isn't working so well with the ARM code yet. This is still breaking builders after fixing the compiler warnings. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16Documentation: Add some more acronyms to the listMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2022-11-16arch/arm/armv7: Don't set gcc specific options for clang buildsMartin Roth
Clang doesn't understand the -Wa,-mno-warn-deprecated option. Remove it for now. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9f91d6ec2db247e901ba9bc41bc4b888bbe43236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-16drivers/intel/fsp2_0: add log level parameter to fsp_print_guidFelix Held
Not all functions that call fsp_print_guid print their output with the BIOS_SPEW log level, so introduce a new log level parameter so that the caller of fsp_print_guid can specify which log level fsp_print_guid should use for printing the GUID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/common: Don't set gcc specific options for clang buildsMartin Roth
Clang doesn't understand the -Wstack-usage=40960 option. Replace it with -Wframe-larger-than=40960. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16mb/google/skyrim/var/winterhold: Update DPTC setting for SMTEricKY Cheng
Follow Dynamic Thermal Table Switching proposal to initialize thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:232946420, b:258572474 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-16mb/google/skyrim: Create crystaldrift variantChao Gui
Create the crystaldrift variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_CRYSTALDRIFT Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16mb/google/zork: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in commit 22683fab (mb/google/skyrim: Use detect vs probed flag for touchscreens) Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69457 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16mb/google/zork: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard tables set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors the change to skyrim in commit f90ff456 (mb/google/skyrim: Implement touchscreen power sequencing) Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SBSubrata Banik
This patch uses index 0x10 for IOE P2SB memory resource allocation instead of static 0. Additionally, switches to `mmio_resource` from `mmio_resource_kb`. TEST=Able to build and boot Google/Rex and observed log as below. Without the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 0 With the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-16mb/google/nissa/var/craask: Correct G2 touchscreen HIDTyler Wang
Correct G2 touchscreen HID to GT75CH02. BUG=b:235919755 Test=Dump the SSDT on craask and check the HID had been modified. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 13:45:06 +0000