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2020-11-23soc/intel/alderlake: Update UART0 GPIO as per latest schematicsSubrata Banik
UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23mb/intel/adlrvp: Enable pre-boot display over HDMI-B portSubrata Banik
List of changes: 1. Configure CTRLCLK and CTRLDATA for HDMI 2. Enable Ddc and HPD for Port-B 3. Disable dual eDP configuration for Port-A and B TEST=Able to see depthcharge pre-boot screens over HDMI-B port. Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZESubrata Banik
According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang. Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22libpayload/usb: Add format string checking to usb_debugCaveh Jalali
This turns on the compiler's printf style format string checker. BUG=b:167517417 TEST=enabled all USB controllers on volteer and fixed resulting compiler errors when USB_DEBUG is enabled. Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22libpayload/usb: Fix printf format string mismatches in debug messagesCaveh Jalali
This fixes format string mismatch errors in the USB subsystem found by the compiler's format string checker. BUG=b:167517417 TEST=enabled all USB controllers on volteer and fixed resulting compiler errors when USB_DEBUG is enabled. Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ↵Bora Guvendik
UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and ↵Bora Guvendik
UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22tests: Add lib/cbmem_console-test test caseJakub Czapiga
Add test case executed twice, once for ROMSTAGE and once RAMSTAGE. Each test is named and visible in cmocka output with stage in its name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I464eee61f538188427bec730d2e004c7b76cca67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-22soc/ti/am335x: Fix timer implementationSam Lewis
Implements the monotonic timer using the am335x dmtimer peripheral. Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22soc/ti/am335x: Enable MMU in bootblockSam Lewis
Enables the MMU primarily to allow the unaligned word reads that the FMAP code requires. Without enabling this, the chip gets data access exceptions. Enabling the MMU also gives some advantages in allowing the icache and dcache to be enabled, so is probably worth doing regardless. Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/ocp/deltalake: Override SMBIOS type 4 cpu voltageTim Chu
Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-22util/docker: Minor Makefile updatesMartin Roth
- Update url for docker install instructions. - Update docker-cleanall target to require verification. - Update docker-jenkins-attach target to check for docker and use docker variable. - Update spaces to tabs in the docs targets. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ic1e1a545024fe1fdc37d7d8c7e6f54f124d1697b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-22util/crossgcc: Retry package downloads on failureMartin Roth
For whatever reason, I've had buildgcc fail to download packages a number of times. Adding 2 additional retries before failing helps with that problem. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I060eaa5a0da955436169e2199c1c62044dcfd5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-22mb/google/puff/var/dooly: update USB2 type-c strengthTony Huang
Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-11-22nb/amd/pi: Remove 00660F01 directory & filesMartin Roth
These files are not used by any platform, so remove them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/volteer: Remove unused devices for terrador and todorDavid Wu
Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22crossgcc: Upgrade nasm to version 2.15.05Elyes HAOUAS
Changes (https://nasm.us/doc/nasmdocc.html): Version 2.15.05: Correct %ifid $ and %ifid $$ being treated as true. Add --reproducible option to suppress NASM version numbers and timestamps in output files. Version 2.15.04: Correct the encoding of the ENQCMDS and TILELOADT1 instructions. Fix case where the COFF backend (the coff, win32 and win64 output formats) would add padding bytes in the middle of a section if a SECTION/SEGMENT directive was provided which repeated an ALIGN= attribute. This neither matched legacy behavior, other backends, or user expectations. Fix SSE instructions not being recognized with an explicit memory operation size (e.g. movsd qword [eax],xmm0). Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44694 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22crossgcc: Upgrade IASL to version 20200925Elyes HAOUAS
This release added support for SMBus predefined names: _SBA, _SBI, _SBR, _SBT and _SBW. CB:44507 and CB:41735 needs this version. Change log: https://acpica.org/node/184 Change-Id: I3559e5bd884db4dccdaa5ac7edba4faf57da7930 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-11-22vendorcode/eltan/security: Add dependency for menu itemsFrans Hendriks
Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are always displayed. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22drivers/tpm: Move PPI stubPatrick Rudolph
As preparation to a full PPI implementation move the acpi code out of the pc80/tpm/tis driver into the generic tpm driver folder. This doesn't change any functionality. Change-Id: I7818d0344d4a08926195bd4804565502717c48fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/facebook/fbg1701/Kconfig: Add dependencyFrans Hendriks
VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22soc/intel/xeon_sp: Work around FSP-T not respecting its own APIArthur Heymans
The CPX FSP-T does not respect the FSP2.x spec and uses registers where coreboot has its initial timestamp stored. If the initial timestamp is later than some other timestamps this messes up the timestamps 'cbmem -t' reports as it thinks they are a result from a timestamp overflow (reporting that it took 100k years to boot). TEST: The ocp/deltalake boots within the span of a lifetime. Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/octopus: fix droid lte sku load specific wifi sar valueSheng-Liang Pan
This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex. BUG=none BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/amd/microcode: Remove dead MakefileArthur Heymans
Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmclib.c: Properly guard apm_control()Arthur Heymans
This function is only properly implemented with SMM support. Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/common/pmc.c Don't implement a weak function that diesArthur Heymans
Buildtime failures are better than runtime failures. Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Only include the PCI driver when it is not hiddenArthur Heymans
On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.cArthur Heymans
pmc.c mostly contains a PCI driver, while this function just calls into SMM. Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22MAINTAINERS: update maintainers of Intel Denverton-NS SoCMariusz Szafranski
Change-Id: Ifdb24f9566b53af6c23b4cd4adba0c1876e4fc9d Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian <d.guckian20@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-11-22soc/intel/denverton_ns: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2020-11-22mb/google/volteer/var/voema: Update gpio and devicetree settingsDavid Wu
Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/facebook/fbg1701: Add VBOOT supportFrans Hendriks
Add VBOOT support. Disable USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-11-22drivers/i2c/hid: Use ACPI device name if provided by configMatt DeVillier
Follow model of drivers/i2c/generic and use user-supplied device name if specified in the chip config. Change-Id: Ia783bac2797e239989c03a3421b9293a055db3d0 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47782 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22drivers/i2c/generic: Only write DDN field if description not emptyMatt DeVillier
DDN field isn't required, no point in writing an empty string to it. Change-Id: Ifea6e48c324598f114178e86a79f519ee35f5258 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47781 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22Documentation: Mention newer Intel μ-code updates in 4.13 release notesPaul Menzel
Start a new section *Notes* for these kind of information. Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22drivers/i2c: Add a driver for Semtech SX9324Eric Lai
This adds a new driver for the SX9324 proximity detector device. Follow SX9324 datasheet Rev3. BUG=b:172397658 BRANCH=zork TEST=Test sx9324 is working as expected. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd582482728a2f535ed85f6696b2f5a4529ba421 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47640 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22Doc/releases/checklist.md: Fix up URLsAngel Pons
Use angle brackets so that they appear as links, and update a link to a Gerrit change to use the current format. Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22Doc/releases/checklist.md: Add reminder to unpack relnotesAngel Pons
Explicitly add this easy-to-forget step. Also add a missing period. Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22payloads/external: Fix up SPDX license headersAngel Pons
Remove copyright notices and other unnecessary churn. Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47815 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22payloads/external/Makefile.inc: Fix SeaBIOS option regressionsAngel Pons
Commit 14ca7407196 (Makefile.inc: Move adding SeaBIOS cbfs config files) introduced various regressions that were not spotted during review. TEST=Building with SEABIOS_THREAD_OPTIONROMS is working properly again. Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47814 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/kontron: Add Kontron mAL10 COMe module supportMaxim Polyakov
This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T outputFrans Hendriks
Report the FSP temporary RAM location Tested on Facebook FBG1701 Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22drivers/intel/fsp1_1: Add function to report FSP-T outputFrans Hendriks
This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols. Tested on Facebook FBG1701 Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area onlyFrans Hendriks
Whole car region is cleared, while only small part needs to be done. Clear .bss area only Tested on Facebook FBG1701 Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/sarien: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-22mb/google/brya: Add new google brya mainboardTim Wawrzynczak
This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-11-22vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFSFurquan Shaikh
If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22util/inteltool/ivy_memory.c: Do not rely on MR0 valuesAngel Pons
MR0 may not always be programmed in the training result registers. Thus, do not rely on its values. Also account for per-channel differences. Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-22util/inteltool/ivy_memory.c: Properly mask tAONPDAngel Pons
This field is only 4 bits wide. Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
This register needs to be updated differently depending on the CPU generation and stepping. Handle this as per reference code. Further, introduce a bitfield for the register to make the code easier to read. Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
Values differ between Sandy and Ivy Bridge. Remove the lookup table, since it contains duplicated values and is hard to see which values correspond to which frequencies. New values come from reference code. Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded valueFelix Singer
Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Make helper for write leveling sequenceAngel Pons
Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Remove a potentially-outdated comment. Proper documentation will be written once code refactoring and various improvements are complete. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD registerAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRCMDPICODINGAngel Pons
This register's layout makes no sense, so use bitfields for clarity. Tested on Asus P8H61-M PRO, still boots. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Move constants out of for-loopAngel Pons
Most per-channel registers are programmed with the same values. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Use bitfields to program MCMAIN timingsAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up TC_OTHP writesAngel Pons
ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use one sequence for write levelingAngel Pons
In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/zork: update berknip CHTC thermal settingKevin Chiu
Update APU CHTC thermal temperature protection point: Temperature limit(C'): 90 Update system config=2 to meet TDP 15W design. BUG=b:162377903 BRANCH=zork TEST=1. emerge-zork coreboot 2. check CHTC temperature by AMD utility Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-22soc/amd: move non-CAR linker scripts to common directoryFelix Held
AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-22sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDsAngel Pons
These two IDs are for Cougar Point and Panther Point, the previous generation of Platform Controller Hubs. So, drop their device IDs. Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-21util/amdfwtool: add missing zero-initialization for local variableFelix Held
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21soc/amd: factor out vbnv_cmos_failed() into soc/amd/common/vbootFelix Held
Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik
List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21mb/google/asurada: Get RAM code from ADC 3Yidi Lin
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Asurada the RAM code can be read from ADC channel 3. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21cbfs: Add metadata cacheJulius Werner
This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-21nb/intel/sandybridge: Introduce `disable_refresh_machine` functionAngel Pons
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop. Tested on Asus P8H61-M PRO, still boots. Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21intel/socket_441: Increase bootblock sizeJulius Werner
One mainboard using this socket has less than 20 bytes of space left in its bootblock, hindering development. Double the bootblock size to solve the problem. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I620c13eab53c3326a4f4660b63ed1dd0fc81f563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21Update vboot submodule to upstream masterJulius Werner
Updating from commit id 4c523ed1: vboot2: Add support for modexp acceleration to commit id 9d4053df: Revert "Reland: Clean up implicit fall through." This brings in 32 new commmits. Among the changes are restored support for older GCC/clang versions that do not support __attribute__((fallthrough)). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21zork: Create gumboz variantKevin Chiu
Create the gumboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:173536689 BRANCH=zork TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_GUMBOZ Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update DRAM table for dirinbozKevin Chiu
Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:173480390 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21util: Add new DDR4 H5ANAG6NCJR-XNC for zork boardsKevin Chiu
Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=None TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update telemetry settings for WoomaxKane Chen
Update Woomax to improve the performance. BUG=b:168073070 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-21include/device/pci_ids: add PCI IDs for new AMD SoCsFelix Held
Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10John Su
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC) activation. BUG=b:171531244 TEST=build and verify by thermal team Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Rename loop variableAngel Pons
The `discover_edges_real` function actually tests a range of values for DQS PI and evaluates how the system responds. Rename the loop variable. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/zork: Remove 50ms WIFI delayMartin Roth
As a part of trying to get our boot time as low as possible, any delays in the code should try to be refactored out. This removes the 50ms delay in the WIFI sequence by enabling power and putting the wifi module into reset in bootblock, then bringing it out of reset in ramstage. This is significantly longer than the 50ms requirement. The reset GPIO was already being set high in ramstage, so that code didn't need to be added. BUG=b:171513520 TEST=Boot on boards with different module types, WIFI works on both. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20intel/fsp2_0: Add soc_validate_fsp_version for FSP version checkJohnny Lin
Only need to check this once so check it at romstage where the console is usually ready. Also define union fsp_revision to avoid code duplication. Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-20mb/google/volteer/var/elemi: Update gpioWisley Chen
1. Config EN_PP3300_SSD (GPP_B2) to gpo 2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11 3. WLAN_PERST_L (GPP_H10) change to GPP_H10 BUG=b:172630765, b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/var/elemi: enable Genesys Logic GL9763EWisley Chen
Enable Genesys GL9763E as PCI-to-eMMC bridge. BUG=b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESAPaul Menzel
Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing the connected network device also to be missing. This is caused by not configuring the third of the four PCIe General Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be exposed as one to four PCIe devices. So, enable it in AGESA but disable enumeration in coreboot. Otherwise, the serial console stops working in romstage after […] PCI: 00:15.1 bridge ctrl <- 0013 PCI: 00:15.1 cmd <- 06 PCI: 00:15.2 bridge ctrl <- 0013 PCI: 00:15.2 cmd <- 07 and the system hangs in the payload (SeaBIOS banner is shown on VGA attached monitor). TEST=Serial console and payload works, and Linux 5.10-rc2 configures PCIe bridge. Output of `lspci -t`: -[0000:00]-+-00.0 +-00.2 +-01.0 +-01.1 +-10.0 +-10.1 +-11.0 +-12.0 +-12.2 +-13.0 +-13.2 +-14.0 +-14.2 +-14.3 +-14.4-[01]-- +-14.5 +-15.0-[02]-- +-15.1-[03]----00.0 +-15.2-[04]----00.0 +-18.0 +-18.1 +-18.2 +-18.3 +-18.4 \-18.5 Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20Makefile.inc: Add CARRIER_DIR to component discoveryMaxim Polyakov
The idea is to split the “mainboard” category into “variants” and “carrierboards”, in the case when we use the COMe module together with the Carrier Board instead of a single monolithic motherboard. Previously, the “variants” category defined the type of motherboard, which has a number of differences from the base one, for example, it differed in the size or type of memory, and in the configuration of the interfaces. Thus, there is no need to create a separate directory in src/mainboard for a board that is similar in configuration to the base board. But for a COMe module, “variants” contains different variants of only this module, and the entire Carrier Board configuration is allocated to a separate category - “carrierboards”, and each of the variants can be used with one of the many boards in “carrierboards”. For example, in the case of the Kontron mAL10 COMe module, variant refers to the COMe-mAL10 or COMe-m4AL10 module type. They differ in the type of memory (DDR3L or DDR4), and maybe they differ in some chips (see more in https://www.kontron.com/products). However, all variants contain the same type of processor/SoC. The "carrierboards" directory can be able contain both the Kontron's Evalution carrier boards (such as Eval Carrier2 T10 and COMe Ref.Carrier-i T10 TNI) and third party vendor backplanes that are compatible with the COMe modules from “variants”. Thus, the src/mainboard/<module-name> directory contains the common configuration code for all variants from src/mainboard/<module-name>/ variants, which can be supplemented/redefined with a configuration from src/mainboard/<module-name>/carrierboard/<vendor-carrierboard-name>. This architectural solution will be able to systematize and simplify understanding of the code structure for COMe modules and will allow vendors to add/maintain their code in a separate directory. This work is also the first step towards to union of all carrierboards into the global category in src/carrierboard on a par with all boards from src/mainboard. The patch takes this into account in the build system and adds CARRIER_DIR component to use the “carrierboards” category, as it has done for VARIANT_DIR. TEST = Build ROM image for Kontron mAL10 COMe module together with T10 TNI carrier board (https://review.coreboot.org/c/coreboot/+/39133). Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20vc/intel/fsp2/denverton_ns: Remove unused filesFelix Singer
The Denverton-NS SoC uses the header files from the FSP git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:30:37 +0000