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2022-02-15soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboardMatt DeVillier
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1] moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig, but in doing so inadvertently disabled HECI1 for Puff-based boards which previously had HECI1 enabled by default. To correct this, move the Kconfig selection back into the mainboard Kconfig, and set defaults to match values prior to refactoring in 805956bce. Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and ensure Disable HECI1 option defaults to selected for all except Puff. Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKEMatt DeVillier
Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1] switched CNL-based mainboards from using FSP for HECI disablement to SBI msg, but this causes google/hatch to hang when attempting to unhide p2sb as part of disabling HECI1 via SBI during SMM, so switch to using PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not support PMC disablement method, so they remain using SBI. Test: build/boot google/hatch, verify HECI1 disabled via console log and lspci in booted OS. Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.cMatt DeVillier
Move cse_disable_mei_devices() from cse_eop.c into heci_disable.c, so that platforms needing to use heci1_disable_using_pmc() can do so without requiring cse_eop.c be unnecessarily compiled in as well. This will allow Cannon Lake platforms to use PMC to disable HECI1 instead of SBI, which is currently causing a hang on google/hatch (and will be changed in a follow-on patch). Test: build test google/{ampton,drobit,eve,akemi} boards to ensure no breakage. Change-Id: Iee6aff570aa4465ced6ffe2968412bcbb5ff3a8d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15mb/google/dedede/var/beadrix: Add LTE power off sequenceTeddy Shih
This change adds LTE power off sequence for beadrix. BUG=b:204882915 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: I11370bf69438465d2230e2633044ba42685a152b Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61329 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15soc/intel/apollolake: Fix overlapping ACPI resource rangesMatt DeVillier
The address space allotted to MCRS in the northbridge needs to be exclusive of the address space allotted to the GPIO controllers in the southbridge, otherwise Windows complains of overlapping resource ranges and disables the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS to set the upper bound of MCRS rather than MMCONF. Test: boot Windows 10/11 on google/{reef,ampton} and verify that GPIO controllers are indicated as without fault in Device Manager. Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
2022-02-15soc/intel/common/cse: Add `cse_send_end_of_post()` as a public functionSubrata Banik
This patch creates a global function `cse_send_end_of_post()` so that IA common code may get access to this function for sending EOP command to the HECI1/CSE device. Additionally, use static variable to track and prevent sending EOP command more than once in boot flow. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-15soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/xeon_sp: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/61652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/apollolake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/skylake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Additionally, move the PMCON status bit clear operation to finalize.c to cover any such chances where FSP-S NotifyPhase requested a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15mb/google/guybrush: Add a mainboard specific SPL tableZheng Bao
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/intel/elkhartlake: Fix PCR ID for eSPIWerner Zeh
According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file. [1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true Test=Read and modify PCR registers of eSPI controller. Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15Update blobs submodule to upstream masterZheng Bao
Updating from commit id b8e3eaf: 2021-07-15 08:09:11 +0000 - (mainboard/starlabs: Add files for Star Labs laptops) to commit id f14575c: 2022-02-14 21:14:23 +0800 - (mb/google/guybrush: Add SPL table) This brings in 11 new commits. 2021-07-15 08:09:11 +0000 - (mainboard/starlabs: Add files for Star Labs laptops) 2021-07-22 15:52:42 +0800 - (soc/mediatek/mt8195: Update MCUPM firmware from v1.00.00 to v1.01.00) 2021-07-22 17:11:04 +0800 - (soc/mediatek/mt8195: Add dram.elf for full calibration flow) 2021-07-29 16:19:31 +0800 - (soc/mediatek/mt8195: Add dpm.pm and dpm.dm version 1.0) 2021-10-06 16:18:46 +0800 - (soc/mediatek/mt8195: Update MCUPM firmware from v1.01.00 to v1.02.00) 2021-11-16 12:01:22 +0800 - (soc/mediatek/mt8186: Add MT8186 basic files) 2021-12-24 17:25:31 +0800 - (soc/mediatek/mt8186: Add SPM firmware) 2021-12-24 17:25:33 +0800 - (soc/mediatek/mt8186: Add SSPM firmware) 2022-01-21 10:30:35 +0800 - (soc/mediatek/mt8186: List `sspm.bin` in README) 2022-01-24 16:48:56 +0800 - (soc/mediatek/mt8186: Add dram.elf version 0.1.0 for DRAM calibration) 2022-02-09 14:53:44 +0800 - (soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1) 2022-02-14 21:14:23 +0800 - (mb/google/guybrush: Add SPL table) Change-Id: I0ced625982135c0cb7630cd0fb94cf78e3654673 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61935 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15mb/google/brya/var/nereid: Disable LTE-related GPIOsReka Norman
Nereid does not support the LTE sub-board, so disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Initialise overridetreeReka Norman
Add an initial overridetree for nereid based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Add H9JCNNNBK3MLYR-N6E for P1 buildReka Norman
Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=b:217096008 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15spd/lp5: Add new part H9JCNNNBK3MLYR-N6EReka Norman
Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya: Create kinox variantDtrain Hsu
Create the kinox variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215049181 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KINOX Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I68cac421f6299a5f82f2ab51633173648c993060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15drivers/wwan/fm/acpi_fm350gl.c: Fix bit checksAngel Pons
Fix always-true conditions to properly test whether a bit is set. Change-Id: I54b5dbfdbb99a47ef0dfdb9497179f516d6e1f23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/common/block/pcie/rtd3: Fix bit checksAngel Pons
Fix always-true conditions to properly test whether a bit is set. Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"MAULIK V VAGHELA
This reverts commit 9a7fbbc98e8610a0a5314470edd8d5dafe676a06. SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP Hob generation also skips syncing correct version of chipset data with CSE since FSP uses version information from MBP HOB. In absence of MBP Hob, FSP is unable to get version information and hence chipset data sync is skipped. This creates an issue while platform tries to enter deeper sleep states. BUG=b:215448362 BRANCH=None TEST= FSP can get version information from MBP HOB and chipset sync is performed. It has been Verified using FSP debug logs on Brya board. Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15soc/apollolake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-15soc/intel/cnl: Enable CSE FW sync for CSE LITE SKUMatt DeVillier
Boards based on google/puff baseboard (hatch variant) use CSE LITE, which utilizes RO and RW firmware. If the CSE does not switch to the RW firmware, the HECI1 interface is disabled, and dependent drivers (like SOF audio firmware) fail to load. Use the same logic as other platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW firmware update is available, and if not jump to the onboard RW firmware. Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware loaded via cbmem console, HECI1 interface is present vis lspci, and the SOF DSP firmware is correctly loaded via dmesg. Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/amd/sabrina: Select ACP gen2Fred Reitberger
Select ACP gen2 for Sabrina Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/amd/common/acp: add acp_gen2Fred Reitberger
The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15herobrine: update SPI-NOR config optionsT Michael Turney
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-15drivers: spi_flash: Addressing mode change for SPI NORT Michael Turney
As 4-byte addressing mode is not support in coreboot, change the addressing mode of SPI NOR from 4-bytes to 3-bytes. BUG=b:215605946 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-14mb/google/brya/var/vell: update gpio for DMICShon Wang
Data on channel 0 & 1 are normal (from DMIC) but there is noise on channel 2 & 3, so change to NF PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE), BUG=b:210802722 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14mb/google/guybrush: Enable power resource for BTRaul E Rangel
The `reset` gpio is currently being consumed by the btusb kernel driver. The functionality was added in https://crrev.com/c/3342774. The goal of the patch was to reset the BT device when command timeouts occur. This works, but it doesn't support the case where the BT device is having problems with USB enumeration. In that case the device can't enumerate so the driver can't help resetting the device. If we instead switch to using an ACPI power resource, the kernel can control the BT device's power. This is beneficial when the device is having USB communication problems since the kernel will try and power cycle the device. We don't lose the ability to reset the device on command timeouts either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if there is no `reset` GPIO. So win / win. This results in the following power resource: PowerResource (PR02, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x84) Sleep (0x01F4) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.STXS (0x84) Sleep (0x0A) } } I switched the device tree entry from using reset_gpio to enable_gpio because the acpi_device_add_power_res method asserts the reset in the _ON method unconditionally. This results in a small glitch on the line. By using the enable_gpio we get the correct behavior. I don't have a datasheet right now, so I just picked some values for the reset timing. The kernel driver was using 200ms. We can revisit the numbers when we get a datasheet. BUG=b:218295688 TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power resource is created on the kernel. This should allow the kernel to power cycle the device via usb_acpi_set_power_state. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-14mb/google/brya: Adjust FMD file for some boardsTracy Wu
When brya boards that use ChromeOS autoupdate update their firmware, devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to replace IOM and NPHY BPDT firmware in the CSE region. However, because of the way the autoupdate works, the CSE RO will not be updated during autoupdate. This means that these boards now have different stitching schemes between CSE RO and RW and this causes the sub-partition update to fail and the boot hangs. To remedy the situation for these boards, a separate FMD files is provided so they can continue to use the cse_serger tool for stitching. The only boards affected were kano and brask, so they are updated here. BUG=b:218376385 TEST=use flashrom to downgrade to 14474 then use futility to update to image with this patch and system boots. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-14drivers/smmstore/store.c: Add fmap_config.h dependencyArthur Heymans
This fixes building with -jx Change-Id: I51efc03839c53b96fa248e6fe5dc0e00b773aa53 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-14soc/intel/graphics: Repurpose graphics_get_memory_base()Ethan Tsao
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory base if required, because it may vary by platfrom. BUG=b:216756721 TEST= Check default offset for existing platform and update platform specific offset in Kconfig under SoC directory. Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14mb/google/brya/var/brask: Enable ASPM of RTL8125Alan Huang
Brask cannot pass powerd_dbus_suspend test because the NIC does not enter ASPM L1.2. Here we add "enable_aspm_l1_2" in devicetree for RTL8125 to enable ASPM L1.2. BUG=b:204309459 BRANCH=None TEST=emerge and test with command powerd_dbus_suspend Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-14drivers/net/r8168: Add ASPM control mechanismAlan Huang
Add a new configuration parameter "enable_aspm_l1_2". Write value 0xe059000f to register offset 0xb0 to allow kernel driver to enable ASPM L1.2. Use Kconfig "PCIEXP_ASPM" and "enable_aspm_l1_2" to decide whether to enable ASPM L1.2. BUG=b:204309459 TEST=emerge and test if the driver can read the correct value Change-Id: I944dbf04d3ca19df4de224540bee538bff4d1f12 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-13mb/amd/chausie: update GPIO for chausieFred Reitberger
Add/update initial GPIO pin descriptions and initialization types for chausie mainboard. Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-13soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUSFelix Held
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12arch/x86/id.S: Fix building with clangArthur Heymans
The following error message is now gone: CC bootblock/arch/x86/id.o /tmp/id-35b17a.s:35:7: error: expected relocatable expression .long - ver ^ /tmp/id-35b17a.s:36:7: error: expected relocatable expression .long - vendor ^ /tmp/id-35b17a.s:37:7: error: expected relocatable expression .long - part ^ Tested with BUILD_TIMELESS=1 on x86_32 with gcc. The binary stays the same. Change-Id: I930e7b96c4428bcb95ff1903e6a3e7679171ffee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12soc/intel/apl: Use Kconfig to enable CseRbpSean Rhodes
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is memory mapped and ensures SkipCseRbp UPD is guarded against this config. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12mb/google/dedede/var/beadrix: Add LTE modem supportTeddy Shih
This change adds LTE modem for beadrix. BUG=b:204882915 BRANCH=dedede TEST=Build and boot beadrix, check with command modem status Change-Id: I7acb88634478ff486810b2c3fc14d6739c3268e1 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61328 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1. BUG=b:215599230 TEST=Build guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12arch/x86/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Iabfaaee22011a75cc981607d366d61660838ab21 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/brya/var/agah: Update Aux settingsTony Huang
Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/nissa: Set half_populated trueKrishna Prasad Bhat
Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-12sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config'Elyes HAOUAS
Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cacheWerner Zeh
The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in a recovery state for different reasons. In this case we still want the MRC cache to be around to avoid the DRAM retraining on every boot. This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes the already available MRC recovery region in FMAP useable. Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC cache is used. Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-02-12soc/amd/cezanne: Allow to specify SPL table path in KconfigZheng Bao
BUG=b:216096562 Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/majolica/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing on Chausie that was a 1:1 copy caused some issues with the I2C driver, so port the Chausie IRQ mapping change back to Majolica. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/chausie/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. This should fix these errors: [ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found [ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found [ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found [ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-12mb/google/guybrush/var/nipperkin: Add _HID for privacy screen deviceKevin Chiu
BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot dump SSDT, see _HID instead of _ADR Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/amd/common: Scan bridge devices behind SoCs GPU ControllerKevin Chiu
Scan devices behind SoCs GPU controller to expose more buses. BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12amdfwtool: Add options to support mainboard specific SPL tableZheng Bao
For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12util/inteltool: Actually read SATA init data from SIRDBenjamin Doron
Fix issue where registers always seem to contain their own offset. After writing the desired register into SIRI, the requested data is returned in SIRD. This register is 4 bytes after SIRI, commonly 0xA4. Tested on TGL-H (SATA SIR registers are common), genuine data is returned. Change-Id: I322b11d53178e5b64e353c1b4e576548592c16c3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-12soc/mediatek: Fix printing SPM versionYu-Ping Wu
Currently the SPM version string is stored at the end of the blob, possibly without a trailing '\0'. Therefore, we should be careful not to print characters beyond the blob size. BUG=b:211944565 TEST=emerge-corsola coreboot TEST=SPM version looked good in AP console BRANCH=asurada,cherry Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11util/chromeos/crosfirmware: Handle "broken" recovery imagesMatt DeVillier
Several recovery images for newer ChromeOS boards fail in extract_partition() due to parted detecting that there are overlapping partitions, and therefore failing to print the partition layout (this is potentially a parted bug; requries further investigation). To work around this, fall back to using fdisk, making the assumption that ROOT-A is always partition #3, and calculate the partition start and size using the sector size. Test: successfully extract coreboot firmware images from recovery images which previously failed to extract (fizz, octopus, volteer). Change-Id: I03234170ba0544af9eb0879253f0a8e0e7bf33f5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11util/chromeos/crosfirmware: Fix handling of newer boardsMatt DeVillier
Wile historically there was a unique recovery image for each Chrome OS board/HWID (with matching names), this is no longer the case. Now, multiple boards share a single recovery image, so adjust how the proper recovery image is determined, and how the coreboot image is extracted from it. Test: successfully extract coreboot images for older 1:1 boards (e.g. CAVE) and newer 1:N boards (e.g. DROBIT) Change-Id: If478aa6eadea3acf3ee9d4c5fa266acd72c99b7a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11util/cbmem: Add --loglevel option to restrict console printing by levelJulius Werner
This patch adds a new --loglevel option to the CBMEM utility which can be used either numerically (e.g. `cbmem -1 --loglevel 6`) or by name (e.g. `cbmem -c --loglevel INFO`) to restrict the lines that will be printed from the CBMEM console log to a maximum loglevel. By default, using this option means that lines without a loglevel (which usually happens when payloads or other non-coreboot components add their own logs to the CBMEM console) will not be printed. Prefixing a `+` character to the option value (e.g. `--loglevel +6` or `--loglevel +INFO`) can be used to change that behavior. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8458027083246df5637dffd3ebfeb4d0a78deadf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMERCasper Chang
Config USE_PM_ACPI_TIMER to y for primus4es only as commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression) breaks suspend stress test on ES CPU SKU. BUG=b:211377699 TEST=USE="project_primus emerge-brya coreboot" and verified the suspend stress test works on primus4es. Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-11soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/fsp: check fsp image revisionJulian Schroeder
Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11src/arch/ppc64/*: pass FDT address to payloadSergii Dmytruk
It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-02-11arch/ppc64/boot.c: handle non-OPD entry pointSergii Dmytruk
Change-Id: I309be370d66a808b355241fcee880883631f38ce Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-11src/mainboard/emulation/qemu-power9: require hb-mode=onYaroslav Kurlaev
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11src/mainboard/emulation/qemu-power9: add RAM detectionYaroslav Kurlaev
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11ppc64/arch/mmio.h: ignore HRMOR and inhibit cacheYaroslav Kurlaev
Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboardYaroslav Kurlaev
Add initial implementation for booting on QEMU POWER9 emulation. Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc generated by gen_part_id using mem_parts_used.txt. BUG=b:218415732 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11soc/amd/common/block/lpc/espi_util: add decode range register helpersFelix Held
Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11soc/amd/common/block/include/espi: rename IO/MMIO base/size registersFelix Held
This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Implement WWAN power sequencingReka Norman
Nissa is using the FM101, which has the following power sequencing requirements: Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN Add a power resource to the USB device, and use wwan_power.asl to handle the power off sequence. BUG=b:217092522 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya: Support power sequencing for USB-only WWANReka Norman
Nissa is using the FM101 which is USB only. To allow us to reuse the existing wwan_power.asl for power sequencing, move the PCIe-specific part behind a new Kconfig HAVE_PCIE_WWAN. BUG=b:217092522 TEST=Build brya0 and check that generated dsdt.asl doesn't change. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Disable LTE-related GPIOs based on fw_configReka Norman
If the LTE USB DB is not connected, disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Initialise overridetreeReka Norman
Add an initial overridetree for nivviks based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-11src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADERTim Wawrzynczak
There may be occasions where an I2C device was initialized during "early initialization," but when used again in ENV_PAYLOAD_LOADER before resource allocation happens, it would currently return that it has not been assigned a BAR. However, because of the early BAR assigned to it, it should still be valid to use that until proper resources have been assigned, therefore return any BAR that may have been assigned to the device during early initialization. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-11drivers/i2c/tpm/cr50: Remove unused `chip` function argumentsTim Wawrzynczak
The `chip` argument passed around to many functions in this driver is actualy unused, so remove it where it is unused. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib8d32fdf340c8ef49fefd11da433e3b6ee561f29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-11lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'Elyes HAOUAS
Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-11soc/mediatek/mt8186: Lower SPI NOR speed to 52MHizYu-Ping Wu
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's HW design, which is capable of up to 52MHz. Therefore, lower the speed to univpll_d3_d8 (52MHz). BUG=b:218775654 TEST=emerge-corsola coreboot TEST=Boot time didn't increase significantly BRAHCH=none Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11ppc64/bootblock_crt0.S: minimal implementation for bootblock C environmentKrystian Hebel
BSS is loaded as part of the bootblock, it is zeroed in the file so it doesn't have to be cleared explicitly by the code. Code for clearing is left as a comment along with a warning about alignment requirements. Vector operations are sometimes generated for code such as 'uint8_t x[32] = {0}', this results in an exception when vector registers (VR) are not enabled. VSR (vector-scalar register) operations are also enabled, there is no reason not to. Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INITKyösti Mälkki
Fix regression after commit 9ec7227c9b cpu/x86/lapic: Move LAPIC configuration to MP init The call to disable_lapic() got removed and with asus/p2b SeaBIOS payload was unable to load kernel. The combination of entering SeaBIOS payload with an enabled lapic but not having programmed LAPIC_LVT0 for DELIVERY_MODE_EXTINT apparently disconnects i8259 PIC interrupt delivery pin. Change-Id: If51e5d65153a02ac7af191e7897c04bd4e298006 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-11src/arch/ppc64/arch_timer.c: implement timer functionsMichał Żygowski
Change-Id: I4a244df01f6d15cbefb3b01079f6eec943136983 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-11src/cpu/power9: add file structure for power9, implement SCOM accessIgor Bagnucki
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11soc/mediatek: Only update required bits when triggering WDT resetRex-BC Chen
To prevent to modify original value of wdt_mode, we use setbits32 to update required bits. BUG=b:218420108 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-10mb/google/octopus,reef: Align SMMSTORE region in default.fmdArthur Heymans
The SMMSTORE region needs to be 64K aligned or error will be thrown. Change-Id: I5d4f71f80c3219ac2c7000e1fa95fd04100d9cfe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-10drivers/smmstore/store.c: Add static assertion based on fmapArthur Heymans
Instead of having runtime failures that are hard to debug because SMM debugging is disabled by default assert some properties of fmap at buildtime. Change-Id: I5b5b511142d93d5799565a8936e9a087117044b3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-10drivers/intel/gma: Guard add_vbt_to_cbfs macroMatt DeVillier
Guard macro via CONFIG_INTEL_GMA_ADD_VBT, rather than guarding each of the calls to it (most of which are currently unguarded). Test: build google/coral w/ and w/o CONFIG_INTEL_GMA_ADD_VBT selected, verify VBTs added (or not) to CBFS based on Kconfig selection. Change-Id: Ic25554cb2c61b81bdb4b0987094c3558e0bbcbd8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/reef: Add VBTs for all variantsMatt DeVillier
Adjust Kconfig so all variants use proper VBTs. Add Makefile entries for variants which use multiple VBTs. extracted from ChromeOS firmwares: Google_Coral.10068.113.0 Google_Pyro.9042.233.0 Google_Reef.9042.233.0 Google_Sand.9042.220.0 Google_Snappy.9042.253.0 Change-Id: I46ad4ec321e32d019e44f0741956b18a464fb8ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/reef/coral/mainboard.c: Drop break after return inside switchMatt DeVillier
Drop unnecessary switch break after return, to alleviate linter warnings. Change-Id: I7cc49caaeafb490cb62b75ec5c3ca4822573464b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10mb/google/reef/coral: Sync mainboard.c with Chromium forkMatt DeVillier
Several commits were made to the Chromium coral branch (firmware-coral-10068.B) which were not committed upstream first. Pull them in here: 486ce56 mainboard/google/coral: Override VBT selection for babymako c1d7720 Babymako: add touchpad i2c speed config 911d547 mainboard/google/coral: Override VBT selection for babytiger 730a5af Babytiger: add touchpad i2c speed config 724711e rabbid: add the touchpad i2c speed config 80c5d16 mainboard/google/coral: Override VBT selection for babymega e8931a4 Babymega: add touchpad i2c speed config These add support for additional coral sub-variants. The I2C speed config changes were adapted to account for upstream changes not present in the coral Chromium branch. Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-10mb/google/reef: drop nasher variantMatt DeVillier
Release firmware on Nasher/Nasher360 are built as coral sub-variants; remove the old/unused code Change-Id: Ie8d10a31e663230b7deabf92e1c06cd991bbdccb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10Update arm-trusted-firmware submodule to upstream masterMartin Roth
Updating from commit id 73193689c: 2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration) to commit id e0a6a512b: 2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration) This brings in 324 new commits. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-10tests/include: Move EMPTY_WRAP() macro to tests/include/test.hJakub Czapiga
EMPTY_WRAP() might be useful for tests other than CBFS's ones. Move it to the main tests header file to make it easily accessible. Change-Id: Ic06c55912488681daf6d2c48cb0c879fa97ba4be Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-02-10Update qc_blobs submodule to upstream masterMartin Roth
Updating from commit id 98db386: 2021-08-03 11:57:30 -0700 - (herobrine: Add gsi_fw_blobs and Release Notes) to commit id 9ab0f0b: 2022-01-18 19:01:30 +0530 - (sc7280: Update AOP firmware to version 379) This brings in 13 new commits: 9ab0f0b sc7280: Update AOP firmware to version 379 826cb9c sc7180/boot : Update qclib blobs binaries and release notes ddf67d1 sc7280/ boot and shrm blobs updated 8592f11 sc7280: Update AOP firmware to version 364 aef8a0a sc7280/ boot and shrm blobs updated c72bc4e sc7280/cpucp: Update cpucp blobs binaries and release notes version from 054 to 060 33e57fe sc7280/boot,/shrm : Update qclib blobs binaries and release notes version 13 511851b sc7180/boot : Update qclib blobs binaries and release notes version 30 f91d0ef herobrine: qc_sec blob update 8c50f78 sc7180/boot : Update qclib blobs binaries and release notes 8523ef4 sc7180/qtiseclib: Update version from 26 to 44 5b77a37 sc7280/qtiseclib: Update version from 33 to 44 4815cc2 sc7280: Update AOP firmware to version 360 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I510141916900507fd29a0e9315a3f8d954bc0cab Reviewed-on: https://review.coreboot.org/c/coreboot/+/60825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-10Update intel-microcode submodule to upstream masterMartin Roth
Updating from commit id 3f97690: 2021-06-08 09:44:38 -0700 - (microcode-20210608 Release) to commit id 115c3e4: 2022-02-07 18:23:52 -0800 - (microcode-20220207 Release) This brings in 1 new commits: 115c3e4 microcode-20220207 Release Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idb2dcd3e3ef9692e21109ac0e8bdfa9f61740f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-10mb/google/brya: Create moli variantRaihow Shi
Create the moli variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:214439135 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MOLI Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I3f3bfd3db12cba8b73b351e7c700b6a58797c906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-02-10mb/intel/adlrvp: Fix vbt loading errorLean Sheng Tan
When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. The reason for having this function is that chromeOS has emerge tool to streamline the VBT stitching process to support multiple VBTs for different RVP boards; while we only need 1 vbt for generic non-chromeOS usage. Hence add a chomeos kconfig to guard this. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-10soc/intel/common: Add Crash Log and PMC SRAM PCI device IDsTim Wawrzynczak
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-10mb/google/dedede/var/magolor: Add custom Wifi SAR for magnetoTyler Wang
Add wifi sar for magneto. Due to fw-config cannot distinguish between magolor and magneto. Using sku_id to decide to load magneto custom wifi sar. BUG=b:208261420 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-02-10mb/google/volteer/var/drobit: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:204517112 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-10mb/google/volteer/var/copano: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:218245715 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 22:57:34 +0000