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2024-04-17mb/google/brya: Enable UFS driver for edk2 payloadMatt DeVillier
Several brya-based boards use UFS for storage, so enable the edk2 UFS driver when using the edk2 payload. TEST=build/boot google/brya (banshee, craaskov), verify internal boot media functional with edk2 payload. Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-17mb/google/zork: Enable eMMC driver for edk2 payloadMatt DeVillier
Several zork-based boards use eMMC for storage, so enable the edk2 eMMC driver when using the edk2 payload. TEST=build/boot google/zork (morphius, vilboz), verify internal boot media (both eMMC and NVMe) functional with edk2 payload. Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-17payloads/edk2: Add Kconfig to enable AMD Picasso eMMC driverMatt DeVillier
Add a Kconfig to selectively enable the AMD Picasso eMMC driver recently added to MrChromebox's edk2 fork. When selected, will enable booting from AMD Picasso devices with eMMC storage. TEST=tested with rest of patch train Change-Id: I6536a6f243f6766b913e295afebcf5b965e4e969 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81892 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17payloads/external: Call $(strip_quotes ) on prebuilt iPXE pathNico Huber
Currently, we keep the double-quotes from Kconfig, resulting in an invalid path. So just call `strip_quotes` like we do with all other paths from Kconfig. Change-Id: Ibcaa59be0fdd84d1fb9e061394fd9b0f7aa1830b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81947 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-17ec/google/chromeec: Update EC headersAseda Aboagye
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81932 Reviewed-by: Forest Mittelberg <bmbm@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-17mb/google/corsola: Add new board variant VeluzaFrank Wu
Add a new Krabby follower device 'Veluza'. BUG=b:333630131 BRANCH=corsola TEST=none Change-Id: Idedcbfbddd6d98a51cf28a0963d68f6d8c68382c Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81791 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-17mb/up/squared: Make mini PCIe port mode configurableReto Buerki
Add config choice menu and pad configuration to put Mini PCIe port into mSATA mode. The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has been used together with the output of inteltool and intel2pm to deduce the exact pad configuration. Note: the vendor firmware does not autodetect the mode, and the default setting for the port is "Mini PCIe". Tested with Kingston SUV500MS120G mSATA SSD. Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f Signed-off-by: Reto Buerki <reet@codelabs.ch> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-17arch/x86: Prevent .text/.init overlap with older linkersSubrata Banik
Add Kconfig option `X86_BOOTBLOCK_EXTRA_PROGRAM_SZ` to reserve extra space, avoiding overlap between .text and .init sections when using older linkers (binutils 2.3x). Default is 1024 bytes (1 KiB) for ChromeOS, 0 otherwise. BUG=b:332445618 TEST=Built and booted google/rex (32-bit/64-bit). Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81886 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-16mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)Joel Linn
This is another readily available (used market) system. Based on autoport. * All peripherals should work. * Automatic fan control as well as S3 are working. * The board was tested to boot Linux and Windows. EHCI debug is untested. * When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16superio/fintek/f81866d: Fix UART numbersMaxim Polyakov
Change-Id: I996b8e56d943e26ab426f1802ada07cde805286d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81915 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16buildgcc: Match the string of downloading percentage more preciselyZheng Bao
The command "wget" prints some hyperlink with "%", which will be filtered in by previous regular expression. So we need to change to match the string with exactly 3 digits and a percent symbol. TEST: echo 45% | grep -o "\<[0-9]\{1,3\}%" 45% echo 1245% | grep -o "\<[0-9]\{1,3\}%" <empty> echo aa% | grep -o "\<[0-9]\{1,3\}%" <empty> Change-Id: I6ef9e7c87fd4ee6cc707346954d91e6e3af3b939 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-16security/tpm: support compiling in multiple TPM driversSergii Dmytruk
Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69162 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16payloads/edk2/Makefile: Drop duplicated build string optionMatt DeVillier
The `PRIORITIZE_INTERNAL` option was somehow duplicated, so remove the extra copy, leaving the one under the MrChromebox repo specific settings. TEST=build qemu w/edk2 payload, check build log that the 'PRIORITIZE_INTERNAL' option is only added once to the build string. Change-Id: I4c4c433184d93337c926e256e77054afc00a2566 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-04-16mb/google/nissa/variant/sundance: Modify i2c device for touch deviceLeo Chou
1. Remove non-use i2c address 0x10, 0x24 and 0x40 of touch IC for touch screen 2. Add new i2c address 0x5d of Goodix touch IC for touch screen 3. Add new i2c address 0x38 of Focal touch IC for touch pad BUG=b:333804572 TEST=FW_NAME=sundance emerge-nissa coreboot chromeos-bootimage Change-Id: I8e2c60820a07b99b69860fd4f6557b448aef2341 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16payloads/edk2: Add Kconfig to enable UFS supportMatt DeVillier
Add a Kconfig to selectively enable the UFS DXE driver recently added to MrChromebox's edk2 fork. When selected, will enable booting from devices with UFS storage. TEST=tested with rest of patch train Change-Id: I0b54d21dc87abf6938c03948830f92ce5097ef7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81870 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16mb/google/nissa: Create pujjoga variantLeo Chou
Create the pujjoga variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:333839287 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGA Change-Id: Ia8eb11eb65f9013e83abd45eefe7705d05b8697e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81891 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-16sb/intel/ibexpeak: Sever bd82x6x source dependencyKeith Hui
It shares southbridge devicetree definition with bd82x6x, causing changes made there to break builds for boards with this PCH. Give ibexpeak its own copy. TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all. Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16mb/packardbell/ms2290: Correct header includedKeith Hui
It uses ibexpeak southbridge and should include its pch.h, not bd82x6x's. TEST=Timeless binary did not change. Change-Id: Iafa83b7f3c1cd2d8ab9af51aa331ca673d9a66df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-16nb/intel/haswell: Fix building BDW MRC.bin path with clangAngel Pons
Clang complains that the two enumerations are incompatible. However, the values themselves are the same (0: mobile, 1: desktop, 5: ULT). So, cast the function's return value to silence the warning. Change-Id: If7b5e22e893e9f3f17a15197c65448fb782590f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81862 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16sb/intel/lynxpoint: Fix AER and L1 sub-state reportingAngel Pons
Program the AER capability header register in a single write because it's write-once. In addition, only PCH-LP supports L1 sub-states, so only report the L1 sub-state capability on PCH-LP. This follows what Lynx Point PCH reference code version 1.9.1 does. Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16sb/intel/lynxpoint/pcie.c: Fix 0xf5 register maskAngel Pons
Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of the PCIe root port register at offset 0xf5. Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16lynxpoint/broadwell: Correct L1 exit latency with ASPMAngel Pons
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/zork: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot zork (morphius) with SMMSTORE enabled. Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/skyrim: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot skyrim (frostflow) with SMMSTORE enabled. Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/google/myst: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81867 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/guybrush: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot guybrush (dewatt) with SMMSTORE enabled. Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-15mb/amd/*: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81865 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15mb/google/fizz: Use variant-specific gma-mainboard.ads filesMatt DeVillier
The karma variant, being a Chromebase, has an internal eDP output for the built-in display whereas the fizz/endeavour variants do not. Use separate gma-mainboard.ads files so that karma's internal panel works properly with libgfxinit. TEST=build google/fizz (fizz/karma) with libgfxinit enabled, ensure correct gma-mainboard.ads file is included in the build. Change-Id: Ia6aca538ba8c13b48aa80901222071d704b5f0c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-15sb/intel/bd82x6x: Add four new USB currentsJoel Linn
Found by inteltool on HP Pro 3500 Series running vendor firmware version 8.14 Rev.A. Change-Id: I156787e533c2605e7440548a2d3bf711bb1af5d7 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15drivers/crb: use crb_tpm_ prefix instead of tpm2_Sergii Dmytruk
This prevents name clashes with drivers/spi/tpm and allows both to be potentially compiled in at the same time. Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-15mb/google/brox: Create greenbayupoc variantEren Peng
Create the greenbayupoc variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:329530883 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_GREENBAYUPOC. Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-15mb/google/corsola: Add new board variant SkittyHerbert Wu
Add a new Krabby follower device 'Skitty'. BUG=b:331702790 TEST=emerge-corsola coreboot chromeos-bootimage BRANCH=corsola Change-Id: I2f12bccfda591a5baf8d23d217b6f1f81b059d15 Signed-off-by: Herbert Wu <herbert1_wu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81772 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Geoffrey Chien <geoffrey_chien@pegatron.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2024-04-15acpigen_ps2_keybd: Add support for dictation keyAseda Aboagye
Some internal keyboards have a dictation key; this commit simply adds support for this key by adding the mapping from the scancode to the Linux keycode for use in the linux,physmap ACPI table. BUG=b:333101631 TEST=Flash DUT that emits a scancode for a dictation key, verify that it is mapped to KEY_DICTATE in the Linux kernel. Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-04-15soc/amd/picasso: Mark eMMC as non-removable for Windows 10/11 installCoolStar
Mark eMMC as non-removable to allow Windows 10/11 to install now that edk2 can boot from it. Change-Id: If0e14106521f99cb97d1bf421f4d82d1234c2f15 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-15src/mb: Rename new Makefile.inc files to Makefile.mkMartin Roth
These files were added after the switch. Change-Id: I1986e4f921e0e56fe5255433d4b9216dc7c4dc59 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81856 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15soc/intel/xeon_sp/spr: Use official microcodesPatrick Rudolph
Use the official microcode updates from intel-microcode submodule by default. Downstream users can still decide to use their own files. Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-04-15include: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented header. Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-14soc/intel/broadwell: Add ACPI CIDs for SerialIO devicesAngel Pons
Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-14lynxpoint/broadwell: Correct PCH-LP PCIe ASPM checkAngel Pons
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-14soc/intel/xeon_sp/spr: Drop microcode constraintsPatrick Rudolph
For current generation SPR/EMR you need to add at least 3 different microcodes having about 2MiB of size in total. This doesn't work with the hardcoded offset and size in Kconfig. Since it's loaded through FIT there's no need to pass it to FSP-T. Drop the hardcoded locations and place it somewhere in CBFS. Test: Booted on ibm/sbp1 with microcode confirmed loaded in bootblock on BSP. All the APs also have the correct microcode version loaded. TEST= Build and boot on intel/archercity CRB 'cat /proc/cpuinfo | grep microcode' result doesn't change before and after this patch. Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-14soc/intel/xeon_sp: Compress FSP-SPatrick Rudolph
Compress FSP-S to save some space in CBFS. Reduces the size of debug FSP-S by about 25%. Test: Still boots on ibm/sbp1. TEST= Build and boot on intel/archercity CRB. Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-14drivers/uart/pl011: Enhance struct documentationMaximilian Brune
Source: PrimeCell UART (PL011) Technical Reference Manual Revision: r1p5 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I58409b23e3790a052d3bc0ecf6a6bede15b4d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80180 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13mb/samsung/stumpy: Set initial fan PWM to 30%Matt DeVillier
Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot stumpy to payload, verify fan noise is negligible. Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81514 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13mb/google/beltino: Set initial fan PWM to 30%Matt DeVillier
Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot google/beltino to payload, verify fan noise is negligible. Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13superio/ite: Add function to disable PME# outputJoel Linn
A function to disable the PME# output was added. This is required to set up the SuperIO on the "HP Pro 3500 Series" mb. Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13superio/ite: Add function to disable 3VSBSW# signalJoel Linn
The 3VSBSW# signal can now also be disabled again which is necessary to power components down properly in SMM when entering S5. In such cases the signal will be enabled only in the SMM S3 handler. Change-Id: I8535176908ec39e9916774135e028cbc7c203474 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13superio/ite: Add special fan vectorsJoel Linn
A number of ITE SIOs support "special fan control vectors", which effectively allow non-linear fan speed control. This is for example used by the vendor firmware of the "HP Pro 3500 Series". The special vector registers won't be written to until the mb's devicetree configures `FAN_VECX.tmp_start != 0`. Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13superio/ite: Unify it8772f with common codeJoel Linn
The it8772f is now configured by the much better common code that is used for other chips in the family as well. This mainly concerns the EC, the GPIO functionality was not moved to common as it currently lacks a sane abstraction in any codebase. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-13lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARYLeah Rowe
Haswell ThinkPads have Nvidia Optimus wired in on some models. With recent coreboot changes, legacy VGA decode is now disabled on the iGPU, and the iGPU itself is disabled, when a dGPU is present. This is a problem on Optimus laptops, because it means that the Intel GPU would be effectively disabled, when it is the one that has to handle the framebuffer. On these boards, you can enable ONBOARD_VGA_IS_PRIMARY so that coreboot does not disable the iGPU. This is because on Optimus laptops, the Nvidia GPU is only used for offloaded rendering. Enable ONBOARD_VGA_IS_PRIMARY by default on these boards. Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31 Signed-off-by: Leah Rowe <info@minifree.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81645 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-13soc/intel/broadwell/pch/sata.c: Add missing SATA init stepsAngel Pons
WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macroAngel Pons
Integer division in C truncates toward zero. When the dividend and the divisor are positive, one can add half of the divisor to the dividend to round the division result towards the closest integer. We already have a macro in commonlib to do just that, so put it to good use. Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2 and the Asrock B85M Pro4 do not change. Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12nb/intel/sandybridge/raminit: Add tCPDED corner casePatrick Rudolph
tCPDED is always 1, except for steppings earlier than Sandy Bridge D0. Reduces the differences to MRC.bin. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-12nb/intel/sandybridge/raminit: Only write register on Ivy BridgePatrick Rudolph
Only write register WMM_READ_CONFIG on Ivy Bridge as it's reserved on Sandy Bridge. Tested on Lenovo X220: Still boots and runs fine. Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79761 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-12nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNBPatrick Rudolph
MRC.bin doesn't write BANDTIMERS_SNB register, so drop the write. The bits written were targeting a reserved range, so assume it didn't do anything useful. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I920aabd60831c791188af976914553787cc0ff18 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-12mb/google/brox: Initialize NOTE_BOOK_MODE GPIOShelley Chen
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took the liberty of alphabetizing all the ISH GPIOs to they're easier to search through. BUG=b:316421831 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Make sure that brox device still boots up with this change. Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12mb/dell/optiplex_9020: Fix SATA port mapsMate Kukri
Previously incorrect sets of SATA ports were enabled. There are no publically available schematics, but I am almost certain the new values are correct. The original 0x33 value was carlessly copy pasted, and only enables ports 0, 1, 4, 5, leaving 2, 3 disabled. On the SFF, with 0x33 only the first 2 ports worked. I have verified by plugging in devices under the stock firmware that 0, 1, 2 are the ones that should be enabled, so setting the value to 0x7 per datasheet. This was also tested in practice to work. I don't have an MT, but I was told the two white ports didn't work with 0x33, so those are most certainly ports 3, 4, hence me setting the value to 0xf. If the MT's working ports are port 0, 1 on the PCH this is correct. Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop duplicated <stdarg.h> and <stdio.h>Elyes Haouas
<string.h> is supposed to provide <stdarg.h> and <stdio.h> Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/pci_{def,type}.h>Elyes Haouas
<device/pci.h> is supposed to provide <device/pci_{def,type}.h> Change-Id: Ia645b8dba8c688187a25916f508593f333821f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop unused <cbmem.h>Elyes Haouas
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12include/device/device.h: Drop duplicated <console/console.h>Elyes Haouas
Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12Makefile.mk: Account for large code model sections in cbfs_structArthur Heymans
Starting with version 18 LLVM puts code and data generated with -ffunction-section -mcmodel=large inside sections with an 'l' prefix. This would now also pick up const data in .rodata. Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-12mb/google/brya/var/sundance: Add GPIO tableLeo Chou
Fill GPIO table for Sundance. BUG=b:327520553 TEST=emerge-nissa coreboot Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81613 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-04-11tree: Drop unused <timestamp.h>Elyes Haouas
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <timer.h>Elyes Haouas
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Drop unused <halt.h>Elyes Haouas
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-11tree: Drop unused <stdlib.h>Elyes Haouas
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSPBenjamin Doron
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and `PchPcieClockGating` UPDs, so, remove the preprocessor check that only enabled it for AlderLake FSPs. Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11drivers/acpi/thermal_zone: Correct Kelvin constant used for conversionNicholas Sudsgaard
As 0C is 273.15K you could argue that 2731 and 2732 are both correct. However, 2732 is deemed as correct both throughout the codebase and in the ACPI specification[1]. [1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/11_Thermal_Management/thermal-control.html#temperature-change-notifications Change-Id: I845bc750681c7ae6f2d1342b32983b990ce6d296 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81197 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-04-11soc/intel/**/fast_spi.c: Reorganize some statementsAngel Pons
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the result won't be used. Also, reorder a condition so that compile-time constants appear first, so as to help the compiler optimize it out. Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-11mb/google/nissa/var/craaskov: Disable external fivrIan Feng
In next phase, craaskov will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:330253778 TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81607 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11mb/google/karis: Add FW_CONFIG and device for VPUJamie Ryu
BUG=b:333605309 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared. Change-Id: I6e2230715d783ea7108d71699fd19684ce19e2ff Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-11mb/google/brya: Create trulo variantDinesh Gehlot
This patch adds a new variant trulo for the baseboard trulo. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: I91157d252ef56c8938bfc08ed0f734c5dc7e614d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81627 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-04-11mb/google/brya: Add new baseboard truloDinesh Gehlot
This patch adds a new baseboard trulo. This commit is a stub which only adds the minimum code needed for a successful build. BUG=b:333314089 TEST=abuild -a -x -p none -t google/brya Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0Shuo Liu
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. TEST=Build and boot on intel/archercity CRB Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acmsSergii Dmytruk
This is a good board for compiling TPM PPI sources for the following reasons (based on `config TPM_PPI` definition): - uses TPM - the board is not related to ChromeOS - ACPI tables are enabled - it doesn't use EDK2 payload At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all, see CB:69161 and CB:81590. `CONFIG_TPM_PPI` is off by default but at least several configurations under `configs/` (Protectli, MSI) should exercise the file because they use EDK2 payload which changes default value. This is however negated by abuild disabling all payloads and thus effectively preventing `CONFIG_TPM_PPI` from being set. This board not using EDK2 also ensures that `CONFIG_TPM_PPI=y` will not disappear after some future `make savedefconfig`. Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81800 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10lib/thread.c: Move 'asmlinkage' before type 'void'Elyes Haouas
Change-Id: Ibd35bef4182ea075ef5fa153e2e47678ffce171b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10tree: Drop unused <stdio.h>Elyes Haouas
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10mb/google/corsola/var/wugtrio: Correct the display orientationYang Wu
Set orientation of KD_KD101NE3_40TI to LB_FB_ORIENTATION_RIGHT_UP to align the volume up/down direction with menu up/down in FW screen. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage, and check FW screen on wugtrio, test volume key behaves as expected. BRANCH=corsola Change-Id: Ie101cc8b983d3d16587f88fa787ed622e59d27eb Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81752 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10mb/google/brya: Remove baseboard-specific FMD namesDinesh Gehlot
This patch renames the 16MB FMD file to remove the baseboard-specific name 'Nissa'. This allows other supported baseboards to utilize the 16MB SPI flash. Additionally, the patch attempts to create a generic, unified 32MB FMD file for both brya and nissa variants. BUG=b:333314089 TEST=Build and boot Nivviks. Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <post.h>Elyes Haouas
Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-09soc/intel/alderlake: Fix non-local header treated as localElyes Haouas
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09mb/google/*: Drop unused header file console/console.hRuihai Zhou
The header file console/console.h is unused, just drop it. TEST=abuild -t google/corsola -b wugtrio -a TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/81685 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-04-09soc/intel/xeon_sp: Add iio_ioapic.cShuo Liu
Move the soc_get_ioapic_info for platforms with IIO IO-APICs to a separate file from src/soc/intel/xeon_sp/acpi.c. TEST=Build intel/archerticy CRB Change-Id: I59022b7685539491604724ef3b550da1cfd53f13 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-09soc/samsung: Move 'inline' between storage class and typeElyes Haouas
Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09drivers/gfx: Remove unnecessary line continuationsElyes Haouas
Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81594 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09soc/mediatek/common/include/soc: Include header file for check_memberRuihai Zhou
To fix the build error below when include i2c_common.h, we should include the necessary header for check_member. """ src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant 24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); | ^~~~~ | ) """ TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I266571686e452e2b7514afee42ff0a48f8891831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09drivers/mipi: Fine tune clock for BOE_NV110WUM_L60Ruihai Zhou
Fine tune the panel clock to prevent mipi noise from affecting wifi band. After tuning, the panel refresh rate keeps at 60Hz and wifi test passed. Just keep consistent with the Linux kernel panel driver panel-boe-tv101wum-nl6 [1] configuration. [1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5029075/59 BUG=b:330807136 TEST=fw screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-08mb/google/brox: Update verb table to fix headset detectionPoornima Tom
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the updated verbtable received from Realtek. Updated Version : 5.0.3.1. This fixes the headset detection failure, when power_save is enabled in legacy hda driver. BUG=b:330433089 BRANCH=None TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Terry Cheong <htcheong@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-08mb/google/brya: Sort Kconfig option alphabeticallyVarshit Pandya
Change-Id: I878c14058e1edc0f64e37c2fc16b8dcf75b90192 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81631 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-04-08lib/program.ld: Account for large code model sectionsArthur Heymans
Starting with version 18 LLVM puts code and data generated with -ffunction-section -mcmodel=large inside sections with an 'l' prefix. Change-Id: Ib755673dfa9e71172bbef0a5aec075154c89a97b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81675 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.binPatrick Rudolph
A register dump between native and MRC.bin raminit showed a difference in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses. Tested on Lenovo X220: Still boots and works fine. Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79759 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07soc/amd/genoa_poc: Allow using UART with DEBUG_SMI=yBenjamin Doron
When DEBUG_SMI is selected, common code may use these helpers to handle addressing and initialising the SoC-specific UART. Therefore, add uart.c to be compiled into SMM. Change-Id: If7c6f2346d5f9ffb371d51d1de6f0b695acedf10 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81072 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-07MAINTAINERS: take Genoa/Onyx rename into accountFelix Held
When soc/amd/genoa was renamed to soc/amd/genoa_poc and mb/amd/onyx was renamed to mb/amd/onyx_poc, the MAINTAINERS file wasn't updated, so no reviewers were added automatically to patches on Gerrit that change things in soc/amd/genoa_poc or mb/amd/onyx_poc. Fix this by updating the folder names in the MAINTAINERS file too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib52781ebc98bd2ce9df495526cfaf9d884aace50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81679 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 20:56:16 +0000