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2013-11-25slippy: Add on-board devices and configure GPIO irq/wakeDuncan Laurie
Add the onboard I2C devices for Slippy trackpad/lightsensor and generate SMBIOS Type41 tables for them. Add ACPI device for the trackpad to expose the interrupt map to the OS so it can be used. Configure interrupt GPIOs as PIRQ type and wake GPIOs as just standard input type. The wake GPIO is reconfigured as ACPI SCI in the specific device _DSW method. This prevents the wake GPIO from generating a flood of SCI at runtime. LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these are not repurposed interrupt pins so they are not generated at runtime. SIM_DET and ALS_INT_L are set as input since we don't have an interrupt handler for them. tested on slippy with trackpad with additional kernel changes to chromeos_laptop.c to initialize devices. 1) Ensure trackpad interrupt is functional and that there is not a flood of ACPI SCI when trackpad does interrupt: 9: 1 0 0 0 IO-APIC-fasteoi acpi 37: 421 0 0 0 IO-APIC-fasteoi cyapa 2) Ensure that devices are exposed as wake capable: Device S-state Status Sysfs node TPAD S3 *enabled pnp:00:00 TSCR S3 *disabled pnp:00:01 3) Ensure that trackpad can wake from S3 by default, but that it does not cause an immediate wake when entering suspend. 4) Ensure that trackpad can be disabled as a wake source with echo TPAD > /proc/acpi/wakeup Change-Id: Id562d20b54eeefec56040b8f70ef238911312628 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56622 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4190 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25lynxpoint: Add ACPI Method to enable GPIO as wake sourceDuncan Laurie
This is an LPT-LP specific method that will enable a specific GPIO as an ACPI SCI wake source. It can be used by a device _DSW method to enable a pin that is otherwise not configured to generate SCI at runtime. It will set: - GPIO owner to ACPI - GPIO route to SCI - GPIO config to GPIO, Input, Inverted Also clean up and remove ACPI field definitions that are unused and/or incorrect. Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4189 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25falco: Add Elpida DIMM SPDDuncan Laurie
This was provided by the vendor but I added the part number at byte 128-143 so it can be identified when extracted by mosys. Change-Id: Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 Reviewed-on: https://gerrit.chromium.org/gerrit/56634 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4192 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25RTC: Skip rtc_init() in S3 resume pathStefan Reinauer
In addition to not clearing the pending interrupts, we also don't want to reset the RTC control register when booting with an S3 resume. On most new systems, when the RTC well is losing power, we will also lose state that is required to perform a resume, so we end up in a normal boot anyways. Hence don't do any RTC initialization in the S3 resume path. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80 Reviewed-on: https://gerrit.chromium.org/gerrit/56826 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4206 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25x86: fix compile error for !CONFIG_MULTIBOOTAaron Durbin
Some code was previously removed regarding elf notes. However, that code left a dangling comma under !CONFIG_MULTIBOOT configs for inline assembly constraints. Instead, place the comma within the #ifdef stanza. Change-Id: I805453ef57d34fbfb904b4d145d8874921d8d660 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56844 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David James <davidjames@chromium.org> Reviewed-on: http://review.coreboot.org/4207 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25baskingridge: drop incorrect USB handling codeStefan Reinauer
These GPIO accesses were copied by accident and don't make sense for the baskingridge board. Change-Id: I03bfc2cf97b6056a746a6c1a27308823ecaa9637 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4204 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQDuncan Laurie
LynxPoint-LP has an additional 16 entries in the IOAPIC that can be assigned to specific GPIOs when they are configured as PIRQ. The maximum redirection entries field in the IOAPIC needs to be set to 0x27 when this is enabled. Additionally specific GPIOs need to be routed to PIRQ so they interrupt via the IOAPIC instead of the GPIO IRQ 14/15. Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56620 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4203 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25wtm2: add ssdt2 tableAaron Durbin
The LynxPoint southbridge ACPI code needs the SSDT2 table to function properly. Otherwise the ACPI evaluator in the kernel spews errors. Change-Id: I73918545a07e43f4a281ff34d8537340d601b102 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56601 Reviewed-on: http://review.coreboot.org/4188 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25smbios: Add generic type41 write functionDuncan Laurie
Mainboards were defining their own SMBIOS type41 write function. Instead pull this into the generic SMBIOS code and change the existing mainboards to make use of it. Change-Id: I3c8a95ca51fe2a3118dc8d1154011ccfed5fbcbc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56619 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25elog: Check for successful flash erase in elog_shrinkDuncan Laurie
A parrot device with a bad flash part has been seen to hang in the elog_shrink code becuase the flash was not successfully erased and it gets stuck in a loop trying to shrink the log and then add an event. Change-Id: I8bb13dbadd293f9d892f322e213c9255c8e9acb3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56405 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4186 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25haswell: update pei_data data structureAaron Durbin
Update and use the new pei_data data structure. Now that the reference code is fixed it's possible to properly disable/enable the USB2 and USB3 ports correctly. Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25falco: Initial mainboard commitDuncan Laurie
- Only the first two DIMM SPDs are specified so far - GPIO map is updated - iSSD power sequencing removed - USB port map updated Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: fix mem corruption during ssdt2 genAaron Durbin
The ssdt2 generation code was calling acpigen_patch_len(). However, none of the entries had AML object lengths that needed patching. That resulted in the following message: ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c',  line 52 Additionally, this caused an errant write to a memory address whose value was in the variable ltop. This was the 0 address. Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56299 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Fix XHCI controller device in ACPIDuncan Laurie
The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4181 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Enable SerialIO clock in PCI modeDuncan Laurie
The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25libpayload: Fix xcompileStefan Reinauer
The architecture name for our ARM port is armv7, not arm. Hence, none of those flags were ever actually used. Fix the architecture name and remove the flags, they should not be set in xcompile, but in the Makefile, like in coreboot. Change-Id: Id9c5db7ebceafddb58a1ce1988417f09c074ba6c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4179 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Enable EC SMIDuncan Laurie
Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC. 1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4177 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25libpayload: Add USB support for non-PCI controllersStefan Reinauer
Restructure USB stack to not depend on PCI, and make PCI stub available on x86, but provide fixed BARs for ARM (Exynos 5) Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49970 Reviewed-on: http://review.coreboot.org/4175 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25libpayload (EHCI): correctly align PORTSCStefan Reinauer
Two structures in the USB EHCI stack were pointing to hardware but not marked attribute((packed)) hence leaving it to GCC to correctly align the data structures. Next, the number of reserved bytes in hc_op_t was wrong (but implicitly aligned to the correct values on x86) It seems this worked fine on x86, but on ARM it was doing the wrong thing. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d Reviewed-on: https://gerrit.chromium.org/gerrit/55555 Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4174 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: update azalia device idsAaron Durbin
The vendor ids were never updated to reflect LynxPoint's device ids. Therefore, none of the initialization was being ran. Fix this. Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55821 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4173 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Change SerialIO device enable reporting to ACPIDuncan Laurie
In order to report whether coreboot enabled a SerialIO device in ACPI mode we had been relying on reading NVS in the _STA method for the SerialIO device. The ACPI _STA method has restrictions on what it can access and is unable to access OperationRegions outside its scope which means it should not be trying to read NVS. This change adds a new SSDT to the ACPI tables and fills it with constants that indicate whether or not a device is enabled in ACPI mode. The ACPI code is changed to read these variables from the SSDT and use that instead of trying to query a variable in NVS. Attempt to use lpt-clk driver to probe the device clocks for SerialIO devices and see that the kernel does not complain about accessing the GNVS region. Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Fix int15 return value for mainboard oprom handlersDuncan Laurie
These boards were returning 0 to indicate success when the realmode handler expects it to return 1 to indicate that it handled the interrupt. Change-Id: I2baeaf8c2774fa7668a8b2f2d9ad698302eefb21 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50881 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4168 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25wtm2: Set SerialIO I2C ports to 3.3VDuncan Laurie
These are both pulled up to 3.3V in the schematic. Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4164 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25cbfstool: check potential microcode update earlierAaron Durbin
The update-fit command takes in a parameter for number of slots in the FIT table. It then processes the microcobe blob in cbfs adding those entries to the FIT table. However, the tracking of the number of mircocode updates was incremented before validating the update. Therefore, move the sanity checking before an increment of the number of updates. Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50319 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4161 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25x86: call cbfstool update-fit when fit selectedAaron Durbin
In order for the FIT entries to be populated in the table the update-fit command needs to be done on the coreboot image. That way the microcode entries are added to the table properly. Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50317 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4159 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Expose ACPI Device for LP GPIO controllerDuncan Laurie
In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 Reviewed-on: http://review.coreboot.org/4158 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Make ssize_t an actual ssize_tStefan Reinauer
In the process of getting rid of compiler includes during in coreboot and libpayload, we defined size_t and ssize_t ourselves, using a GCC macro for size_t: __SIZE_TYPE__. Unfortunately, there is no __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make __SIZE_TYPE__ __SSIZE_TYPE__. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b Reviewed-on: https://gerrit.chromium.org/gerrit/49947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4156 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25call fill_lb_framebuffer() earlierDavid Hendricks
fill_lb_framebuffer() now sets the framebuffer pointer according to the EDID information, so it must be called before setting the tag and size. (credit to rminnich for this, I'm just uploading it) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I5ac783fa3a776eee504d39889284041d1dc2c92a Reviewed-on: https://gerrit.chromium.org/gerrit/50012 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4155 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Move ME lock down to ramstageDuncan Laurie
Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 Reviewed-on: http://review.coreboot.org/4153 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Add missing ME MBP entriesDuncan Laurie
There were two undefined MBP types that are now defined. These include NFC status and some interesting timing data. ME: Wake Event to ME Reset: 6 ms ME: ME Reset to Platform Reset: 7 ms ME: Platform Reset to CPU Reset: 51 ms Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49756 Reviewed-on: http://review.coreboot.org/4152 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: export mem console pointer in ACPIAaron Durbin
Instead of having an OS re-parse cbmem book-keeping records for the cbmem allocator just to get the console buffer export the pointer to the memory console directly in a field named 'CBMC'. This field lives in the GNVS table. Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49764 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4149 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25elog: Make sure the elog data structures are initialized in elog_clear.Gabe Black
If elog_clear is called before other elog functions, for instance if it's called through an SMI immediately after the system boots, then the elog data structures won't have been set up and the system will go off the deep end. This change adds a call to elog_init to elog_clear to make sure things things are always initialized before we start using them. Before this change, this command would cause the system to lock up if run immediately after boot: echo 1 > /sys/firmware/gsmi/clear_eventlog After this change, that results in the log being cleared correctly. Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Updates to power management and clock gatingDuncan Laurie
Slight tweaks found when looking at latest ref code when investigating package C-state issues. A few bits in the clock gating register don't match the documentation and are also cleaned up. Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49330 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4142 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25x86: use proper types for interrupt callbacksAaron Durbin
The mainboard_interrupt_handlers() argument for the function pointer was using void * as the type. This does not allow the compiler to catch type differences for the arguments. Thus, some code has been committed which violates the new interrupt callbacks not taking any arguments. Make sure the compiler provides a type checking benefit. Change-Id: Ie20699a368e70c33a9a9912e0fcd63f1e6bb4f18 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48970 Reviewed-on: http://review.coreboot.org/4141 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Unify and clean up remaining INT15 handlersStefan Reinauer
Some handlers still had 2 variants, others were incorrectly guarded by CONFIG_ variables. This patch straightens them out. This does not touch the siemens/sitemp_g1p1 which provides an interestingly complex solution for the int15 handler. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5d74fdf7c2ab1faa96ebc2b5ca5c69398449b069 Reviewed-on: https://gerrit.chromium.org/gerrit/48979 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4140 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25ARM: Update the size/location of the coreboot tables so we can boot againGabe Black
Change-Id: I3235f42c7faaf28a63455162ea55dc1a6bebd1f5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-by: Hung-Te Lin <hungte@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48290 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25butterfly: Log EC shutdown reason in ELOGDuncan Laurie
The EC saves its last "shutdown reason" for the system in EC RAM that we can read back and log on boot. The decode for the "reason" field will be added to mosys. Change-Id: I834d39122e45262ef8e7ba59201accbee5857aac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48323 Reviewed-by: David James <davidjames@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4127 Tested-by: build bot (Jenkins)
2013-11-25cbmem utility: compatibility with older coreboot versionsStefan Reinauer
Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot table entries from a pointer to a uint64_t. This change was introduced to make the cbmem utility work on both 32bit and 64bit userland. Unfortunately, this broke the cbmem utility running on older versions of coreboot because they were still providing a 32bit only field for the address while the cbmem utility would now take the following 4 bytes as upper 32bits of a pointer that can obviously not be mmapped. This change checks if the size of the lb_cbmem_ref structure provided by coreboot is smaller than expected, and if so, ignore the upper 32bit of the address read. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: If4c8e9b72b2a38c961c11d7071b728e61e5f1d18 Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Fix VGA option rom INT15 handlerStefan Reinauer
The format of this function changed but was not updated in all mainboards. This fixes all Sandybridge/Ivybridge boards. The int15 handler no longer takes a regs structure as an argument and instead uses global variables. The yabel interface is now similar enough that we can drop the duplicate handler. Change-Id: Icdaae4d6d50884f6d7bce7a167d48cb1d4807010 Reviewed-on: https://gerrit.chromium.org/gerrit/48969 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4135 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25armv7: import updated cache/MMU stuff from corebootDavid Hendricks
This imports the cache/MMU code from coreboot as of 1877cee. Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48288 Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4134 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25qemu: cirrus native video initVladimir Serbinenko
Recent commit proposal by Ron Minnich proposes to move to native gfx init for qemu. Unfortunately we didn't have native init for default qemu video (cirrus) Here is one extracted from GRUB one which I wrote couple of years ago. Change-Id: Icb89cf918ef5d276bcc703c48c568e7b9c1be756 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Support for nehalem northbridgeVladimir Serbinenko
Including raminit Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4044 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25Support for Ibexpeak southbridgeVladimir Serbinenko
Part of X201 port. Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4052 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-25bochs: add support for native graphicsRonald G. Minnich
Per our discussions with Gerd, qemu will now always do native graphics on coreboot. The VGA BIOS capability is not needed and will no longer be supported. Attempts to build without native graphics will result in an error. This code builds for both x86 emulation targets. I'm hitting an issue testing that is unrelated to coreboot; if someone can test, that would be helpful. Be sure to start qemu with -vga std. We also add a test for the PCI BAR being zero and return silently if it is. Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4258 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2013-11-25Add declaration of dock registers 1, 2 and 3.Vladimir Serbinenko
Needed to make dock work on X201. Change-Id: Id0b32266cacf04bb48530bedf50818c268f947ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4081 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-11-25google/butterfly: Declare mrc_scrambler_seed_chk in cmos.layoutAlexandru Gagniuc
SandyBridge raminit uses this CMOS option. If it is not declared, the build fails when USE_OPTION_TABLE is selected. Change-Id: I1ba1f994d4ea3824dc66e8f35d0b5b24b88d4dd6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4269 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25.gitignore: Properly ignore KDevelop filesmrnuke
Change-Id: I1410242e4d1995baedd5d3a001f86619e729db98 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4268 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-24no-car/cbmemc: Fix compilationVladimir Serbinenko
the part !CAR && PRE_RAM is obviously meant as dummies. Unfortunately cbmemc_tx_byte has wrong number of arguments and hence causes compilation failure. Found out when compiling for vexpress-a9. Change-Id: Ic84d142bac5c455c2371fbc9439c898de04a974e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4267 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-24haswell: Update GT PM register valueDuncan Laurie
This was changed to 0x80000000 in SA BWG 1.5.0. Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50852 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4166 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: Update ULT microcode to 0x10Duncan Laurie
[ 1.503741] microcode: CPU0 sig=0x40651, pf=0x40, revision=0x10 [ 1.510483] microcode: CPU1 sig=0x40651, pf=0x40, revision=0x10 [ 1.517213] microcode: CPU2 sig=0x40651, pf=0x40, revision=0x10 [ 1.523947] microcode: CPU3 sig=0x40651, pf=0x40, revision=0x10 Change-Id: I19ef40b636eebeb8cc29cc0404abbe263ec8eaa7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4165 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: Remove limit on package C-stateDuncan Laurie
With the XHCI controller enabled we no longer hang the system when dropping into a package C-state so remove the code that was disabling it. Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50355 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4163 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: Update ChromeOS ACPI GPIO packageDuncan Laurie
The chromeos_acpi driver sysfs naming is not what crossystem expects if there is just one entry in the package because it does not add a ".#" suffix in that case. Specify all the expected GPIOs on wtm2 as undefined, which should be 0xFF and not 0x00 becuase 0 is a valid GPIO. Change-Id: I9b17e9bab94219695e65b17914c84acf02a0983b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4162 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: split microcode between ULT and non-ULTAaron Durbin
The current microcode blobs contain both ULT and non-ULT revisions. Only include one or the other based off of the CONFIG_INTEL_LYNXPOINT_LP Kconfig option. Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50318 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4160 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: enable monotonic timerAaron Durbin
For all the current haswell boards enable the monotonic timer. The ULT boards use the 24MHz MSR while the non-ULT boards use the local apic. Change-Id: I8b19f526a5a49e8467f296c566a2c4263bc5a863 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49763 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4148 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: Update ULT microcode to rev 'a'Duncan Laurie
Change-Id: I714208da23bf7cbd1232874c05ad3100551f5f7c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4146 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: Configure PCH power sharing for ULTDuncan Laurie
This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: calibrate 24MHz clock against BCLKAaron Durbin
On haswell ULT systems there is a 24MHz clock that continuously runs when deep package c-states are entered. The 100MHz BCLK is shut down in the lower c-states. When the package wakes back up a conversion formula needs to be applied. The 24MHz calibration is done using the internal PCODE unit. Change-Id: I6be7702fb1de1429273724536f5af9125b98da64 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48292 Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4136 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24haswell: configure c-statesAaron Durbin
The c-states are configured according to the BWG, however the package c-states are disabled as they currently cause platform instability. The exposed ACPI c-state to processor c-state mapping are as follows for ULT boards: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C7S long latency) ACPI(C3) = MWAIT(C10) The non-ULT boards have an expoed c-state mapping: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Included in this patch is removing the updating of current limit registers as some of the MSRs are different and the proper values are currently unknown. Lastly, some of the MSRs were renamed to match the BWG. Booted 3.8 kernel and used powertop to note package, core, and acpi c-state residency. Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48291 Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4133 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Add a function to set an individual GPIODuncan Laurie
This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Rework LP GPIO handlingDuncan Laurie
This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this. Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare. Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4138 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Add panel power sequence timingsDuncan Laurie
These are placeholder values until we can configure for the exact panel. Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56807 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4196 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Clean up for easier portingDuncan Laurie
Minor tweaks to variable names in the slippy mainboard that make it easier to base a new board from without as much renaming. Also properly set up the thermal variables for the thermal zone that is defined in ACPI instead of using the generic setup from WTM2. Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56328 Reviewed-on: http://review.coreboot.org/4183 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Run EC init as part of mainboard init stepDuncan Laurie
This will log and clear EC events so they do not take effect when the SMI handler is enabled. Change-Id: I5ef563f7cedc8977410cc3f69e2655fc4e14c9eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4178 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Update interrupt routingDuncan Laurie
The SerialIO devices have specific requirements for PCI interrupt mode to use PIRQ{E,F,G,H} that are not being met. D21:F0 uses PIRQE, which must not be shared with other PCH D21:F1-F6 share PIRQF, which must not be shared with other PCH D23:F0 uses PIRQH, which must not be shared with other PCH - Fix D20IR -> D20IP typo - Remove D25/EHCI2 as it does not exist - Reorder other interrupts to clear PIRQE/PIRQF/PIRQH Check device interrupts in the kernel 0: IO-APIC-edge timer 1: IO-APIC-edge i8042 8: IO-APIC-edge rtc0 9: IO-APIC-fasteoi acpi 16: IO-APIC-fasteoi ath9k 18: IO-APIC-fasteoi i801_smbus 19: IO-APIC-fasteoi ehci_hcd:usb1 21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1 40: PCI-MSI-edge PCIe PME 41: PCI-MSI-edge i915 42: PCI-MSI-edge ahci 43: PCI-MSI-edge xhci_hcd 44: PCI-MSI-edge snd_hda_intel Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: set PWM valuesAaron Durbin
The dev screen was not displaying properly. With the PWM values programmed the screen displays correctly. Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51472 Reviewed-on: http://review.coreboot.org/4172 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Put SerialIO devices in PCI modeDuncan Laurie
The device at function 0 also needs to be enabled or the kernel will ignore all other functions. 00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03) 00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03) 00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03) Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4171 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Add EC to the device treeDuncan Laurie
This lets the keyboard init get called properly. Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4167 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Update SPDDuncan Laurie
Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50082 Reviewed-on: http://review.coreboot.org/4157 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Add SPD data for on-board memoryDuncan Laurie
Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4154 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Prepare LPC IO decode ranges for ECDuncan Laurie
- 0x200-0x208 for host command window - 0x800-0x8ff for host command arguments and parameters - 0x900-0x9ff for exported EC memory map Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49755 Reviewed-on: http://review.coreboot.org/4151 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Add iSSD power sequencingDuncan Laurie
Without an LM10506-A the power sequencing for this part needs to be done manually using GPIOs. Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49648 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4150 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24slippy: Initial mainboard commitDuncan Laurie
Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49531 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4147 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24amd/olivehill: Fix the double spaces in copyright headerZheng Bao
Change-Id: I1bdc52efc827c331c53b97d2b96edafc518d05bf Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4259 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-11-24Honor vboot's request to load the VGA option ROMBill Richardson
This removes an earlier patch that caused the VGA option ROM to be loaded by coreboot even in normal mode when it isn't needed. Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48173 Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4125 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24libpayload: fix wrong endian assumption in sha1.cStefan Reinauer
Not all platforms !x86 are big endian, hence actually look at the CONFIG_LITTLE_ENDIAN flag instead of CONFIG_ARCH_X86. Change-Id: Ibbd8f48b377a1121dd1e045834a94a2d67eda2ab Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/56066 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4236 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Northbridge: i945: Native VGA init: print the GMA and GTT addressesPeter Stuge
The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Northbridge: i945: Native VGA init: use UMA addressPeter Stuge
The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Lenovo X60: Native VGA init: Get rid of the memory corruptions.Peter Stuge
Without that fix the GTT points at 0x00000000. The patch was made by Peter Stuge, I just split it and added a commit message. Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/4002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24lenovo/x60: native vga init: fix code style issues.Denis 'GNUtoo' Carikli
Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3999 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24dmp/vortex86ex: Move DMP specific POST code defines into one fileAndrew Wu
Move into src/cpu/dmp/dmp_post_code.h Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24lenovo/x60: export reboot_bits nvram configuration.Denis 'GNUtoo' Carikli
This permits any software running after the ramstage to tell coreboot that the boot was successfull. Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3992 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24payloads/external/SeaBIOS/Makefile.inc: Remove empty lines at file beginningPaul Menzel
Change-Id: I3e6eba62b6790836edf9813c2a45c77390d8c078 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4094 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24haswell: Put each logical processor in its own P-state domainDuncan Laurie
The recommendation from Intel is to report each core as a separate logical domain in the _PSD table. This goes against the recommendation in the ACPI specification because all of these cores are on the same package and share a VR so they will do voltage transitions together. The reasoning is that with a larger number of logical processors the P-state often ramps too quickly resulting in higher power consumption. By exposing each core as a separate domain the OS can manage them individually allowing the socket to select the optimum frequency. $ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT $ iasl -d /tmp/SSDT Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000001, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000002, 0x000000FE, 0x00000001 } }) } Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) { Name (_PSD, Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00000003, 0x000000FE, 0x00000001 } }) } Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24haswell: Update microcode for ULT/40651 to rev 8Duncan Laurie
$ cat /sys/devices/system/cpu/cpu*/microcode/version 0x8 0x8 0x8 0x8 Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4129 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Fix compile error in chromeos by adding stddef.hDuncan Laurie
Compile was failing with the following error: In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0, from src/vendorcode/google/chromeos/chromeos.c:22: vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t' src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload': src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function) Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48289 Reviewed-on: http://review.coreboot.org/4131 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Lenovo hotkeys supportVladimir Serbinenko
Implement proprietary lenovo ACPI hotkeys Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4055 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23Change EC GPE on X201Vladimir Serbinenko
X201 has GPE at 0x11 (17) instead of 28. Tested on X201. Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4053 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23lib/coreboot_table: set type and size of framebuffer tag after ↵Vladimir Serbinenko
fill_lb_framebuffer When testing Ron's patch on qemu I found out that fill_lb_framebuffer overwrites size and tag fields. We need either to fix/check all fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer. I prefer later as it's more robust. Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4263 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.Vladimir Serbinenko
2065x is with nehalem and not sandybridge. I don't care much eitherway but it clears some confusion. Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4046 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-23Call X201 dock hooks in EC codeVladimir Serbinenko
Unlike on X60/T60 dock has to be inited at the same time as EC. Change-Id: If6eb3140c871859ce99027a50908f72bcc560243 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4082 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-23Remove MRC variables from 2065x CAR init.Vladimir Serbinenko
2065x boards don't use MRC. And the space in question isn't used either. Read number of variable range MTRRs from MSR rather than hardcoding it. 2ff is still zeroed out as unless you zero-out undocumented bits as well boot fails. Tested on Lenovo X201. Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4080 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-11-22Don't wait on 2065xVladimir Serbinenko
The mdelay is not necessarry on 2065x. Tested on X201 that it works without delay. Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4083 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-11-22AMD f15tn, f16kb: Remove CDIT table and DMI tableWANG Siyuan
On AMD Trinity and Kabini boards errors similar to the following are shown. ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431 DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 The reason is that on f16kb boards, the CDIT and DMI table are not created. On f15tn boards, only the DMI table is not created. Until the root cause is found, disable the table generation to remove the errors. Thanks to Wei Hu for debugging and reporting this issue on the list [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html CDIT table is not created Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4092 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-21Fix error message on wrong compiles of 2065xVladimir Serbinenko
Current error message refers to sandybridge chipset. Instead error should be that 2065x needs Ibex Peak. Change-Id: I8cc8a34f496aec7af0ce95b4b65fd25e165f43fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4202 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19Asus F2A85-M: Fix S3 memory power cut-offRudolf Marek
The power to memory is lost during the the suspend, activate the 3VSBSW# which switches the power during S3 suspend sequence. As a result resuming from suspend to RAM works now, but now the GPP ports of the Hudson southbridge are gone after resume from S3. The devices 15.0 and 15.1 are disabled (decode as ffff) and therefore anything behind them too [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html fam15tn hudson PCIe GPP ports off after resume Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/4041 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-19Add GRUB2 payload to build systemVladimir Serbinenko
Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and FILO. So make it easy for coreboot users to use GRUB 2 as a payload by integrating it into coreboot’s build system, so it can be selected in Kconfig. As the last GRUB 2 release 2.00 is too old and has several bugs when used as a coreboot payload only allow to build GRUB 2 master until a new GRUB release is done. The downside is, that accidental breakage in GRUB’s upstream does not affect coreboot users. Currently the GRUB 2 payload is built with the default modules which results in an uncompressed size of around 730 kB. Compressed it has a size of 340 kB, so it should be useable with 512 kB flash ROMs. Tested with QEMU. Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4058 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19nvramtool: write size field more obviouslyPatrick Georgi
The field wasn't initialized in RAM first and later overwritten in a somewhat twisted way (that relied on the size field coming after the tag field in the struct). Change-Id: Ibe931b297df51e3c46ae163e059338781f5a27e2 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4087 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-11-18cbfs: 64-bit cleanupsRonald G. Minnich
cbfs used u32 in a number of cases where uintptr_t was correct. This change builds for both 64-bit and 32-bit boards. Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/4037 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 14:25:16 +0000