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Move SB700 calls to match comments and changes already made for
family14 et al.
Change-Id: I20a84e487ba346f63dd4454447077e0d2fd12c89
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6222
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Implement logging just once to have uniform output.
Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6180
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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AGESA correctly uses the enum AGESA_STATUS type whereas boards use a
mess of UINT32 typecasts.
Also no need to shout VOID. We are not that careful on changing
all cases of VOID->void or whitespace issues as these files will
get merged with follow-ups.
Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6182
Tested-by: build bot (Jenkins)
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Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.
Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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SPI controllers in Intel and AMD bridges have a slightly different
restriction on how long transactions they can handle.
Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6163
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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There are two separate restrictions to take into account:
Page Program command must not cross address boundaries defined by the
flash part's page size.
Total number of bytes for any command sent to flash part is restricted
by the SPI controller capabilities.
Consider
CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4.
This write would be split at offset 64 for no reason.
Consider
CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4.
This write would not be split at page boundary as required.
We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT
is a misnomer for the maximum payload length supported by the SPI controller
and is removed in a followup.
Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6162
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.
BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946
Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: http://review.coreboot.org/6003
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6007
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6006
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.
BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
coreboot's romstage and ramstage have different timestamps
in their banners.
Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Based on latest thermal report
BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther
Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6004
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther
Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6002
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Sometimes the SuperIO seems to provide wrong readings, especially early
on after a resume from suspend. This will cause the system to power off.
If that happens, wait for 1s and read again, to make sure the high
temperature value was not just a flaky read.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=Boot tested on Panther.
Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6001
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There is no speaker and no builtin microphone in this system,
hence disable them in the verb table.
BRANCH=panther
BUG=chrome-os-partner:24230
TEST=Boot Panther, see Microphone and Speaker disappear
in Audio Settings
Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182006
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6000
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5999
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/5998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Update fan policy according to Panther thermal report.
CPU Temp. Readings | PWM
-------------------+------
40C | 42%
50C | 42%
83C | 80%
90C | 90%
96C | 100%
BUG=chrome-os-partner:24532
BRANCH=panther
TEST=boot tested on Panther
Change-Id: I60f04d8b038c561b87dad505bbf058100119cc23
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181666
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/5997
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.
BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther
Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5996
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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(panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e)
BUG=none
BRANCH=none
TEST=boot tested on Panther
Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177474
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-on: http://review.coreboot.org/5995
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther
Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-on: http://review.coreboot.org/5994
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
BUG=none
BRANCH=none
TEST=boot test on panther
Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5993
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5992
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Fan is attached to port 2 instead of 3.
(panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174984
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5991
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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In C99 we defined a syntax for this. GCC’s old syntax is deprecated.
Modelled after commit 8089f178 (mainboard/lenovo/x230 Fix usage of GNU field
designator extension) [1].
[1] http://review.coreboot.org/5392
Change-Id: I51c72252800be64b9420d845e330fc0481c66470
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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(Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer)
BUG=chrome-os-partner:23563
TEST=emerge-panther chromeos-coreboot-panther
[pg: Drop configs/, which is chromeos stuff, adapted
libpayload's config.panther to work with upstream]
[pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options]
[pm: rebase to master branch of coreboot upstream]
[md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set]
Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174555
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5990
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The fan2 (chasis fan) was set to automatic mode, but the
registers for smart guardian have still default value which
will stop it. Run it in manual mode for now.
Change-Id: Ic2c2414ac88abba77a9e7a129788f9777e7e5ad5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/6217
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.
BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen
Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6017
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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I have been attempting to work around USB3 issues that appear in the
kernel with hacks in the firmware, but this is resulting in more
headaches in the kernel.
Instead remove all the work that was being done at resume time and undo
the change that was issuing a warm reset to all ports at suspend time.
The bad device behavior will be dealt with at the kernel level to
handle devices that get stuck in polling state after enable/disable
sequence.
BUG=chrome-os-partner:22754
BRANCH=falco,peppy,wolf,leon
TEST=manual:
suspend/resume with several misbehaving devices:
Kingston USB3 Media Reader
Transcend USB3 Media Reader
Various ADATA USB3 drives
Various Kingston USB3 sticks
Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170107
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7)
Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170578
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Worked out the purpose of more int15 calls and let them return
appropriate values. Also remove handlers for copy-pasted calls never
observed on this board.
Change-Id: I3d8c4ec5542bd19baca1dca83badc9b568779e1b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6249
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Fix some outputs of the super i/o that should be GPIOs and make
variables out of magic values that configure LVDS.
Change-Id: Ib9eef065980cefff0046485549a68cf8f070d5b9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6248
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The global pointer `biosmem` defined in vbe.c was never set. Thus, VBE
calls didn't work within YABEL.
Change-Id: I63c1c77755f9c442cfec227a495332595ce2b70c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6250
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Remove some ASCII art past 80 columns.
Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The objective here is to tighten coreboot up a bit by not repeating
common helpers. This makes the code base more consistent and
unified/tight.
Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller
Sequencing
The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may
be processor specific and may be sensitive to temperature.
Potential Effect on System:
System hang.
Suggested Workaround:
BIOS should set D18F2x408_dct[1:0] bit 31 = 1b.
See Publication # 48931 Revision: 3.08
Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/6216
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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In an abuild run, cbfstool is built in a shared directory
using "make tools". Unfortunately the build system doesn't
actually use that binary directly but creates a per-board
copy (for convenience purposes when editing the image later)
and uses that.
With this change the build system uses the original file but
still creates the copy for the user, avoiding the race while
ensuring convenience.
Change-Id: I38c603a7eca5ef859875ad3031bf7a850189645f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/6242
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Setting of `controller->reg_base` is of no use here, as it is never read
(in another function) later. Looks like this pattern originated from uhci.c
where it makes sense.
By removing the indirection through `reg_base` we also fix a possible
truncation to u32.
Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6251
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Fix a possible null-pointer dereference (hopefully) before anyone runs
into this. Also don't switch ports to xHCI if initialization failed.
Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6245
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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As the controller structure is never fully cleared, this one wasn't
initialized for non-pci controllers (but checked for non-null later).
Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6246
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Using void* for physical addresses leads to much casting and confuses
developers when to convert from physical to virtual addresses or
the other way around. When using plain integers for physical addresses
and pointers for virtual addresses things become much cleaner and we
won't ever end up dereferencing a physical address.
Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6244
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Like done in FILO, libpayload's console drivers might be initialized
before a relocation. So keep physical pointers in there which won't
break on relocation.
Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6247
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove a redundant phys_to_virt() that sneaked in the initialization of
PCI xHCI controllers. The use of casts from void* to u32 (and vice versa)
prompts for things going wrong here. That will be addressed in a later
commit.
Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6243
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add the following useful macros:
* Absolute Value Macro
* Taking ceiling of (a / b)
* Check if value x is a power of 2 or not
Change-Id: I4e9a326aea3cdd963f13548d1fb63331a57d84b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6198
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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If one commented out HAVE_ACPI_RESUME in Kconfig file for a board
using agesa/hudson the build failed.
Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6253
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
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Family15tn video bioses internal have a PCI ID of 1002/9901.
The vendor/device mapping in the family15tn/northbridge.c
file needs to map to 1002/9901 and not to 1002/9900.
This was tested on the amd/parmer mainboard.
Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6252
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx
tested/verified working on google/panther
Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6223
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ic63c456e775ad0863ea773abd957d9399e8e2a13
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6191
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I716253fe8532a4215e5770cd901ee3b3c4963d3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6187
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iace2ccfe95bd7f7e5dabbbc69ee4249d80d1cb84
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6190
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ieca3358a2a459016b7a38dce7f717100b55baba5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6186
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6189
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6185
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I3af50553191d7df9255be222eaf941b4232955d9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6188
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I485f79ece481210f31b0b6d3c62d7269131e29ab
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6184
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6201
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I05d6d22664155ac8478e665733f816776e277c22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6200
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib8d26d62566e42a78abc282dc9e351774b8e2faf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6212
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iea9e95981e5e87f2890841e7a0cf45ba93ce84eb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6211
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6210
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6209
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I1829c77f41cc809b590d00ef5522f368bd5fd814
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6208
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6207
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I472f3b70226ea5236ba6fc231f0f257f0f0eed9d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6206
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I69a4a2ffb41eeae04529e527d68edc652f3638a5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6205
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I50a5177a8bad5dada862f30c5c9421f08b0e1686
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6204
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6203
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I8633d331d095fe9506a8f01969060ba9889c8eac
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6202
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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ifdfake is the newest tool addition that leads to build time
races on highly parallel builds.
Change-Id: I86289e50079da851dcc8e1c05c2536d5c03de87c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6197
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ie3287cba45bd6f4f8823ce03cd9983707c9ad0de
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6194
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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We have the macro, let us be sure to make use of it.
Change-Id: I8dc5ca580c7485e3cce7ebc29189a452de52b1b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I90a120e64a5062493f64e3e8b48a75dae9342ec4
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/6178
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6049
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6048
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I246cfb38aa47e67d62bcfcc37539e9593b8026ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6179
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This code is not specific to any board or AGESA family.
Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5690
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.
BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None
Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6175
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.
BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None
Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6174
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The few remaining boards without CAR override this with
select ROMCC.
Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6172
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Although it builds without any further changes, including the header
src/northbridge/intel/i945/i945.h
where `BSM` is defined, would be useful. Unfortunately that conflicts
with the already included header `southbridge/intel/bd82x6x/pch.h`,
so it is left as is.
Change-Id: I7c0a795338c34038169e082446907987364a0e88
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5932
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This is needed to successfully build fox_wtm2 from external repo.
BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware
Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4132
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Some USB3 devices are not showing up after suspend/resume cycles.
In particular if a device uses a lower power state like U2 it may
take longer to come up and the firmware needs to wait after sending
a warm port reset.
In addition skipping port reset to connected ports in the way into
suspend was causing problems so instead send all ports a reset
before suspend.
BUG=chrome-os-partner:22402
BRANCH=falco,peppy,leon,wolf
TEST=manual:
Suspend/resume with ADATA HE720 HDD (and other devices) both
connected at suspend and connecting while in suspend and ensure
that the devices always show up in the kernel.
Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6015
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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At the end of some SPI operations the SPI device needs to be polled
to determine if it is done with the operation. For SPI data writes
the predicted time of that operation could be less than 10us.
The current per loop delay of 500us is adding too much delay.
This change replaces the delay(x) in the do-while loop with a
timer so that the actual timeout value won't be lengthened by the
delay of reading the SPI device.
Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5973
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The monotonic time now needs to be a first class citizen in Coreboot as
it is a hard dependency of the drivers/spi flash command polling
function.
Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I19c456e8bcd2de19c5f9d963ea17dad84d300ab8
Signed-off-by: Vladimir Berezniker <vmpn@vmpn.net>
Reviewed-on: http://review.coreboot.org/6170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.
BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours
Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6013
Tested-by: build bot (Jenkins)
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This was missing from lynxpoint.
BUG=chrome-os-partner:21796
BRANCH=falco,peppy
TEST=emerge-falco chromeos-coreboot-falco
Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66669
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6012
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.
BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco
Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6011
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Without a prompt the config option will always stay 0
due to the way Kconfig works.
BUG=chrome-os-partner:25387
BRANCH=panther
TEST=Boot into dev mode with Mohammed's TV screen, see
the dev mode screen appear.
Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185970
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6010
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.
BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
and see it go away.
Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6009
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Current build configuration always wants to include an Intel Management Engine
(ME) firmware (`me.bin`) on Intel Lynx Point systems. However, we can have a
working coreboot without it, as long as the factory delivered ME firmware is
kept untouched in the flash ROM. So let the user decide if a ME firmware will
be included in the build by introducing the Kconfig option `HAVE_ME_BIN`.
The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin
optional) [1] for Intel Sandy Bridge (BD82x6x).
[1] http://review.coreboot.org/3522
Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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On newer Intel systems, like Intel Lynx Point, the flash ROM is shared
between the host processor (BIOS), its Management Engine (ME) and an
integrated Ethernet controller (GbE). The layout of the flash ROM (and
other information) is kept in the so called Intel Firmware Descriptor
(IFD). If we only want to build coreboot to update the BIOS section,
all we need is the flash layout.
So add the option to specify the flash layout in the mainboard’s
Kconfig, and thus, to build without the real IFD. However, with such a
build, one has to make sure that the IFD section on the flash ROM will
not be written over (nor any other section that has not been included
by coreboot). A patch to write selected sections of a flash ROM with
IFD has been sent to the flashrom mailing list [2].
The same was done in commit a15cd66b [1] (sandybridge: Make build
possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x).
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
[PATCH] Add option to read ROM layout from IFD
[2] http://review.coreboot.org/3524
Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update acpi_slp_type early in ramstage.
Change-Id: I30ec2680d28b880171217e896f48606f8691b099
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6142
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Instead of calling get_bus_conf() three times from write_tables()
and executing it once, just make one call before entering write_tables().
Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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NOTE: The procedure is moved across a collected timestamp
TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
for in an earlier entry in cbmem -t output.
Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6132
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.
We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.
Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.
For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.
Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
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