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2023-01-06mb/google/brya/var/omnigul: use i2c1 for TPMjamie_chen
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-06mb/google/brya/var/omnigul: use RPL FSP headersjamie_chen
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL FSP headers for omnigul. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa/var/craask: Modify GPIOs for NVMeRen Kuo
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06mb/google/nissa: Disable stage cacheReka Norman
Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06Kconfig: Allow mainboards to disable stage cacheReka Norman
On recent Intel ChromeOS devices, although S3 is still supported, only S0ix is used on user devices, so we don't care about optimising S3 resume time. Disabing the stage cache saves boot time at the cost of increasing the S3 resume time. E.g. on nissa this reduces boot time by 6 ms and increases S3 resume time by 89 ms. BUG=b:247940538, b:192032803 TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE selected. Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macroPratikkumar Prajapati
Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU capabilities flags using cpuid_ext inline function. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71646 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05mb/google/skyrim/var/markarth: Update GPIO settingsJohn Su
Configure GPIOs based on b/263534907#comment4 from EE. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05Update vboot submodule to upstream mainElyes Haouas
Updating from commit id 196b0843e9 : to a09b792e6a : Makefile: Remove old include directories This brings in 9 new commits. Fix: cc1: error: firmware/lib/cryptolib/include: No such file or directory [-Werror=missing-include-dirs] cc1: error: firmware/lib20/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71582 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterunChris.Wang
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/google/brya/var/marasov: Disable FPMCU interfaceFrank Chu
Set fingerprint control GPIO to NC by HW design. BUG=b:264340020 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05mb/system76/tgl-u: Add FSP-S configs per variantTim Crawford
Configure CPU PCIe RP and IOM per variant. Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-05nb/intel/haswell: Specify supported memory typeElyes Haouas
Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-05mb/google/brya: Create omnigul variantjamie_chen
Create the omnigul variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263060849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OMNIGUL Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Define a more suitable MRC training text message"Jakub Czapiga
This reverts commit e45f70423e5da8509bae83aba84b08f8fc0f624e. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Add romstage early graphics for brya"Jakub Czapiga
This reverts commit 96d9b756690839c17b307a93b8a1898bd1c02ff5. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Define a more suitable MRC training text messageJeremy Compostella
This message is designed to reduce end-user confusion who may not know what memory training is. It also provides a maximum time estimation calibrated for brya devices. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=New message observed on skolas Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-04soc/intel: Create common function to check PCH slotKapil Porwal
BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04spd.h: Move enum ddr3_module_type to ddr3.hElyes Haouas
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVPHarsha B R
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig option, CSE reboots the system into CSE_RW FW region on cold reboot. BUG=b:224325352 TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe CSE boot to RW FW region as part of coreboot console log, localhost ~ # cbmem -c | grep cse [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04spd.h: Move enum ddr2_module_type to ddr2.hElyes Haouas
Move specific enum ddr2_module_type to <device/dram/ddr2.h>. Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04nb/intel/ironlake: Specify supported memory typeElyes Haouas
Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04payloads: Update GRUB2 stable version from 2.04 to 2.06Paul Menzel
GRUB2 was released on June 8th, 2021 [1]. [1]: https://lists.gnu.org/archive/html/grub-devel/2021-06/msg00022.html Change-Id: I050a78c769c3cd4c9ae627c7e3124a4894a018d7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/skyrim/var/markarth: Generate RAM IDs for new memory partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04mb/google/skyrim: Create markarth variantChao Gui
Create the markarth variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:262092858 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MARKARTH Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Signed-off-by: Chao Gui <chaogui@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-04mb/google/nissa/var/yaviks: Disable external fivrWisley Chen
In next phase, yaviks will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:263842258 TEST=build, boot to OS, suspend/resume work normally. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-04mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSIDKapil Porwal
BUG=none TEST=Verify presence of subsystem ID for fast_spi device on google/rex. lspci output before this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] lspci output after this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23] Note: UPD SiSkipSsidProgramming was set to 1 for above test. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-04soc/intel/common: Add API to check Key Locker supportPratikkumar Prajapati
Add is_keylocker_supported() API in common cpulib. This function checks if the CPU supports Key Locker feature. Returns true if Key Locker feature is supported otherwise false. Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya/var/gaelin: Use RPL FSP headersMike Shih
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP. Since we use RPL FSP and it will support ADL as well, we rename "Gaelin4ADL" to "Gaelin". BUG=b:258603624 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Cq-Depend: chrome-internal:5227091, chromium:4113361 Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/brya/var/lisbon: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:263050944 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I8495a88f2034e5e4ccf28ff53c81e0d6561e2e0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMeChris.Wang
winterhold/whiterun has different H/W topology to skyrim that the eMMC device is on a different GPP: skyrim: GPP1 -> SD winterhold : GPP1 -> eMMC BUG=b:263763288 BRANCH=none TEST=s0i3 stress over 2500 cycles. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-03vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-03soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/intel/baytrail: add _HRV to GPIO ACPI devicesMatt DeVillier
For some reason, the Windows LPEA drivers won't attach without _HRV (hardware version) defined for the GPIO controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load properly. Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03soc/intel/baytrail: add _HRV to I2C ACPI devicesMatt DeVillier
For some reason, the Windows i2c drivers won't attach without _HRV (hardware version) defined for the i2c controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load properly. Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03mb/google/samus: Set hidden flag for RT5677AA ACPI deviceMatt DeVillier
Coolstar's Windows drivers don't utilize it, and the Linux drivers don't care about _STA, so hide it from Windows to tidy up Device Manager. Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03mb/google/slippy/peppy: Set cypress TP IRQ to Level vs EdgeMatt DeVillier
Change the IRQ triggering from edge to level for cypress touchpad on peppy variant for compatibility with Windows drivers. TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad functional. Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02nb/intel/e7505: Specify supported memory typeElyes Haouas
Change-Id: Idda0a8330463205efe5ec5faa82a1f458894e521 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c3d1fc3d34e9b67ddb26afcaad3a47ffa92e2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on drallion, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/drallion: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02nb/intel/i440bx: Specify supported memory typeElyes Haouas
Change-Id: If94037f2b010527440795e6920dd7a533c52f606 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02mb/google/rex: Update USB2-C1 mappingSubrata Banik
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Remove USB2_8 ConnectionSubrata Banik
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Revise config for the Proto 1 buildSubrata Banik
1. Rename DB_USB4 for KB8010 while adding ANX7452 as different DB_USB4 option. 2. Add audio component for Soundwire. 3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S. Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02drivers/pc80/vga: Add API to write multi-line video messageSubrata Banik
This patch provides an API to allow users to output multi-line messages using VGA framebuffer. The current limitation with multiline message is that, vga_line_write() function is unable to understand newline character hence, eventually output multiple lines separated with a newline character with a single line statement. This patch ensures to parse the entire string and split it into multiple lines based on the newline character and print each line separately to the VFG framebuffer. User can choose to align the output video message as per given choice between left/center/right of the screen (i.e. enum VGA_TEXT_ALIGNMENT ). Additionally, added macros to define the horizontal screen alignment as well. Ideally if user would like to print the video message at the middle of the screen then the vertical alignment would be `VGA_TEXT_CENTER` and horizontal alignment would be `VGA_TEXT_HORIZONTAL_MIDDLE`. TEST=Able to build and boot Google/Taeko. While output a video message such as : "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device." Without this patch: Your device is finishing an update. This may take 1-2 minutes. nPlease do not turn off your device. With this patch: (in Left Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Right Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Center Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-02soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati
Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-01apollolake/include/soc/meminit.h: Add missing stdboolElyes Haouas
stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31security/intel/stm/StmPlatformResource.c: Fix typo on "threads"Elyes HAOUAS
Change-Id: Id57a9c689d5fa35cf1b4df9c37b12dd95cb9ef23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-31mb/google/brya/var/gladios: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:262959586 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/facebook/fbg1701: Enlarge COREBOOT region for VBOOT by 64kBYu-Ping Wu
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not large enough. Therefore, adjust vboot-rw.fmd (which is used only with VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to COREBOOT(CBFS) region. TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/google/rambi: Drop ChromeOS supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early flash access in romstage: /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps section .car.data VMA [00000000fe000000,00000000fe008787] make: *** [src/arch/x86/Makefile.inc:194: coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1 More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected, then the _bss region will increase by 0x10c8 bytes (for global variables such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed 0x8000. Since rambi has reached its AUE (2021-09-01), disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-30fw_config: Fix typo in documentBora Guvendik
There is no fw_config_probe_one api, change it to fw_config_probe. BUG=none TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I916713c038f72a1718be8c9d4e8e21420effbf76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-30mb/google/skyrim/var/frostflow: Update I2C setting for touchpadJohn Su
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 390.1 kHz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ied00e43e87404489af2b570206a70b685e554b78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVPHarsha B R
Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-28coding_style: Add more guidelines on error handling, die() and assert()Julius Werner
This patch adds a new section to the coding style which codifies existing practices about how to handle errors and how to use the die() and assert() macros. Also clean up some references to Linux-specific facilities that do not exist in coreboot in the adjacent function return type guidelines, and add a small blurb of documentation to the definition of the assert() macro itself. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice37ed9f995a56d69476e95a352209041b337284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-28src/security/vboot: Fix wrong CONFIG nameMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2af3bc9bf9eaf258b9180da5fc5494b21764f379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71518 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28mb/google/brya/var/kuldax: Add wifi sar tableDavid Wu
Add wifi sar table for kuldax BUG=b:248367859 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27mb/google/brya/var/kano: Enable Fast VMode for kanoDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVPHarsha B R
Add devicetree and GPIO configuration for MTL-RVP Changes include, 1. Add initial devicetree to support MTL-RVP board & variant 2. Add initial setup for ramstage gpio config BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS using subsequent patches in the train. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVPHarsha B R
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/google/rex: Enable PMC IPC configSubrata Banik
TEST=Able to build and boot Google/Rex. Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Meteor Lake IPC Controller") // _DDN: DOS Dev ice Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0B) } ... } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mb/google/brya/var/marasov: Add DmaProperty for ISHSubrata Banik
On Marasov, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on Marasov. TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/google/brya/var/marasov: Remove ISH firmware-nameSubrata Banik
For marasov, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com>
2022-12-26sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxElyes Haouas
Replace Divide (a,b,c,d) with: c = a % b d = a / b Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, c, d)` with these instructions: c = a % b d = a / b Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-26mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntaxFelix Singer
Replace `Not (a, b)` with `b = ~a`. Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26drivers/pc80/vga: Add NULL check for `vga_line_write()`Subrata Banik
This patch ensures vga_line_write() returns if the argument 1 (aka output string) is NULL. TEST=Able to build and boot Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-26sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntaxElyes Haouas
Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel/meteorlake: Make use of is_devfn_enabled() functionDinesh Gehlot
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on MTL. Port of 'commit 50134eccbdf4 ("soc/intel/alderlake: Make use of is_devfn_enabled() function")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25arch/riscv: Use 'enum cb_err'Elyes Haouas
Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25arch/x86: Use 'enum cb_err'Elyes Haouas
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25util/docker: Update setuptools to get dtc buildingMartin Roth
python3-setuptools installed via apt-get is not currently working to build dtc from git.kernel.org. Falling back to setuptools version 58.2.0 allows it to build again. The failure message was: /usr/lib/python3/dist-packages/setuptools/installer.py:27: SetuptoolsDeprecationWarning: setuptools.installer is deprecated. Requirements should be satisfied by a PEP 517 installer. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04cb6d776c3748f9a4b0cfc4ffd4f46458560d3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71500 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24util/mb/google: Add support for rexSubrata Banik
Add the file templates for creating a new variant of Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4abca1f999accc008eb2549fcc13199b8d9bdc7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Enable DPTF functionality for Rexzhaojohn
Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATETracy Wu
With enabling FSP Notify Phase APIs, it has chance to issue a global reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY ), which CSE already in idle mode and cause failure. For this reason we should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select SOC_INTEL_CSE_SEND_EOP_LATE instead. BUG=b:261544011 BRANCH=firmware-brya-14505.B TEST=tested and verified on Marasov, make sure this kind of global reset can be executed successfully. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 18:16:28 +0000