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-rw-r--r--util/inteltool/cpu.c138
-rw-r--r--util/inteltool/gpio.c23
-rw-r--r--util/inteltool/inteltool.c2
-rw-r--r--util/inteltool/inteltool.h2
-rw-r--r--util/inteltool/memory.c1
-rw-r--r--util/inteltool/pcie.c3
-rw-r--r--util/inteltool/powermgt.c36
-rw-r--r--util/inteltool/rootcmplx.c1
8 files changed, 206 insertions, 0 deletions
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index e6b28c087a..dd23d8196f 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -307,6 +307,143 @@ int print_intel_core_msrs(void)
//{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
};
+ /* Pentium 4 and XEON */
+ /*
+ * All MSRs per
+ *
+ * Intel® 64 and IA-32 Architectures
+ * Software Developer.s Manual
+ * Volume 3B:
+ * System Programming Guide, Part 2
+ *
+ * Table B-5
+ */
+ static const msr_entry_t modelf4x_global_msrs[] = {
+ { 0x0000, "IA32_P5_MC_ADDR" },
+ { 0x0001, "IA32_P5_MC_TYPE" },
+ { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x002a, "MSR_EBC_HARD_POWERON" },
+ { 0x002b, "MSR_EBC_SOFT_POWRON" },
+ { 0x002c, "MSR_EBC_FREQUENCY_ID" },
+// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x019d, "MSR_THERM2_CTL" },
+ { 0x01a0, "IA32_MISC_ENABLE" },
+ { 0x01a1, "MSR_PLATFORM_BRV" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x02ff, "IA32_MTRR_DEF_TYPE" },
+ { 0x0300, "MSR_BPU_COUNTER0" },
+ { 0x0301, "MSR_BPU_COUNTER1" },
+ { 0x0302, "MSR_BPU_COUNTER2" },
+ { 0x0303, "MSR_BPU_COUNTER3" },
+ /* Skipped through 0x3ff for now*/
+
+ /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
+ * set in MCX_STATUS */
+ { 0x400, "IA32_MC0_CTL" },
+ { 0x401, "IA32_MC0_STATUS" },
+ { 0x402, "IA32_MC0_ADDR" },
+ { 0x403, "IA32_MC0_MISC" },
+ { 0x404, "IA32_MC1_CTL" },
+ { 0x405, "IA32_MC1_STATUS" },
+ { 0x406, "IA32_MC1_ADDR" },
+ { 0x407, "IA32_MC1_MISC" },
+ { 0x408, "IA32_MC2_CTL" },
+ { 0x409, "IA32_MC2_STATUS" },
+ { 0x40a, "IA32_MC2_ADDR" },
+ { 0x40b, "IA32_MC2_MISC" },
+ { 0x40c, "IA32_MC3_CTL" },
+ { 0x40d, "IA32_MC3_STATUS" },
+ { 0x40e, "IA32_MC3_ADDR" },
+ { 0x40f, "IA32_MC3_MISC" },
+ { 0x410, "IA32_MC4_CTL" },
+ { 0x411, "IA32_MC4_STATUS" },
+ { 0x412, "IA32_MC4_ADDR" },
+ { 0x413, "IA32_MC4_MISC" },
+ };
+
+ static const msr_entry_t modelf4x_per_core_msrs[] = {
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x009b, "IA32_SMM_MONITOR_CTL" },
+ { 0x00fe, "IA32_MTRRCAP" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x0179, "IA32_MCG_CAP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0180, "MSR_MCG_RAX" },
+ { 0x0181, "MSR_MCG_RBX" },
+ { 0x0182, "MSR_MCG_RCX" },
+ { 0x0183, "MSR_MCG_RDX" },
+ { 0x0184, "MSR_MCG_RSI" },
+ { 0x0185, "MSR_MCG_RDI" },
+ { 0x0186, "MSR_MCG_RBP" },
+ { 0x0187, "MSR_MCG_RSP" },
+ { 0x0188, "MSR_MCG_RFLAGS" },
+ { 0x0189, "MSR_MCG_RIP" },
+ { 0x018a, "MSR_MCG_MISC" },
+ // 0x18b-f Reserved
+ { 0x0190, "MSR_MCG_R8" },
+ { 0x0191, "MSR_MCG_R9" },
+ { 0x0192, "MSR_MCG_R10" },
+ { 0x0193, "MSR_MCG_R11" },
+ { 0x0194, "MSR_MCG_R12" },
+ { 0x0195, "MSR_MCG_R13" },
+ { 0x0196, "MSR_MCG_R14" },
+ { 0x0197, "MSR_MCG_R15" },
+ { 0x0198, "IA32_PERF_STATUS" },
+ { 0x0199, "IA32_PERF_CTL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
+ { 0x01d7, "MSR_LER_FROM_LIP" },
+ { 0x01d8, "MSR_LER_TO_LIP" },
+ { 0x01d9, "MSR_DEBUGCTLA" },
+ { 0x01da, "MSR_LASTBRANCH_TOS" },
+ { 0x0277, "IA32_PAT" },
+ /** Virtualization
+ { 0x480, "IA32_VMX_BASIC" },
+ through
+ { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
+ Not implemented in my CPU
+ */
+ { 0x0600, "IA32_DS_AREA" },
+ /* 0x0680 - 0x06cf Branch Records Skipped */
+
+ };
+
+
+
typedef struct {
unsigned int model;
const msr_entry_t *global_msrs;
@@ -319,6 +456,7 @@ int print_intel_core_msrs(void)
{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
+ { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
};
cpu_t *cpu = NULL;
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index b4f11691dd..a02817d586 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -58,6 +58,24 @@ static const io_register_t ich4_gpio_registers[] = {
{ 0x3C, 4, "RESERVED" }
};
+static const io_register_t ich6_gpio_registers[] = {
+ { 0x00, 4, "GPIO_USE_SEL" },
+ { 0x08, 4, "RESERVED" },
+ { 0x0c, 4, "GP_LVL" },
+ { 0x10, 4, "RESERVED" },
+ { 0x14, 4, "RESERVED" },
+ { 0x18, 4, "GPO_BLINK" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "RESERVED" },
+ { 0x2c, 4, "GPI_INV" },
+ { 0x30, 4, "GPIO_USE_SEL2" },
+ { 0x34, 4, "GP_IO_SEL2" },
+ { 0x38, 4, "GP_LVL2" },
+ { 0x04, 4, "GP_IO_SEL" },
+};
+
static const io_register_t ich7_gpio_registers[] = {
{ 0x00, 4, "GPIO_USE_SEL" },
{ 0x04, 4, "GP_IO_SEL" },
@@ -119,6 +137,11 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich7_gpio_registers;
size = ARRAY_SIZE(ich7_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH6:
+ gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ gpio_registers = ich6_gpio_registers;
+ size = ARRAY_SIZE(ich6_gpio_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6f7530067c..2c8ab747dc 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -36,6 +36,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
@@ -50,6 +51,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index db386d0c93..74bfdca802 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -38,6 +38,7 @@
#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
+#define PCI_DEVICE_ID_INTEL_ICH6 0x2640
#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
@@ -49,6 +50,7 @@
#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
+#define PCI_DEVICE_ID_INTEL_82915 0x2580
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index b0db13ce20..5c5a07e03a 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -34,6 +34,7 @@ int print_mchbar(struct pci_dev *nb)
printf("\n============= MCHBAR ============\n\n");
switch (nb->device_id) {
+ case PCI_DEVICE_ID_INTEL_82915:
case PCI_DEVICE_ID_INTEL_82945GM:
case PCI_DEVICE_ID_INTEL_82945P:
case PCI_DEVICE_ID_INTEL_82975X:
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 81e71e1a4f..5acb0b6ba2 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -33,6 +33,7 @@ int print_epbar(struct pci_dev *nb)
printf("\n============= EPBAR =============\n\n");
switch (nb->device_id) {
+ case PCI_DEVICE_ID_INTEL_82915:
case PCI_DEVICE_ID_INTEL_82945GM:
case PCI_DEVICE_ID_INTEL_82945P:
case PCI_DEVICE_ID_INTEL_82975X:
@@ -84,6 +85,7 @@ int print_dmibar(struct pci_dev *nb)
printf("\n============= DMIBAR ============\n\n");
switch (nb->device_id) {
+ case PCI_DEVICE_ID_INTEL_82915:
case PCI_DEVICE_ID_INTEL_82945GM:
case PCI_DEVICE_ID_INTEL_82945P:
case PCI_DEVICE_ID_INTEL_82975X:
@@ -137,6 +139,7 @@ int print_pciexbar(struct pci_dev *nb)
printf("========= PCIEXBAR ========\n\n");
switch (nb->device_id) {
+ case PCI_DEVICE_ID_INTEL_82915:
case PCI_DEVICE_ID_INTEL_82945GM:
case PCI_DEVICE_ID_INTEL_82945P:
case PCI_DEVICE_ID_INTEL_82975X:
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index fbf9e3a07a..47db163eed 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -145,6 +145,37 @@ static const io_register_t ich8_pm_registers[] = {
{ 0x7c, 4, "RESERVED" },
};
+/*
+ * INTEL I/O Controller Hub 6 Family
+ * http://www.intel.com/assets/pdf/datasheet/301473.pdf
+ */
+static const io_register_t ich6_pm_registers[] = {
+ /* 10.8.3 */
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* These registers return 0 on read, but reading them may cause
+ * the system to enter C2/C3/C4 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2" },
+ { 0x15, 1, "LV3 (Mobile Only)" },
+ { 0x16, 1, "LV4 (Mobile Only)" },
+#endif
+ { 0x20, 1, "PM2_CNT (Mobile Only)" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2c, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x50, 1, "SS_CNT (Mobile Only)" },
+ { 0x54, 4, "C3_RES (Mobile Only)" },
+};
+
static const io_register_t ich4_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -331,6 +362,11 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich8_pm_registers;
size = ARRAY_SIZE(ich8_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH6:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich6_pm_registers;
+ size = ARRAY_SIZE(ich6_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH4:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich4_pm_registers;
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 438e5b0b11..9c3f70f4ef 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -31,6 +31,7 @@ int print_rcba(struct pci_dev *sb)
printf("\n============= RCBA ==============\n\n");
switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_ICH6:
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 10:28:05 +0000