diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/socket_754/Config.lb | 3 | ||||
| -rw-r--r-- | src/cpu/amd/socket_754/chip.h | 4 | ||||
| -rw-r--r-- | src/cpu/amd/socket_754/socket_754.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/Config.lb | 317 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/Options.lb | 210 |
5 files changed, 334 insertions, 207 deletions
diff --git a/src/cpu/amd/socket_754/Config.lb b/src/cpu/amd/socket_754/Config.lb new file mode 100644 index 0000000000..cf16a0e73c --- /dev/null +++ b/src/cpu/amd/socket_754/Config.lb @@ -0,0 +1,3 @@ +config chip.h +object socket_754.o +dir /cpu/amd/model_fxx diff --git a/src/cpu/amd/socket_754/chip.h b/src/cpu/amd/socket_754/chip.h new file mode 100644 index 0000000000..d9f3600b2c --- /dev/null +++ b/src/cpu/amd/socket_754/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_amd_socket_754_ops; + +struct cpu_amd_socket_754_config { +}; diff --git a/src/cpu/amd/socket_754/socket_754.c b/src/cpu/amd/socket_754/socket_754.c new file mode 100644 index 0000000000..6274e6d55a --- /dev/null +++ b/src/cpu/amd/socket_754/socket_754.c @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + + +struct chip_operations cpu_amd_socket_754_ops = { + .name = "socket 754", +}; diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb index 7147b4546a..ad8bad9325 100644 --- a/src/mainboard/amd/solo/Config.lb +++ b/src/mainboard/amd/solo/Config.lb @@ -1,122 +1,3 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HARD_RESET_BUS -uses HARD_RESET_DEVICE -uses HARD_RESET_FUNCTION -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_STREAM -uses CONFIG_ROM_STREAM_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR - - -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE=262144 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -default HARD_RESET_BUS=1 -default HARD_RESET_DEVICE=5 -default HARD_RESET_FUNCTION=0 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=8 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default LinuxBIOS cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## AMD Solo is a 1cpu board -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="SOLO" -default MAINBOARD_VENDOR="AMD" - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE - ## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. @@ -135,7 +16,6 @@ end ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_STREAM = 1 ## ## Compute where this copy of linuxBIOS will start in the boot rom @@ -152,12 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end -#cpu k8 end +arch i386 end ## ## Build the objects we have code for in this directory. @@ -166,12 +41,13 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o ## ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c" + depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" end @@ -180,11 +56,11 @@ makerule ./failover.inc action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" end -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h " +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h " action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end -makerule ./auto.inc +makerule ./auto.inc depends "./auto.E ./romcc" action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc" end @@ -192,21 +68,20 @@ end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -#mainboardinit cpu/i386/bist32.inc -ldscript /cpu/i386/entry16.lds -ldscript /cpu/i386/entry32.lds +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds ## ## Build our reset vector (This is where linuxBIOS is entered) ## -if USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript /cpu/i386/reset16.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/i386/reset32.inc - ldscript /cpu/i386/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end ### Should this be in the northbridge code? @@ -218,18 +93,13 @@ mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -## -## Setup our mtrrs -## -mainboardinit cpu/k8/earlymtrr.inc - ### -### This is the early phase of linuxBIOS startup +### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end @@ -240,74 +110,107 @@ end ## ## Setup RAM ## -mainboardinit cpu/k8/enable_mmx_sse.inc +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc -mainboardinit cpu/k8/disable_mmx_sse.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc ## -## Include the secondary Configuration files +## Include the secondary Configuration files ## dir /pc80 config chip.h -northbridge amd/amdk8 "mc0" - pci 0:18.0 - pci 0:18.0 - pci 0:18.0 - pci 0:18.1 - pci 0:18.2 - pci 0:18.3 - southbridge amd/amd8151 "amd8151" link 0 - pci 0:0.0 - pci 0:1.0 - end - southbridge amd/amd8111 "amd8111" link 0 - pci 0:0.0 - pci 0:1.0 on - pci 0:1.1 on - pci 0:1.2 on - pci 0:1.3 on - pci 0:1.5 on - pci 0:1.6 on - pci 1:0.0 on - pci 1:0.1 on - pci 1:0.2 on - # pci 1:1.0 off - superio NSC/pc87360 link 1 - pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - pnp 2e.4 off # SWC - pnp 2e.5 off # Mouse - pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - pnp 2e.7 off # GPIO - pnp 2e.8 off # ACB - pnp 2e.9 off # FSCM - pnp 2e.a off # WDT +# sample config for arima/hdama +chip northbridge/amd/amdk8 + device pci_domain 0 on + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/NSC/pc87360 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic + #phillips pca9545 smbus mux + device i2c 70 on + # analog_devices adm1026 + chip drivers/generic/generic + device i2c 2c on end + end + end + device i2c 70 on end + device i2c 70 on end + device i2c 70 on end + end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end + device pci 1.5 off end + device pci 1.6 on end + end + end # device pci 18.0 + + device pci 18.0 on end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + device apic_cluster 0 on + chip cpu/amd/socket_754 + device apic 0 on end end end end -cpu k8 "cpu0" -end - -## -## Include the old serial code for those few places that still need it. -## -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -#mainboardinit cpu/i386/bist32_fail.inc - diff --git a/src/mainboard/amd/solo/Options.lb b/src/mainboard/amd/solo/Options.lb new file mode 100644 index 0000000000..998215d6c6 --- /dev/null +++ b/src/mainboard/amd/solo/Options.lb @@ -0,0 +1,210 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HARD_RESET_BUS +uses HARD_RESET_DEVICE +uses HARD_RESET_FUNCTION +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses CC +uses HOSTCC +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=524288 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +default FALLBACK_SIZE=131072 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Funky hard reset implementation +## +default HARD_RESET_BUS=1 +default HARD_RESET_DEVICE=4 +default HARD_RESET_FUNCTION=0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=9 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="SOLO" +default MAINBOARD_VENDOR="AMD" + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end |