diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/via/epia-m700/Options.lb | 42 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/dram_init.h | 3 |
2 files changed, 23 insertions, 22 deletions
diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb index 2bce2960ac..5fe9240778 100644 --- a/src/mainboard/via/epia-m700/Options.lb +++ b/src/mainboard/via/epia-m700/Options.lb @@ -72,17 +72,17 @@ uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses MAX_RAM_SLOTS -uses USB_ENABLE -uses EHCI_ENABLE -uses HPET_ENABLE -uses USB_PORTNUM -uses FULL_ROM_SIZE -uses FULL_ROM_BASE -uses PAYLOAD_IS_SEABIOS -uses VIACONFIG_TOP_SM_SIZE_MB -uses VIACONFIG_VGA_PCI_10 -uses VIACONFIG_VGA_PCI_14 +#uses MAX_RAM_SLOTS +#uses USB_ENABLE +#uses EHCI_ENABLE +#uses HPET_ENABLE +#uses USB_PORTNUM +#uses FULL_ROM_SIZE +#uses FULL_ROM_BASE +#uses PAYLOAD_IS_SEABIOS +#uses VIACONFIG_TOP_SM_SIZE_MB +#uses VIACONFIG_VGA_PCI_10 +#uses VIACONFIG_VGA_PCI_14 ## New options default USE_DCACHE_RAM = 1 @@ -91,18 +91,18 @@ default DCACHE_RAM_BASE = 0xffef0000 # default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. default DCACHE_RAM_SIZE = 8 * 1024 default CONFIG_USE_INIT = 0 -default MAX_RAM_SLOTS = 2 -default USB_ENABLE = 1 -default EHCI_ENABLE = 1 -default HPET_ENABLE = 1 -default USB_PORTNUM = 2 -default FULL_ROM_SIZE = 512 * 1024 -default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1) -default VIACONFIG_TOP_SM_SIZE_MB = 0 +#default MAX_RAM_SLOTS = 2 +#default USB_ENABLE = 1 +#default EHCI_ENABLE = 1 +#default HPET_ENABLE = 1 +#default USB_PORTNUM = 2 +#default FULL_ROM_SIZE = 512 * 1024 +#default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1) +#default VIACONFIG_TOP_SM_SIZE_MB = 0 # default VIACONFIG_VGA_PCI_10 = 0xd0000008 # default VIACONFIG_VGA_PCI_14 = 0xfd000000 -default VIACONFIG_VGA_PCI_10 = 0xf8000008 -default VIACONFIG_VGA_PCI_14 = 0xfc000000 +#default VIACONFIG_VGA_PCI_10 = 0xf8000008 +#default VIACONFIG_VGA_PCI_14 = 0xfc000000 default ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 1 diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index 50007c18a7..0a6bb1039f 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -110,7 +110,8 @@ #define SPD_DATA_SIZE 44 //Dram cofig are /*the most number of socket*/ -//#define MAX_RAM_SLOTS 2 +#define MAX_RAM_SLOTS 2 + #define MAX_SOCKETS MAX_RAM_SLOTS #define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */ /*the most number of RANKs on a DIMM*/ |