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-rw-r--r--src/mainboard/google/brya/Kconfig.name3
-rw-r--r--src/mainboard/google/brya/variants/anahera/Makefile.inc6
-rw-r--r--src/mainboard/google/brya/variants/anahera/fw_config.c57
-rw-r--r--src/mainboard/google/brya/variants/anahera/gpio.c141
-rw-r--r--src/mainboard/google/brya/variants/anahera/overridetree.cb356
5 files changed, 559 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 946632b735..51bc8e1744 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -59,3 +59,6 @@ config BOARD_GOOGLE_FELWINTER
config BOARD_GOOGLE_ANAHERA
bool "-> Anahera"
select BOARD_GOOGLE_BASEBOARD_BRYA
+ select DRIVERS_GENESYSLOGIC_GL9763E
+ select DRIVERS_GFX_GENERIC
+ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
diff --git a/src/mainboard/google/brya/variants/anahera/Makefile.inc b/src/mainboard/google/brya/variants/anahera/Makefile.inc
new file mode 100644
index 0000000000..f2a624c0e8
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/anahera/fw_config.c b/src/mainboard/google/brya/variants/anahera/fw_config.c
new file mode 100644
index 0000000000..b12293f3be
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera/fw_config.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config dmic_enable_pads[] = {
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0 */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0 */
+
+};
+
+static const struct pad_config dmic_disable_pads[] = {
+ PAD_NC(GPP_R4, NONE),
+ PAD_NC(GPP_R5, NONE),
+};
+
+static const struct pad_config i2s_enable_pads[] = {
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
+};
+
+static const struct pad_config i2s_disable_pads[] = {
+ PAD_NC(GPP_R0, NONE),
+ PAD_NC(GPP_R1, NONE),
+ PAD_NC(GPP_R2, NONE),
+ PAD_NC(GPP_R3, NONE),
+ PAD_NC(GPP_S0, NONE),
+ PAD_NC(GPP_S1, NONE),
+ PAD_NC(GPP_S2, NONE),
+ PAD_NC(GPP_S3, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+ if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
+ printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
+ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
+ gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
+ return;
+ }
+
+ if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) ||
+ fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682IVS_I2S))) {
+ printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
+ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
+ gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
+ }
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c
new file mode 100644
index 0000000000..1ce98e4d10
--- /dev/null
+++ b/src/mainboard/google/brya/variants/anahera/gpio.c
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+ /* A7 : SRCCLK_OE7# ==> NC */
+ PAD_NC(GPP_A7, NONE),
+ /* A17 : DISP_MISCC ==> NC */
+ PAD_NC(GPP_A17, NONE),
+ /* A19 : DDSP_HPD1 ==> NC */
+ PAD_NC(GPP_A19, NONE),
+ /* A20 : DDSP_HPD2 ==> NC */
+ PAD_NC(GPP_A20, NONE),
+ /* A21 : DDPC_CTRCLK ==> NC */
+ PAD_NC(GPP_A21, NONE),
+ /* A22 : DDPC_CTRLDATA ==> NC */
+ PAD_NC(GPP_A22, NONE),
+
+ /* B3 : PROC_GP2 ==> eMMC_PERST_L */
+ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+ /* B5 : ISH_I2C0_SDA ==> NC */
+ PAD_NC(GPP_B5, NONE),
+ /* B6 : ISH_I2C0_SCL ==> NC */
+ PAD_NC(GPP_B6, NONE),
+ /* B15 : TIME_SYNC0 ==> NC */
+ PAD_NC(GPP_B15, NONE),
+
+ /* C3 : SML0CLK ==> NC */
+ PAD_NC(GPP_C3, NONE),
+ /* C4 : SML0DATA ==> NC */
+ PAD_NC(GPP_C4, NONE),
+
+ /* D3 : ISH_GP3 ==> NC */
+ PAD_NC(GPP_D3, NONE),
+ /* D5 : SRCCLKREQ0# ==> NC */
+ PAD_NC(GPP_D5, NONE),
+ /* D13 : ISH_UART0_RXD ==> NC */
+ PAD_NC(GPP_D13, NONE),
+ /* D14 : ISH_UART0_TXD ==> NC */
+ PAD_NC(GPP_D14, NONE),
+ /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
+ PAD_CFG_GPO(GPP_D15, 1, DEEP),
+ /* D16 : ISH_UART0_CTS# ==> NC */
+ PAD_NC(GPP_D16, NONE),
+ /* D17 : UART1_RXD ==> NC */
+ PAD_NC(GPP_D17, NONE),
+
+ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
+ PAD_CFG_GPO(GPP_E0, 1, PLTRST),
+ /* E3 : PROC_GP0 ==> NC */
+ PAD_NC(GPP_E3, NONE),
+ /* E7 : PROC_GP1 ==> NC */
+ PAD_NC(GPP_E7, NONE),
+ /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+ PAD_CFG_GPO(GPP_E20, 1, DEEP),
+ /* E23 : DDPA_CTRLDATA ==> NC */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F20 : EXT_PWR_GATE# ==> NC */
+ PAD_NC(GPP_F20, NONE),
+
+ /* H20 : IMGCLKOUT1 ==> NC */
+ PAD_NC(GPP_H20, NONE),
+ /* H21 : IMGCLKOUT2 ==> Privacy screen */
+ PAD_CFG_GPO(GPP_H21, 0, DEEP),
+ /* H22 : IMGCLKOUT3 ==> NC */
+ PAD_NC(GPP_H22, NONE),
+ /* H23 : SRCCLKREQ5# ==> NC */
+ PAD_NC(GPP_H23, NONE),
+
+ /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
+ PAD_NC(GPP_R6, NONE),
+ /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
+ PAD_NC(GPP_R7, NONE),
+
+ /* S4 : SNDW2_CLK ==> NC */
+ PAD_NC(GPP_S4, NONE),
+ /* S5 : SNDW2_DATA ==> NC */
+ PAD_NC(GPP_S5, NONE),
+ /* S6 : SNDW3_CLK ==> NC */
+ PAD_NC(GPP_S6, NONE),
+ /* S7 : SNDW3_DATA ==> NC */
+ PAD_NC(GPP_S7, NONE),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+ /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+ /*
+ * D1 : ISH_GP1 ==> FP_RST_ODL
+ * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+ * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+ * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+ * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+ * FPMCU not working after a S3 resume. This is a known issue.
+ */
+ PAD_CFG_GPO(GPP_D1, 0, DEEP),
+ /* D2 : ISH_GP2 ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_D11, 1, DEEP),
+ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
+ PAD_CFG_GPO(GPP_E0, 0, DEEP),
+ /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+ /* E15 : RSVD_TP ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* E16 : RSVD_TP ==> WWAN_RST_L */
+ PAD_CFG_GPO(GPP_E16, 0, DEEP),
+ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_H13, 1, DEEP),
+ /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
+ PAD_CFG_GPO(GPP_E20, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+ *num = ARRAY_SIZE(override_gpio_table);
+ return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 4f2c04a57a..79f7a974cb 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -1,6 +1,354 @@
+fw_config
+ field DB_SD 0 1
+ option SD_ABSENT 0
+ option SD_GL9750 1
+ end
+ field KB_BL 2 2
+ option KB_BL_ABSENT 0
+ option KB_BL_PRESENT 1
+ end
+ field AUDIO 3 5
+ option AUDIO_UNKNOWN 0
+ option MAX98360_ALC5682I_I2S 1
+ option MAX98360_ALC5682IVS_I2S 2
+ end
+ field DB_LTE 6 7
+ option LTE_ABSENT 0
+ option LTE_USB 1
+ end
+ field EPS 10 10
+ option PRIVACY_SCREEN_ABSENT 0
+ option PRIVACY_SCREEN 1
+ end
+end
chip soc/intel/alderlake
-
- device domain 0 on
- end
-
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | |
+ #| I2C3 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+ device domain 0 on
+ device ref igpu on
+ chip drivers/gfx/generic
+ register "device_count" = "1"
+ register "device[0].name" = ""LCD""
+ # Internal panel on the first port of the graphics chip
+ register "device[0].addr" = "0x80010400"
+ register "device[0].privacy.enabled" = "1"
+ register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)"
+ device generic 0 on
+ probe EPS PRIVACY_SCREEN
+ end
+ end
+ end # Integrated Graphics Device
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""DRAM""
+ register "options.tsr[1].desc" = ""Charger""
+ # TODO: below values are initial reference values only
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
+ }"
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ }"
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 3000,
+ .max_power = 15000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 55000,
+ .max_power = 55000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 1700 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+ device generic 0 on end
+ end
+ end
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 on
+ # Enable PCIE eMMC bridge 7 using clk 6
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .clk_src = 6,
+ .clk_req = 2,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+ }"
+ end #PCIE7 EMMC
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port3 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp8 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+ register "srcclk_pin" = "3"
+ device generic 0 on end
+ end
+ end #PCIE8 SD card
+ device ref i2c0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Headset Codec""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on
+ probe AUDIO MAX98360_ALC5682I_I2S
+ end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""RTL5682""
+ register "name" = ""RT58""
+ register "desc" = ""Headset Codec""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on
+ probe AUDIO MAX98360_ALC5682IVS_I2S
+ end
+ end
+ end #I2C0
+ device ref i2c1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+ register "reset_delay_ms" = "100"
+ register "reset_off_delay_ms" = "5"
+ register "enable_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+ register "enable_delay_ms" = "10"
+ register "enable_off_delay_ms" = "1"
+ register "stop_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GTCH7503""
+ register "generic.desc" = ""G2TOUCH Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
+ register "generic.reset_delay_ms" = "50"
+ register "generic.enable_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+ register "generic.enable_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 40 on end
+ end
+ end
+ device ref i2c5 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+ register "wake" = "GPE0_DW2_14"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end
+ device ref hda on
+ chip drivers/generic/max98357a
+ register "hid" = ""MX98357A""
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ device spi 0 on end
+ end # FPMCU
+ end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "1"
+ register "usb3_port_number" = "1"
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "3"
+ register "usb3_port_number" = "3"
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(3, 1)"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(4, 2)"
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C2 (DB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(3, 1)"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port (DB)""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(4, 1)"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port (DB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(4, 1)"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(4, 2)"
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb3_port4 on end
+ end
+ end
+ end
+ end
+ end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 09:10:05 +0000