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-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c7
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c6
2 files changed, 2 insertions, 11 deletions
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 55a0dab629..0c389d5443 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -158,8 +158,6 @@ static void add_fixed_resources(struct device *dev, int index)
static void nb_read_resources(struct device *dev)
{
- struct resource *res;
-
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
@@ -168,10 +166,7 @@ static void nb_read_resources(struct device *dev)
mmconf_resource(dev, MMIO_CONF_BASE);
/* NB IOAPIC2 resource */
- res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */
- res->base = IO_APIC2_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ mmio_range(dev, IO_APIC2_ADDR, IO_APIC2_ADDR, 0x1000);
add_fixed_resources(dev, 0);
}
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index ecdbe4fee9..081bc1f47d 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -59,7 +59,6 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
static void read_resources(struct device *dev)
{
unsigned int idx = 0;
- struct resource *res;
/* The northbridge has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
@@ -72,10 +71,7 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */
- res = new_resource(dev, idx++); /* IOAPIC2 */
- res->base = IO_APIC2_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
}
static void set_resource(struct device *dev, struct resource *res, u32 nodeid)