diff options
Diffstat (limited to 'src')
45 files changed, 48 insertions, 48 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a33ee18303..e489e25f18 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 8999aa3d63..21661f905f 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -36,7 +36,7 @@ chip soc/intel/skylake subsystemid 0x1025 0x1037 inherit device ref system_agent on # Enable "Enhanced Intel SpeedStep" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 97C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 92e4ba7824..59e297ca9f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -4,7 +4,7 @@ chip soc/intel/skylake register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index f078cdf396..11a8749836 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -17,7 +17,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index bb896aab2c..ac4ec4658b 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/skylake # FSP Configuration register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 7330862960..ad735ed585 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/skylake register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" # "Intel SpeedStep Technology" - register "eist_enable" = "1" + register "eist_enable" = "true" # DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index db843f596a..c0779c664b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25b8d9f159..2976deb12d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Mapping of USB port # to device #+----------------+-------+-----------------------------------+ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f94e9327b..97b0c20a6d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -10,7 +10,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 74780d005b..3b07bf7c02 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ }" - register "eist_enable" = "1" + register "eist_enable" = "true" device domain 0 on subsystemid 0x103c 0x2b5e inherit diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index e6655b536a..51d3b26798 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -6,7 +6,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9599ceccfb..4f7d7eb631 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -7,7 +7,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index d7d83cdb29..e87467913f 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index cfe6b508f4..738c8a3030 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration - register "eist_enable" = "1" + register "eist_enable" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index bc000c70f3..317de80d8f 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -108,7 +108,7 @@ chip soc/intel/cannonlake register "s0ix_enable" = "0" # Enable Turbo - register "eist_enable" = "1" + register "eist_enable" = "true" register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 14e604890e..01c5df7724 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937c71..df0dbdfdb0 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/elkhartlake }" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502b0b..9b0357f654 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "eist_enable" = "1" + register "eist_enable" = "true" # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index cc1433d7d4..dfacdea686 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index c992c4f2bc..f8e494a53b 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake - register "eist_enable" = "1" + register "eist_enable" = "true" register "s0ix_enable" = "0" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 80c497b81c..e26e6b2dd6 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/cannonlake register "s0ix_enable" = "0" - register "eist_enable" = "1" + register "eist_enable" = "true" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 01ae0f264d..5b448f91cd 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index d38639790c..311d96cc9b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - register "eist_enable" = "1" + register "eist_enable" = "true" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index f7096641e4..a555394214 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" # FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 81d593f170..df8bd990ec 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 08f5006d4f..87ccb8a035 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 26197a2e1d..11441621c2 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Graphics # Not used but timings left for reference diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 2a4a21a8aa..f5b7a1fd8f 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 81b023c310..4e2731859f 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,7 +11,7 @@ chip soc/intel/alderlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index dee0bf5015..3a99ab44cb 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index aaffd4ea9b..ed0a520d6e 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index ba88a7159f..5760e669f4 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index e4658a72e6..925144033b 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -11,7 +11,7 @@ chip soc/intel/skylake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 4eea043ee1..cc3c619abd 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c198ea93b2..7e3ef0ccd5 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 25ba3a6694..dd4d5977b0 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -11,7 +11,7 @@ chip soc/intel/alderlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 58a4fcf8fb..2bda9dc037 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/tigerlake # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # CPU (soc/intel/tigerlake/cpu.c) # Power limits diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d7a527a690..d96249db51 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/tigerlake # ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable s0ix, required for TGL-U register "s0ix_enable" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 53d5943f0f..1c5d720054 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/cannonlake }" # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a490540fc5..b58b244607 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -467,7 +467,7 @@ struct soc_intel_alderlake_config { bool skip_ext_gfx_scan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 1e7e5a5225..97657e2feb 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,7 +237,7 @@ struct soc_intel_cannonlake_config { /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5330f223ad..e5c7f54046 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -258,8 +258,8 @@ struct soc_intel_elkhartlake_config { uint8_t Heci2Enable; uint8_t Heci3Enable; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + /* Enable/Disable EIST. true:Enabled, false:Disabled */ + bool eist_enable; /* * SerialIO device mode selection: diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f8d069e004..542ccb61cb 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -178,7 +178,7 @@ struct soc_intel_jasperlake_config { /* Gfx related */ bool SkipExtGfxScan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 7997f7df44..4e0ba86fd7 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -459,8 +459,8 @@ struct soc_intel_skylake_config { u8 SlowSlewRateForSa; /* Enable/Disable EIST - * 1b - Enabled - * 0b - Disabled + * true - Enabled + * false - Disabled */ bool eist_enable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f8d4d4907b..e8d417e3a8 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -286,8 +286,8 @@ struct soc_intel_tigerlake_config { /* Gfx related */ uint8_t SkipExtGfxScan; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + /* Enable/Disable EIST. true:Enabled, false:Disabled */ + bool eist_enable; /* Enable C6 DRAM */ uint8_t enable_c6dram; |