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-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb1
-rw-r--r--src/soc/intel/tigerlake/chip.h1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 9ed8fb299e..643bdc1bf7 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -25,7 +25,6 @@ chip soc/intel/tigerlake
# FSP configuration
register "SaGv" = "SaGv_Disabled"
- register "SataEnable" = "1"
register "SataMode" = "0"
register "SataSalpSupport" = "1"
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index eee29ef2ce..ca9661f09f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -146,7 +146,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA
- register "SataEnable" = "1"
register "SataMode" = "0"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "0"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e729e8c0ee..09c8db1caf 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -215,7 +215,6 @@ struct soc_intel_tigerlake_config {
uint8_t SlowSlewRate;
/* SATA related */
- uint8_t SataEnable;
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];