diff options
Diffstat (limited to 'src')
782 files changed, 4575 insertions, 4575 deletions
diff --git a/src/Kconfig b/src/Kconfig index 026e99da78..67ac5753a7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -454,8 +454,8 @@ config FALLBACK_BOOTSPLASH_FILE depends on BOOTSPLASH default "bootsplash.jpg" help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE @@ -568,7 +568,7 @@ config X86EMU_DEBUG_TRACE depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. - + WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c index 9bab92831f..e5169eaf43 100644 --- a/src/arch/i386/boot/acpi.c +++ b/src/arch/i386/boot/acpi.c @@ -7,7 +7,7 @@ * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH * - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * Copyright (C) 2004 Nick Barker * @@ -15,12 +15,12 @@ * 2005.9 yhlu add SRAT table generation */ -/* +/* * Each system port implementing ACPI has to provide two functions: - * + * * write_acpi_tables() * acpi_dump_apics() - * + * * See Kontron 986LCD-M port for a good example of an ACPI implementation * in coreboot. */ @@ -59,10 +59,10 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) if (rsdp->xsdt_address) { xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address); } - + /* This should always be MAX_ACPI_TABLES */ entries_num = ARRAY_SIZE(rsdt->entry); - + for (i = 0; i < entries_num; i++) { if(rsdt->entry[i] == 0) break; @@ -120,10 +120,10 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) lapic->type=0; lapic->length=sizeof(acpi_madt_lapic_t); lapic->flags=1; - + lapic->processor_id=cpu; lapic->apic_id=apic; - + return(lapic->length); } @@ -146,16 +146,16 @@ unsigned long acpi_create_madt_lapics(unsigned long current) return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) { ioapic->type=1; ioapic->length=sizeof(acpi_madt_ioapic_t); ioapic->reserved=0x00; ioapic->gsi_base=gsi_base; - + ioapic->ioapic_id=id; ioapic->ioapic_addr=addr; - + return(ioapic->length); } @@ -168,7 +168,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, irqoverride->source=source; irqoverride->gsirq=gsirq; irqoverride->flags=flags; - + return(irqoverride->length); } @@ -177,29 +177,29 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, { lapic_nmi->type=4; lapic_nmi->length=sizeof(acpi_madt_lapic_nmi_t); - + lapic_nmi->flags=flags; lapic_nmi->processor_id=cpu; lapic_nmi->lint=lint; - + return(lapic_nmi->length); } void acpi_create_madt(acpi_madt_t *madt) { #define LOCAL_APIC_ADDR 0xfee00000ULL - + acpi_header_t *header=&(madt->header); unsigned long current=(unsigned long)madt+sizeof(acpi_madt_t); - + memset((void *)madt, 0, sizeof(acpi_madt_t)); - + /* fill out header fields */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_madt_t); header->revision = 1; @@ -207,10 +207,10 @@ void acpi_create_madt(acpi_madt_t *madt) madt->flags = 0x1; /* PCAT_COMPAT */ current = acpi_fill_madt(current); - + /* recalculate length */ header->length= current - (unsigned long)madt; - + header->checksum = acpi_checksum((void *)madt, header->length); } @@ -219,23 +219,23 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) acpi_header_t *header=&(mcfg->header); unsigned long current=(unsigned long)mcfg+sizeof(acpi_mcfg_t); - + memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); - + /* fill out header fields */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_mcfg_t); header->revision = 1; current = acpi_fill_mcfg(current); - + /* recalculate length */ header->length= current - (unsigned long)mcfg; - + header->checksum = acpi_checksum((void *)mcfg, header->length); } @@ -294,7 +294,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 mem->proximity_domain = node; - mem->flags = flags; + mem->flags = flags; return(mem->length); } @@ -356,15 +356,15 @@ void acpi_create_hpet(acpi_hpet_t *hpet) #define HPET_ADDR 0xfed00000ULL acpi_header_t *header=&(hpet->header); acpi_addr_t *addr=&(hpet->addr); - + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); - + /* fill out header fields */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_hpet_t); header->revision = 1; @@ -378,12 +378,12 @@ void acpi_create_hpet(acpi_hpet_t *hpet) hpet->id = 0x102282a0; /* AMD ? */ hpet->number = 0; hpet->min_tick = 4096; - + header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } void acpi_create_facs(acpi_facs_t *facs) { - + memset( (void *)facs,0, sizeof(acpi_facs_t)); memcpy(facs->signature, "FACS", 4); @@ -398,46 +398,46 @@ void acpi_create_facs(acpi_facs_t *facs) } void acpi_write_rsdt(acpi_rsdt_t *rsdt) -{ +{ acpi_header_t *header=&(rsdt->header); - + /* fill out header fields */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_rsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t)); } void acpi_write_xsdt(acpi_xsdt_t *xsdt) -{ +{ acpi_header_t *header=&(xsdt->header); - + /* fill out header fields */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_xsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } @@ -448,7 +448,7 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) memcpy(rsdp->oem_id, OEM_ID, 6); rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; - /* Some OSes expect an XSDT to be present for RSD PTR + /* Some OSes expect an XSDT to be present for RSD PTR * revisions >= 2. If we don't have an ACPI XSDT, force * ACPI 1.0 (and thus RSD PTR revision 0) */ @@ -547,7 +547,7 @@ void *acpi_find_wakeup_vector(void) printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; - + end = (char *) rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); diff --git a/src/arch/i386/boot/acpigen.c b/src/arch/i386/boot/acpigen.c index 3ed7a2f05d..2bd2ab5630 100644 --- a/src/arch/i386/boot/acpigen.c +++ b/src/arch/i386/boot/acpigen.c @@ -147,8 +147,8 @@ int acpigen_emit_stream(const char *data, int size) return size; } -/* The NameString are bit tricky, each element can be 4 chars, if - less its padded with underscore. Check 18.2.2 and 18.4 +/* The NameString are bit tricky, each element can be 4 chars, if + less its padded with underscore. Check 18.2.2 and 18.4 and 5.3 of ACPI specs 3.0 for details */ @@ -160,14 +160,14 @@ static int acpigen_emit_simple_namestring(const char *name) { len += acpigen_emit_stream(ud, 4 - i); break; } else { - len += acpigen_emit_byte(name[i]); + len += acpigen_emit_byte(name[i]); } } return len; } static int acpigen_emit_double_namestring(const char *name, int dotpos) { - int len = 0; + int len = 0; /* mark dual name prefix */ len += acpigen_emit_byte(0x2e); len += acpigen_emit_simple_namestring(name); @@ -177,7 +177,7 @@ static int acpigen_emit_double_namestring(const char *name, int dotpos) { static int acpigen_emit_multi_namestring(const char *name) { int len = 0, count = 0; - unsigned char *pathlen; + unsigned char *pathlen; /* mark multi name prefix */ len += acpigen_emit_byte(0x2f); len += acpigen_emit_byte(0x0); @@ -229,7 +229,7 @@ int acpigen_emit_namestring(const char *namepath) { if (dotcount == 0) { len += acpigen_emit_simple_namestring(namepath); - } else if (dotcount == 1) { + } else if (dotcount == 1) { len += acpigen_emit_double_namestring(namepath, dotpos); } else { len += acpigen_emit_multi_namestring(namepath); diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c index 895065e64a..d9cb02e776 100644 --- a/src/arch/i386/boot/boot.c +++ b/src/arch/i386/boot/boot.c @@ -63,9 +63,9 @@ int elf_check_arch(Elf_ehdr *ehdr) return ( ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) + (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) ); - + } void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) @@ -74,7 +74,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) unsigned long lb_start, lb_size; unsigned long adjust, adjusted_boot_notes; - elf_boot_notes.hdr.b_checksum = + elf_boot_notes.hdr.b_checksum = compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); lb_start = (unsigned long)&_ram_seg; @@ -82,7 +82,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) adjust = buffer + size - lb_start; adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; + adjusted_boot_notes += adjust; printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); @@ -91,7 +91,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); - + /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" @@ -172,7 +172,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) " popl %%edi\n\t" " popl %%esi\n\t" - :: + :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), #if CONFIG_MULTIBOOT diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c index b88ca1adba..bdf3b1bc6a 100644 --- a/src/arch/i386/boot/coreboot_table.c +++ b/src/arch/i386/boot/coreboot_table.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2003-2004 Eric Biederman * Copyright (C) 2005-2010 coresystems GmbH * @@ -71,7 +71,7 @@ static struct lb_record *lb_last_record(struct lb_header *header) #if 0 static struct lb_record *lb_next_record(struct lb_record *rec) { - rec = (void *)(((char *)rec) + rec->size); + rec = (void *)(((char *)rec) + rec->size); return rec; } #endif @@ -173,7 +173,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + + strlen(mainboard_vendor) + 1 + strlen(mainboard_part_number) + 1 + 3) & ~3; @@ -203,7 +203,7 @@ static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; cmos_checksum->location = LB_CKS_LOC * 8; cmos_checksum->type = CHECKSUM_PCBIOS; - + return cmos_checksum; } #endif @@ -320,7 +320,7 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) int entries; int i, j; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + /* Sort the lb memory ranges */ for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -357,17 +357,17 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) mem->map[i].size = pack_lb64(end - start); /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], + memmove(&mem->map[i + 1], &mem->map[i + 2], ((entries - i - 2) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* See if I can merge with the next entry as well */ - i -= 1; + i -= 1; } } } -static void lb_remove_memory_range(struct lb_memory *mem, +static void lb_remove_memory_range(struct lb_memory *mem, uint64_t start, uint64_t size) { uint64_t end; @@ -383,16 +383,16 @@ static void lb_remove_memory_range(struct lb_memory *mem, uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); if ((start <= map_start) && (end >= map_end)) { /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], + memmove(&mem->map[i], &mem->map[i + 1], ((entries - i - 1) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* Since the index will disappear revisit what will appear here */ - i -= 1; + i -= 1; } else if ((start > map_start) && (end < map_end)) { /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], + memmove(&mem->map[i + 1], &mem->map[i], ((entries - i) * sizeof(mem->map[0]))); mem->size += sizeof(mem->map[0]); entries += 1; @@ -430,7 +430,7 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) int entries; int i; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + printk(BIOS_DEBUG, "coreboot memory table:\n"); for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -448,14 +448,14 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) default: entry_type="UNKNOWN!"; break; } - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", + printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", i, entry_start, entry_start+entry_size-1, entry_type); - + } } -/* Routines to extract part so the coreboot table or +/* Routines to extract part so the coreboot table or * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. @@ -492,8 +492,8 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) extern uint64_t high_tables_base, high_tables_size; #endif -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { struct lb_header *head; @@ -509,7 +509,7 @@ unsigned long write_coreboot_table( printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", rom_table_end); - + head = lb_table_init(rom_table_end); rom_table_end = (unsigned long)head; printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); @@ -523,7 +523,7 @@ unsigned long write_coreboot_table( low_table_end = (unsigned long)head; } #endif - + printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned low_table_end &= ~0xfff; @@ -535,7 +535,7 @@ unsigned long write_coreboot_table( rom_table_end &= ~0xffff; printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_HAVE_OPTION_TABLE == 1) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ @@ -546,9 +546,9 @@ unsigned long write_coreboot_table( #endif /* Record where RAM is located */ mem = build_lb_mem(head); - + /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, + lb_add_memory_range(mem, LB_MEM_TABLE, low_table_start, low_table_end - low_table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ @@ -588,5 +588,5 @@ unsigned long write_coreboot_table( /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); - + } diff --git a/src/arch/i386/boot/mpspec.c b/src/arch/i386/boot/mpspec.c index 1beba873cc..47ad8ccb33 100644 --- a/src/arch/i386/boot/mpspec.c +++ b/src/arch/i386/boot/mpspec.c @@ -31,7 +31,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph { struct intel_mp_floating *mf; void *v; - + v = (void *)addr; mf = v; mf->mpf_signature[0] = '_'; @@ -106,7 +106,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -114,7 +114,7 @@ void smp_write_processors(struct mp_config_table *mc) cpu_feature_flags = result.edx; for(cpu = all_devices; cpu; cpu = cpu->next) { unsigned long cpu_flag; - if ((cpu->path.type != DEVICE_PATH_APIC) || + if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; @@ -126,7 +126,7 @@ void smp_write_processors(struct mp_config_table *mc) if (boot_apic_id == cpu->path.apic.apic_id) { cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; } - smp_write_processor(mc, + smp_write_processor(mc, cpu->path.apic.apic_id, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); @@ -146,7 +146,7 @@ void smp_write_bus(struct mp_config_table *mc, } void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr) { struct mpc_config_ioapic *mpc; diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c index 86a3500444..4873f6d751 100644 --- a/src/arch/i386/boot/pirq_routing.c +++ b/src/arch/i386/boot/pirq_routing.c @@ -26,7 +26,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr); - + sum = rt->checksum - sum; if (sum != rt->checksum) { @@ -72,9 +72,9 @@ static int verify_copy_pirq_routing_table(unsigned long addr) } } printk(BIOS_INFO, "done\n"); - + check_pirq_routing_table((struct irq_routing_table *)addr); - + return 0; } #endif diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c index 76a7bb21b1..6ee7c2c876 100644 --- a/src/arch/i386/boot/tables.c +++ b/src/arch/i386/boot/tables.c @@ -60,12 +60,12 @@ struct lb_memory *write_tables(void) printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - rom_table_start = 0xf0000; + rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. + * and the coreboot table use low_tables. */ low_table_start = 0; low_table_end = 0x500; @@ -126,7 +126,7 @@ struct lb_memory *write_tables(void) /* Write ACPI tables to F segment and high tables area */ /* Ok, this is a bit hacky still, because some day we want to have this - * completely dynamic. But right now we are setting fixed sizes. + * completely dynamic. But right now we are setting fixed sizes. * It's probably still better than the old high_table_base code because * now at least we know when we have an overflow in the area. * @@ -213,7 +213,7 @@ struct lb_memory *write_tables(void) write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); } - + post_code(0x9e); #if CONFIG_HAVE_ACPI_RESUME @@ -223,7 +223,7 @@ struct lb_memory *write_tables(void) */ cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64)); #endif - + // Remove before sending upstream cbmem_list(); diff --git a/src/arch/i386/boot/wakeup.S b/src/arch/i386/boot/wakeup.S index b348e95a71..a1df4d5597 100644 --- a/src/arch/i386/boot/wakeup.S +++ b/src/arch/i386/boot/wakeup.S @@ -68,11 +68,11 @@ __wakeup: * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld index 67c78cecbc..2e602205dd 100644 --- a/src/arch/i386/coreboot_ram.ld +++ b/src/arch/i386/coreboot_ram.ld @@ -59,7 +59,7 @@ SECTIONS . = ALIGN(4); _erodata = .; - } + } /* After the code we place initialized data (typically initialized * global variables). This gets copied into ram by startup code. * __data_start and __data_end shows where in ram this should be placed, @@ -113,11 +113,11 @@ SECTIONS /* Avoid running into 0xa0000-0xfffff */ _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB"); - /* The ram segment. This includes all memory used by the memory + /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. */ - _ram_seg = _text; + _ram_seg = _text; _eram_seg = _eheap; /* CONFIG_RAMTOP is the upper address of cached memory (among other diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h index ebab54ca42..9b1e1a5d9e 100644 --- a/src/arch/i386/include/arch/acpi.h +++ b/src/arch/i386/include/arch/acpi.h @@ -30,7 +30,7 @@ #if CONFIG_GENERATE_ACPI_TABLES==1 #include <stdint.h> - + #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" #define OEM_ID "CORE " diff --git a/src/arch/i386/include/arch/coreboot_tables.h b/src/arch/i386/include/arch/coreboot_tables.h index 91e6d6cbd5..3c9bf98f22 100644 --- a/src/arch/i386/include/arch/coreboot_tables.h +++ b/src/arch/i386/include/arch/coreboot_tables.h @@ -8,7 +8,7 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_memory_range(struct lb_memory *mem, +void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); /* Routines to extract part so the coreboot table or information diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h index 30b6cc300b..3e799f014d 100644 --- a/src/arch/i386/include/arch/cpu.h +++ b/src/arch/i386/include/arch/cpu.h @@ -102,7 +102,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_RISE 7 #define X86_VENDOR_TRANSMETA 8 #define X86_VENDOR_NSC 9 -#define X86_VENDOR_SIS 10 +#define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff #if !defined(__PRE_RAM__) @@ -129,8 +129,8 @@ static inline struct cpu_info *cpu_info(void) struct cpu_info *ci; __asm__("andl %%esp,%0; " "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) ); return ci; diff --git a/src/arch/i386/include/arch/io.h b/src/arch/i386/include/arch/io.h index 3a76579fbc..dd8d647380 100644 --- a/src/arch/i386/include/arch/io.h +++ b/src/arch/i386/include/arch/io.h @@ -82,7 +82,7 @@ static inline uint32_t inl(uint16_t port) static inline void outsb(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " + "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -91,7 +91,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count) static inline void outsw(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " + "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -100,7 +100,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count) static inline void outsl(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " + "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -110,7 +110,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insb " + "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -119,7 +119,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count) static inline void insw(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insw " + "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -128,7 +128,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count) static inline void insl(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insl " + "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h index 09133b5567..a35693519e 100644 --- a/src/arch/i386/include/arch/pciconf.h +++ b/src/arch/i386/include/arch/pciconf.h @@ -1,7 +1,7 @@ #ifndef PCI_CONF_REG_INDEX // These are defined in the PCI spec, and hence are theoretically -// inclusive of ANYTHING that uses a PCI bus. +// inclusive of ANYTHING that uses a PCI bus. #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc diff --git a/src/arch/i386/include/arch/registers.h b/src/arch/i386/include/arch/registers.h index 63aeec826b..bc1b681339 100644 --- a/src/arch/i386/include/arch/registers.h +++ b/src/arch/i386/include/arch/registers.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index d69d4541bc..f1466273d8 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -85,7 +85,7 @@ static inline int log2f(int value) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ @@ -303,7 +303,7 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - + for(; dev <=last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); diff --git a/src/arch/i386/include/arch/smp/atomic.h b/src/arch/i386/include/arch/smp/atomic.h index 7061461d33..18bbae27cb 100644 --- a/src/arch/i386/include/arch/smp/atomic.h +++ b/src/arch/i386/include/arch/smp/atomic.h @@ -18,29 +18,29 @@ typedef struct { volatile int counter; } atomic_t; /** * atomic_read - read atomic variable * @v: pointer of type atomic_t - * + * * Atomically reads the value of @v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value - * + * * Atomically sets the value of @v to @i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable * @v: pointer of type atomic_t - * + * * Atomically increments @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) { __asm__ __volatile__( @@ -52,10 +52,10 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) /** * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t - * + * * Atomically decrements @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v) { __asm__ __volatile__( diff --git a/src/arch/i386/include/arch/smp/mpspec.h b/src/arch/i386/include/arch/smp/mpspec.h index ab29f2a088..1645d3b38f 100644 --- a/src/arch/i386/include/arch/smp/mpspec.h +++ b/src/arch/i386/include/arch/smp/mpspec.h @@ -9,9 +9,9 @@ /* * This tag identifies where the SMP configuration - * information is. + * information is. */ - + #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') /* @@ -72,7 +72,7 @@ struct mpc_config_processor unsigned char mpc_cpuflag; #define MPC_CPU_ENABLED 1 /* Processor is available */ #define MPC_CPU_BOOTPROCESSOR 2 /* Processor is the BP */ - unsigned long mpc_cpufeature; + unsigned long mpc_cpufeature; #define MPC_CPU_STEPPING_MASK 0x0F #define MPC_CPU_MODEL_MASK 0xF0 #define MPC_CPU_FAMILY_MASK 0xF00 @@ -140,7 +140,7 @@ struct mpc_config_lintsrc unsigned short mpc_irqflag; unsigned char mpc_srcbusid; unsigned char mpc_srcbusirq; - unsigned char mpc_destapic; + unsigned char mpc_destapic; #define MP_APIC_ALL 0xFF unsigned char mpc_destapiclint; } __attribute__((packed)); @@ -211,7 +211,7 @@ struct mp_exten_compatibility_address_space { #define ADDRESS_RANGE_SUBTRACT 1 #define ADDRESS_RANGE_ADD 0 unsigned int mpe_range_list; -#define RANGE_LIST_IO_ISA 0 +#define RANGE_LIST_IO_ISA 0 /* X100 - X3FF * X500 - X7FF * X900 - XBFF @@ -243,7 +243,7 @@ void smp_write_processors(struct mp_config_table *mc); void smp_write_bus(struct mp_config_table *mc, unsigned char id, const char *bustype); void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr); void smp_write_intsrc(struct mp_config_table *mc, unsigned char irqtype, unsigned short irqflag, @@ -269,7 +269,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc, unsigned int range_list); unsigned char smp_compute_checksum(void *v, int len); void *smp_write_floating_table(unsigned long addr); -void *smp_write_floating_table_physaddr(unsigned long addr, +void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr); unsigned long write_smp_table(unsigned long addr); diff --git a/src/arch/i386/include/bitops.h b/src/arch/i386/include/bitops.h index fae2045b9a..9206465c77 100644 --- a/src/arch/i386/include/bitops.h +++ b/src/arch/i386/include/bitops.h @@ -15,6 +15,6 @@ static inline unsigned long log2(unsigned long x) "1:\n\t" : "=r" (r) : "r" (x)); return r; - + } #endif /* I386_BITOPS_H */ diff --git a/src/arch/i386/include/stdint.h b/src/arch/i386/include/stdint.h index a015a84b2a..b393cc10e0 100644 --- a/src/arch/i386/include/stdint.h +++ b/src/arch/i386/include/stdint.h @@ -9,7 +9,7 @@ /* Exact integral types */ typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef signed char int8_t; typedef unsigned short uint16_t; typedef signed short int16_t; @@ -24,7 +24,7 @@ typedef signed long long int64_t; /* Small types */ typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef signed char int_least8_t; typedef unsigned short uint_least16_t; typedef signed short int_least16_t; @@ -39,7 +39,7 @@ typedef signed long long int_least64_t; /* Fast Types */ typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef signed char int_fast8_t; typedef unsigned int uint_fast16_t; typedef signed int int_fast16_t; @@ -50,7 +50,7 @@ typedef signed int int_fast32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; typedef signed long long int_fast64_t; -#endif +#endif /* Types for `void *' pointers. */ typedef int intptr_t; diff --git a/src/arch/i386/init/bootblock_prologue.c b/src/arch/i386/init/bootblock_prologue.c index b07aec3524..25da7b769f 100644 --- a/src/arch/i386/init/bootblock_prologue.c +++ b/src/arch/i386/init/bootblock_prologue.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_prologue.inc b/src/arch/i386/init/crt0_prologue.inc index 225a003d8f..8947f20de3 100644 --- a/src/arch/i386/init/crt0_prologue.inc +++ b/src/arch/i386/init/crt0_prologue.inc @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_romcc_epilogue.inc b/src/arch/i386/init/crt0_romcc_epilogue.inc index 73107c913b..3bd1b36992 100644 --- a/src/arch/i386/init/crt0_romcc_epilogue.inc +++ b/src/arch/i386/init/crt0_romcc_epilogue.inc @@ -1,4 +1,4 @@ -/* +/* * Copyright 2002 Eric Biederman * * This file is free software; you can redistribute it and/or @@ -11,7 +11,7 @@ __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -19,7 +19,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/arch/i386/init/ldscript.ld b/src/arch/i386/init/ldscript.ld index e56f644034..149f048638 100644 --- a/src/arch/i386/init/ldscript.ld +++ b/src/arch/i386/init/ldscript.ld @@ -35,6 +35,6 @@ SECTIONS { *(.reset) . = 15 ; BYTE(0x00); - } + } } diff --git a/src/arch/i386/lib/cbfs_and_run.c b/src/arch/i386/lib/cbfs_and_run.c index a6f19e50ee..1b86f56371 100644 --- a/src/arch/i386/lib/cbfs_and_run.c +++ b/src/arch/i386/lib/cbfs_and_run.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c index 0e54b9a87d..3732ae296e 100644 --- a/src/arch/i386/lib/cpu.c +++ b/src/arch/i386/lib/cpu.c @@ -43,7 +43,7 @@ static int have_cpuid_p(void) * by the fact that they preserve the flags across the division of 5/2. * PII and PPro exhibit this behavior too, but they have cpuid available. */ - + /* * Perform the Cyrix 5/2 test. A Cyrix won't change * the flags, while other 486 chips will. @@ -68,11 +68,11 @@ static inline int test_cyrix_52div(void) * Detect a NexGen CPU running without BIOS hypercode new enough * to have CPUID. (Thanks to Herbert Oppmann) */ - + static int deep_magic_nexgen_probe(void) { int ret; - + __asm__ __volatile__ ( " movw $0x5555, %%ax\n" " xorw %%dx,%%dx\n" @@ -81,7 +81,7 @@ static int deep_magic_nexgen_probe(void) " movl $0, %%eax\n" " jnz 1f\n" " movl $1, %%eax\n" - "1:\n" + "1:\n" : "=a" (ret) : : "cx", "dx" ); return ret; } @@ -95,7 +95,7 @@ static struct { } x86_vendors[] = { { X86_VENDOR_INTEL, "GenuineIntel", }, { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, { X86_VENDOR_UMC, "UMC UMC UMC ", }, { X86_VENDOR_NEXGEN, "NexGenDriven", }, { X86_VENDOR_CENTAUR, "CentaurHauls", }, @@ -124,7 +124,7 @@ static const char *cpu_vendor_name(int vendor) const char *name; name = "<invalid cpu vendor>"; if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && - (x86_vendor_name[vendor] != 0)) + (x86_vendor_name[vendor] != 0)) { name = x86_vendor_name[vendor]; } @@ -173,7 +173,7 @@ static void identify_cpu(struct device *cpu) vendor_name[10] = (result.ecx >> 16) & 0xff; vendor_name[11] = (result.ecx >> 24) & 0xff; vendor_name[12] = '\0'; - + /* Intel-defined flags: level 0x00000001 */ if (cpuid_level >= 0x00000001) { cpu->device = cpuid_eax(0x00000001); @@ -200,7 +200,7 @@ static void set_cpu_ops(struct device *cpu) struct cpu_device_id *id; for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { if ((cpu->vendor == id->vendor) && - (cpu->device == id->device)) + (cpu->device == id->device)) { goto found; } @@ -221,7 +221,7 @@ void cpu_initialize(void) struct device *cpu; struct cpu_info *info; struct cpuinfo_x86 c; - + info = cpu_info(); printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); @@ -240,11 +240,11 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask); - + /* Lookup the cpu's operations */ set_cpu_ops(cpu); - if(!cpu->ops) { + if(!cpu->ops) { /* mask out the stepping and try again */ cpu->device -= c.x86_mask; set_cpu_ops(cpu); @@ -252,7 +252,7 @@ void cpu_initialize(void) if(!cpu->ops) die("Unknown cpu"); printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - + /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { diff --git a/src/arch/i386/lib/exception.c b/src/arch/i386/lib/exception.c index eb1df20e26..20917b6f40 100644 --- a/src/arch/i386/lib/exception.c +++ b/src/arch/i386/lib/exception.c @@ -4,7 +4,7 @@ #if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. - * At least NUM_REGBYTES*2 are needed for register packets + * At least NUM_REGBYTES*2 are needed for register packets */ #define BUFMAX 400 enum regnames { @@ -62,7 +62,7 @@ static uint32_t gdb_stub_registers[NUM_REGS]; #define GDB_SIGSOUND 42 /* Sound completed */ #define GDB_SIGSAK 43 /* Secure attention */ #define GDB_SIGPRIO 44 /* SIGPRIO */ - + #define GDB_SIG33 45 /* Real-time event 33 */ #define GDB_SIG34 46 /* Real-time event 34 */ #define GDB_SIG35 47 /* Real-time event 35 */ @@ -375,7 +375,7 @@ void x86_exception(struct eregs *info) if (info->vector < ARRAY_SIZE(exception_to_signal)) { signo = exception_to_signal[info->vector]; } - + /* reply to the host that an exception has occured */ out_buffer[0] = 'S'; out_buffer[1] = hexchars[(signo>>4) & 0xf]; @@ -412,7 +412,7 @@ void x86_exception(struct eregs *info) case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*ptr++ == ',') && parse_ulong(&ptr, &length)) { copy_to_hex(out_buffer, (void *)addr, length); @@ -423,7 +423,7 @@ void x86_exception(struct eregs *info) case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*(ptr++) == ',') && parse_ulong(&ptr, &length) && (*(ptr++) == ':')) { @@ -475,7 +475,7 @@ void x86_exception(struct eregs *info) put_packet(out_buffer); } #else /* !CONFIG_GDB_STUB */ - printk(BIOS_EMERG, + printk(BIOS_EMERG, "Unexpected Exception: %d @ %02x:%08x - Halting\n" "Code: %d eflags: %08x\n" "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc index 9f402f85b0..443dbad38a 100644 --- a/src/arch/i386/lib/id.inc +++ b/src/arch/i386/lib/id.inc @@ -2,9 +2,9 @@ .globl __id_start __id_start: -vendor: +vendor: .asciz CONFIG_MAINBOARD_VENDOR -part: +part: .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ diff --git a/src/arch/i386/lib/ioapic.c b/src/arch/i386/lib/ioapic.c index efc2ac52fc..d6616f5529 100644 --- a/src/arch/i386/lib/ioapic.c +++ b/src/arch/i386/lib/ioapic.c @@ -40,13 +40,13 @@ void clear_ioapic(u32 ioapic_base) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); /* Read the available number of interrupts */ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); low = DISABLED; high = NONE; @@ -70,15 +70,15 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", bsp_lapicid); if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); /* Set IOAPIC ID if it has been specified */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | (ioapic_id << 24)); } @@ -86,7 +86,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); // XXX this decision should probably be made elsewhere, and @@ -101,11 +101,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) /* For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif diff --git a/src/arch/i386/lib/pci_ops_auto.c b/src/arch/i386/lib/pci_ops_auto.c index 1f144381ee..92eedd30fb 100644 --- a/src/arch/i386/lib/pci_ops_auto.c +++ b/src/arch/i386/lib/pci_ops_auto.c @@ -33,7 +33,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID); if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) || ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) || - (vendor == PCI_VENDOR_ID_MOTOROLA))) { + (vendor == PCI_VENDOR_ID_MOTOROLA))) { return 1; } } @@ -54,8 +54,8 @@ static const struct pci_bus_operations *pci_check_direct(void) outb(0x01, 0xCFB); tmp = inl(0xCF8); outl(0x80000000, 0xCF8); - if ((inl(0xCF8) == 0x80000000) && - pci_sanity_check(&pci_cf8_conf1)) + if ((inl(0xCF8) == 0x80000000) && + pci_sanity_check(&pci_cf8_conf1)) { outl(tmp, 0xCF8); printk(BIOS_DEBUG, "PCI: Using configuration type 1\n"); diff --git a/src/arch/i386/lib/printk_init.c b/src/arch/i386/lib/printk_init.c index d3064046f7..f29ba667f1 100644 --- a/src/arch/i386/lib/printk_init.c +++ b/src/arch/i386/lib/printk_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/i386/lib/stages.c b/src/arch/i386/lib/stages.c index 0605abf49b..a6a232a04a 100644 --- a/src/arch/i386/lib/stages.c +++ b/src/arch/i386/lib/stages.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/llshell/console.inc b/src/arch/i386/llshell/console.inc index 394d5c4f68..84f62e3448 100644 --- a/src/arch/i386/llshell/console.inc +++ b/src/arch/i386/llshell/console.inc @@ -149,7 +149,7 @@ jmp console0 jz 11f ; \ __CONSOLE_INLINE_TX_AL ; \ jmp 10b ; \ -11: +11: #define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) @@ -234,7 +234,7 @@ jmp console0 #define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) /* uses: esp, ax, dx */ -console_tx_al: +console_tx_al: __CONSOLE_INLINE_TX_AL RETSP @@ -333,7 +333,7 @@ console_tx_string: cmp $0, %al jne 9f RETSP -9: +9: __CONSOLE_INLINE_TX_AL jmp console_tx_string diff --git a/src/arch/i386/llshell/llshell.inc b/src/arch/i386/llshell/llshell.inc index 6f8996717a..a66ac150b5 100644 --- a/src/arch/i386/llshell/llshell.inc +++ b/src/arch/i386/llshell/llshell.inc @@ -27,16 +27,16 @@ jmp llshell_out // Designed to be an interactive shell that operates with zero // system resources. For example at initial boot. -// to use, jump to label "low_level_shell" +// to use, jump to label "low_level_shell" // set %esp to the return address for exiting -#define UART_BASEADDR $0x3f8 +#define UART_BASEADDR $0x3f8 #define resultreg %esi #define subroutinereg %edi #define freqtime $2193 // 1.93 * freq #define timertime $6000 -.equ sys_IOPL, 110 +.equ sys_IOPL, 110 // .data // .text @@ -75,9 +75,9 @@ cmds: \r\nAll values in hex (0x prefixing ok) \ \r\n" -cr: +cr: .string "\r\n" -spaces: +spaces: .string " " // .globl _start @@ -187,7 +187,7 @@ jz wmemw cmp $0x00776d6c,%eax jz wmeml cmp $0x0000646d,%eax -jz dodmem +jz dodmem cmp $0x6d656d74,%eax jz memt // mem test cmp $0x00727374,%eax @@ -195,7 +195,7 @@ jz rst // reset cmp $0x00525354,%eax jz RST cmp $0x62656570,%eax -jz beep +jz beep cmp $0x0000646c,%eax jz dodl // download to mem <loc> <size> cmp $0x006a6d70,%eax @@ -203,7 +203,7 @@ jz jmpto // jump to location (eax holds return addr) cmp $0x62617564,%eax jz baud // change baudrate cmp $0x00696e74,%eax -jz doint // trigger an interrupt +jz doint // trigger an interrupt cmp $0x63616c6c,%eax jz callto // call assumes memory cmp $0x70757368,%eax @@ -270,7 +270,7 @@ processchar: cmp $0x3A,%al jl subnum cmp $0x47,%al -jl subcaps +jl subcaps //sublc: sub $0x57,%al jmp additupn @@ -370,7 +370,7 @@ jmp displaystring doneshow1: dec %cx cmp $0x0,%cx -jz exitdmem +jz exitdmem add $0x04,%ebx jmp dmemloop exitdmem: @@ -517,7 +517,7 @@ movl $int1a, subroutinereg jmp readnibbles int1a: mov resultreg,%eax -// need to lookup int table? +// need to lookup int table? // int %eax jmp readcommand @@ -560,7 +560,7 @@ jmp *subroutinereg displayhexlinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg @@ -602,7 +602,7 @@ jmp *subroutinereg displayasciilinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg diff --git a/src/arch/i386/llshell/pci.inc b/src/arch/i386/llshell/pci.inc index eb4d3c3845..7cb741008e 100644 --- a/src/arch/i386/llshell/pci.inc +++ b/src/arch/i386/llshell/pci.inc @@ -11,7 +11,7 @@ * * Notes: This routine is optimized for minimal register usage. * And the tricks it does cannot scale beyond writing a single byte. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the data byte @@ -52,7 +52,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -91,7 +91,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -118,7 +118,7 @@ - + /* * Macro: PCI_READ_CONFIG_BYTE * Arguments: %eax address to read from (includes bus, device, function, &offset) @@ -129,7 +129,7 @@ * Effects: reads a single byte from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -165,7 +165,7 @@ * Effects: reads a 2 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -201,7 +201,7 @@ * Effects: reads 4 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant diff --git a/src/arch/i386/llshell/ramtest.inc b/src/arch/i386/llshell/ramtest.inc index 910f01608f..c02cf451ec 100644 --- a/src/arch/i386/llshell/ramtest.inc +++ b/src/arch/i386/llshell/ramtest.inc @@ -6,7 +6,7 @@ jmp rt_skip #define RAMTEST 1 -#if RAMTEST +#if RAMTEST .section ".rom.data" rt_test: .string "Testing SDRAM : " @@ -16,7 +16,7 @@ rt_toomany: .string "Too many errors.\r\n" rt_done: .string "Done.\r\n" .previous #endif - + ramtest: #if RAMTEST mov %eax, %esi @@ -41,7 +41,7 @@ ramtest: /* Display address being filled */ /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ - + CONSOLE_INFO_TX_HEX32(%ebx) CONSOLE_INFO_TX_CHAR($'\r') 2: @@ -110,7 +110,7 @@ ramtest: sub $1, %ecx jz 5f jmp 3b -5: +5: CONSOLE_INFO_TX_STRING($rt_toomany) post_code(0xf1) jmp .Lhlt diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 686b09576f..061bffdad4 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -45,10 +45,10 @@ it with the version available from LANL. /** * @brief Main function of the RAM part of coreboot. * - * Coreboot is divided into Pre-RAM part and RAM part. - * + * Coreboot is divided into Pre-RAM part and RAM part. + * * Device Enumeration: - * In the dev_enumerate() phase, + * In the dev_enumerate() phase, */ void hardwaremain(int boot_complete); @@ -61,10 +61,10 @@ void hardwaremain(int boot_complete) /* console_init() MUST PRECEDE ALL printk()! */ console_init(); - + post_code(0x39); - printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", + printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); @@ -76,7 +76,7 @@ void hardwaremain(int boot_complete) } /* FIXME: Is there a better way to handle this? */ - init_timer(); + init_timer(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); diff --git a/src/console/Kconfig b/src/console/Kconfig index 86d75754cd..b9d6f69253 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -98,7 +98,7 @@ config USBDEBUG_DIRECT It also requires a USB2 controller which supports the EHCI Debug Port capability. Controllers which are known to work: - + * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) * 8086:24cd Intel ICH4/ICH4-M * 8086:24dd Intel ICH5 diff --git a/src/console/btext_console.c b/src/console/btext_console.c index b1b10e63cb..56d893e36e 100644 --- a/src/console/btext_console.c +++ b/src/console/btext_console.c @@ -62,8 +62,8 @@ u32 boot_text_mapped; boot_infos_t disp_bi; -#define BTEXT -#define BTDATA +#define BTEXT +#define BTDATA /* This function will enable the early boot text when doing OF booting. This @@ -100,7 +100,7 @@ btext_setup_display(u32 width, u32 height, u32 depth, u32 pitch, * changes. */ -void +void map_boot_text(void) { #if 0 @@ -111,9 +111,9 @@ map_boot_text(void) return; base = ((unsigned long) bi->dispDeviceBase) & 0xFFFFF000UL; offset = ((unsigned long) bi->dispDeviceBase) - base; - size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset + size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset + bi->dispDeviceRect[0]; - bi->logicalDisplayBase = ioremap(base,0x800000 ); + bi->logicalDisplayBase = ioremap(base,0x800000 ); if (bi->logicalDisplayBase == 0) return; // bi->logicalDisplayBase += offset; @@ -360,7 +360,7 @@ static u32 expand_bits_8[16] BTDATA = { 0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff #else #error FIXME: No endianness?? -#endif +#endif }; #if 0 static const u32 expand_bits_16[4] BTDATA = { diff --git a/src/console/console.c b/src/console/console.c index 327ad19017..016c3b9664 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -1,5 +1,5 @@ /* - * Bootstrap code for the INTEL + * Bootstrap code for the INTEL */ #include <console/console.h> @@ -18,7 +18,7 @@ void console_init(void) struct console_driver *driver; if(get_option(&console_loglevel, "debug_level")) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - + for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -38,7 +38,7 @@ void console_tx_flush(void) { struct console_driver *driver; for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->tx_flush) + if (!driver->tx_flush) continue; driver->tx_flush(); } @@ -99,7 +99,7 @@ void __attribute__((noreturn)) die(const char *msg) void console_init(void) { - static const char console_test[] = + static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION COREBOOT_EXTRA_VERSION diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c index 3b6c744503..a76791d542 100644 --- a/src/console/logbuf_console.c +++ b/src/console/logbuf_console.c @@ -2,7 +2,7 @@ #define LOGBUF_SIZE 1024 -// KEEP THIS GLOBAL. +// KEEP THIS GLOBAL. // I need the address so I can watch it with the ARIUM hardware. RGM. char logbuf[LOGBUF_SIZE]; int logbuf_offset = 0; diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index fd71ff7dc2..20deaa72e3 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -38,17 +38,17 @@ static void ttyS0_init(void) uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS); } -static void ttyS0_tx_byte(unsigned char data) +static void ttyS0_tx_byte(unsigned char data) { uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } -static unsigned char ttyS0_rx_byte(void) +static unsigned char ttyS0_rx_byte(void) { return uart8250_rx_byte(CONFIG_TTYS0_BASE); } -static int ttyS0_tst_byte(void) +static int ttyS0_tst_byte(void) { return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); } diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 7407c420ab..4a745233b9 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 3c75e3d704..944fd5b96f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -30,7 +30,7 @@ static int skip_atoi(const char **s) #define SPECIAL 32 /* 0x */ #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -static int number(void (*tx_byte)(unsigned char byte), +static int number(void (*tx_byte)(unsigned char byte), unsigned long long num, int base, int size, int precision, int type) { char c,sign,tmp[66]; @@ -112,7 +112,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int precision; /* min. # of digits for integers; max number of chars for from string */ int qualifier; /* 'h', 'l', or 'L' for integer fields */ - + int count; for (count=0; *fmt ; ++fmt) { @@ -120,7 +120,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args tx_byte(*fmt), count++; continue; } - + /* process flags */ flags = 0; repeat: @@ -132,7 +132,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args case '#': flags |= SPECIAL; goto repeat; case '0': flags |= ZEROPAD; goto repeat; } - + /* get field width */ field_width = -1; if (is_digit(*fmt)) @@ -150,7 +150,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args /* get the precision */ precision = -1; if (*fmt == '.') { - ++fmt; + ++fmt; if (is_digit(*fmt)) precision = skip_atoi(&fmt); else if (*fmt == '*') { diff --git a/src/cpu/amd/dualcore/Makefile.inc b/src/cpu/amd/dualcore/Makefile.inc index ee2d93c928..8b6d688300 100644 --- a/src/cpu/amd/dualcore/Makefile.inc +++ b/src/cpu/amd/dualcore/Makefile.inc @@ -1,2 +1,2 @@ -# This is a leaf Makefile, no conditionals. If it is included it will be used. +# This is a leaf Makefile, no conditionals. If it is included it will be used. obj-y += amd_sibling.o diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 28a813c6a5..af96265d6c 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -27,12 +27,12 @@ static int get_max_siblings(int nodes) for(nodeid=0; nodeid<nodes; nodeid++){ int j; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3)); - j = (pci_read_config32(dev, 0xe8) >> 12) & 3; + j = (pci_read_config32(dev, 0xe8) >> 12) & 3; if(siblings < j) { siblings = j; } } - + return siblings; } @@ -47,7 +47,7 @@ static void enable_apic_ext_id(int nodes) dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); val |= (1<<17)|(1<<18); - pci_write_config32(dev, 0x68, val); + pci_write_config32(dev, 0x68, val); } } @@ -70,9 +70,9 @@ unsigned get_apicid_base(unsigned ioapic_num) siblings = get_max_siblings(nodes); if(bsp_apic_id > 0) { // io apic could start from 0 - return 0; + return 0; } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 - return 1; + return 1; } nb_cfg_54 = read_nb_cfg_54(); @@ -100,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num) //4:10 for two way 8:12 for four way 16:16 for eight way //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; + apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; } else { @@ -112,7 +112,7 @@ unsigned get_apicid_base(unsigned ioapic_num) printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n"); enable_apic_ext_id(nodes); } - + return apicid_base; } @@ -145,7 +145,7 @@ void amd_sibling_init(device_t cpu) siblings); #endif - nb_cfg_54 = read_nb_cfg_54(); + nb_cfg_54 = read_nb_cfg_54(); #if 1 id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set @@ -159,7 +159,7 @@ void amd_sibling_init(device_t cpu) return; } #endif - + /* I am the primary cpu start up my siblings */ for(i = 1; i <= siblings; i++) { @@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu) new->path.apic.core_id = i; #if 1 - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", cpu->path.apic.apic_id, new->path.apic.apic_id); #endif diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index a2b180b2b6..9a1a9c53d4 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void) return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +static inline unsigned get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } @@ -22,7 +22,7 @@ static inline unsigned get_initial_apicid(void) //called by amd_siblings too #define CORE_ID_BIT 1 #define NODE_ID_BIT 3 -struct node_core_id get_node_core_id(unsigned nb_cfg_54) +struct node_core_id get_node_core_id(unsigned nb_cfg_54) { struct node_core_id id; // get the apicid via cpuid(1) ebx[27:24] @@ -31,8 +31,8 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); id.coreid &= ((1<<CORE_ID_BIT)-1); - } - else + } + else { // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index d0beb04c98..db3debce2e 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,4 +1,4 @@ -# no conditionals here. If you include this file from a socket, then you get all the binaries. +# no conditionals here. If you include this file from a socket, then you get all the binaries. driver-y += model_10xxx_init.o obj-y += update_microcode.o obj-y += apic_timer.o diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000095.h b/src/cpu/amd/model_10xxx/mc_patch_01000095.h index 1227f310f1..bfb2e107f7 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000095.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000095.h @@ -112,7 +112,7 @@ 0x0f, 0xe0, 0xdf, 0xf0, 0x23, 0x03, 0x00, 0x8e, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, - + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 5a19547b4d..992c957913 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -134,12 +134,12 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100f22 }, { X86_VENDOR_AMD, 0x100f23 }, { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ - { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ - { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ - { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ - { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ - { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ - { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ + { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ + { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ + { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ + { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ + { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { 0, 0 }, }; diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index ea3088b46a..d7490e8fa9 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,4 +1,4 @@ -# no conditionals here. If you include this file from a socket, then you get all the binaries. +# no conditionals here. If you include this file from a socket, then you get all the binaries. driver-y += model_fxx_init.o obj-y += apic_timer.o obj-y += model_fxx_update_microcode.o diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c index 8eeb32fee9..6eb99a4eba 100644 --- a/src/cpu/amd/model_fxx/apic_timer.c +++ b/src/cpu/amd/model_fxx/apic_timer.c @@ -25,5 +25,5 @@ void udelay(unsigned usecs) do { value = lapic_read(LAPIC_TMCCT); } while((start - value) < ticks); - + } diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index edc7ac909c..bfbc93d577 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -424,7 +424,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx) { - /* FIXME: need to check the change path to verify if it is reachable + /* FIXME: need to check the change path to verify if it is reachable * when common fid is small than 1.6G */ if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) { return fidvid; @@ -549,7 +549,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* let all ap trains to state 1 */ lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1); - /* calculate the common max fid/vid that could be used for + /* calculate the common max fid/vid that could be used for * all APs and BSP */ #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 ap_apicidx.num = 0; diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h index f102d37d0f..980572439f 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_c.h +++ b/src/cpu/amd/model_fxx/microcode_rev_c.h @@ -95,7 +95,7 @@ 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/microcode_rev_d.h b/src/cpu/amd/model_fxx/microcode_rev_d.h index 7fc0666de6..61a510c2b2 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_d.h +++ b/src/cpu/amd/model_fxx/microcode_rev_d.h @@ -94,7 +94,7 @@ 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/microcode_rev_e.h b/src/cpu/amd/model_fxx/microcode_rev_e.h index 8d9a5813d4..7cdeed0016 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_e.h +++ b/src/cpu/amd/model_fxx/microcode_rev_e.h @@ -95,7 +95,7 @@ 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 68a2cea070..976168102b 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -94,7 +94,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { #endif #if CONFIG_K8_REV_F_SUPPORT == 1 - + #endif }; @@ -102,7 +102,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { unsigned new_id; int i; - + new_id = 0; for(i=0; i<sizeof(id_mapping_table); i+=2 ) { @@ -112,7 +112,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { } } - return new_id; + return new_id; } diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 4d86467632..8465e3ce34 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -77,7 +77,7 @@ static const char *processor_names[]={ /* 0x24 */ "AMD Athlon(tm) 64 FX-ZZ Processor", /* 0x25 */ NULL, /* 0x26 */ "AMD Sempron(tm) Processor TT00+", - /* 0x27-0x28 */ NULL, NULL, + /* 0x27-0x28 */ NULL, NULL, /* 0x29 */ "Dual Core AMD Opteron(tm) Processor 1RR SE", /* 0x2A */ "Dual Core AMD Opteron(tm) Processor 2RR SE", /* 0x2B */ "Dual Core AMD Opteron(tm) Processor 8RR SE", @@ -404,13 +404,13 @@ int init_processor_name(void) memset(program_string, 0, 48); strcpy(program_string, processor_name_string); - + /* Now create a model number - See Table 4. Model Number Calculation - * in the Revision Guide. NOTE: #6, EE was changed to VV because + * in the Revision Guide. NOTE: #6, EE was changed to VV because * otherwise it clashes with the brand names. */ - - for (i=0; i<47; i++) { // 48 -1 + + for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { #if CONFIG_K8_REV_F_SUPPORT == 0 @@ -430,11 +430,11 @@ int init_processor_name(void) case 'Y': ModelNumber = 29 + NN; break; #endif } - + if(ModelNumber && ModelNumber < 100) { // No idea what to do with RR=100. According // to the revision guide this is possible. - // + // // --> "AMD Opteron(tm) Processor 8100"? program_string[i]=(ModelNumber/10)+'0'; program_string[i+1]=(ModelNumber%10)+'0'; @@ -442,7 +442,7 @@ int init_processor_name(void) } } } - + printk(BIOS_DEBUG, "CPU model %s\n", program_string); for (i=0; i<6; i++) { diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c index 82570f5b0a..f900661959 100644 --- a/src/cpu/amd/model_gx2/cpubug.c +++ b/src/cpu/amd/model_gx2/cpubug.c @@ -50,8 +50,8 @@ pcideadlock(void) msr_t msr; /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); @@ -61,14 +61,14 @@ pcideadlock(void) wrmsr(CPU_DM_CONFIG0, msr); /* interlock instruction fetches to WS regions with data accesses. - * This prevents an instruction fetch from going out to PCI if the + * This prevents an instruction fetch from going out to PCI if the * data side is about to make a request. */ msr = rdmsr(CPU_IM_CONFIG); msr.lo |= IM_CONFIG_LOWER_QWT_SET; wrmsr(CPU_IM_CONFIG, msr); - - /* write serialize memory hole to PCI. Need to unWS when something is + + /* write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; @@ -78,7 +78,7 @@ pcideadlock(void) wrmsr( CPU_RCONF_E0_FF, msr); } -/**************************************************************************** +/**************************************************************************** * * CPUbug784 * @@ -176,7 +176,7 @@ eng2900(void) wrmsr(0x3003, msr); /* change this value to zero if you need to disable this BTB SWAPSiF. */ - if (1) { + if (1) { /* Disable enable_actions in DIAGCTL while setting up GLCP */ msr.hi = 0; @@ -192,16 +192,16 @@ eng2900(void) msr.lo = 2; wrmsr(MSR_GLCP + 0x0016, msr); - /* The code below sets up the CPU to stall for 4 GeodeLink - * clocks when CPU is snooped. Because setting XSTATE to 0 - * overrides any other XSTATE action, the code will always - * stall for 4 GeodeLink clocks after a snoop request goes - * away even if it occured a clock or two later than a - * different snoop; the stall signal will never 'glitch high' + /* The code below sets up the CPU to stall for 4 GeodeLink + * clocks when CPU is snooped. Because setting XSTATE to 0 + * overrides any other XSTATE action, the code will always + * stall for 4 GeodeLink clocks after a snoop request goes + * away even if it occured a clock or two later than a + * different snoop; the stall signal will never 'glitch high' * for only one or two CPU clocks with this code. */ - /* Send mb0 port 3 requests to upper GeodeLink diag bits + /* Send mb0 port 3 requests to upper GeodeLink diag bits [63:32] */ msr.hi = 0; msr.lo = 0x80338041; @@ -222,25 +222,25 @@ eng2900(void) msr.lo = 0; wrmsr(MSR_GLCP + 0x004D, msr); - /* Writing action number 13: XSTATE=0 to occur when CPU is + /* Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled */ msr.hi = 0; msr.lo = 0x00400000; wrmsr(MSR_GLCP + 0x0075, msr); - /* Writing action number 11: inc XSTATE every GeodeLink clock + /* Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle */ msr.hi = 0; msr.lo = 0x30000; wrmsr(MSR_GLCP + 0x0073, msr); - /* Writing action number 5: STALL_CPU_PIPE when exitting idle + /* Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state */ msr.hi = 0; msr.lo = 0x00430000; wrmsr(MSR_GLCP + 0x006D, msr); - /* Writing DIAGCTL Register to enable the stall action and to + /* Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits. */ msr.hi = 0; msr.lo = 0x80004000; @@ -338,7 +338,7 @@ static void bug118339(void) /***/ /****************************************************************************/ static void disablememoryreadorder(void) -{ +{ msr_t msr; msr = rdmsr(MC_CF8F_DATA); @@ -365,7 +365,7 @@ cpubug(void) case 0x20: pcideadlock(); eng1398(); - /* cs 5530 bug; ignore + /* cs 5530 bug; ignore bug752(); */ break; @@ -376,7 +376,7 @@ cpubug(void) bug118339(); break; case 0x22: - case 0x30: + case 0x30: break; default: printk(BIOS_ERR, "unknown rev %x, bailing\n", rev); diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c index 5e786910c5..3cb3cf1a58 100644 --- a/src/cpu/amd/model_gx2/cpureginit.c +++ b/src/cpu/amd/model_gx2/cpureginit.c @@ -18,7 +18,7 @@ BIST(void){ msr = rdmsr(msrnum); msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; wrmsr(msrnum, msr); - + msr.lo = 0x00000003F; msr.hi = 0x000000000; msrnum = CPU_DM_BIST; @@ -29,7 +29,7 @@ BIST(void){ msr.lo &= 0x0F3FF0000; if (msr.lo != 0xfeff0000) goto BISTFail; - + msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET; @@ -89,58 +89,58 @@ cpuRegInit (void){ msr.hi = 0; msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET; wrmsr(msrnum, msr); - + /* Set up GLCP to grab BTM data.*/ msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/ msr.hi = 0x0; msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/ - + /* ;Turn off debug clock*/ msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msr.lo = 0x00; /* No clock*/ msr.hi = 0x00; wrmsr(msrnum, msr); - + /* ;Set debug clock to CPU*/ msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msr.lo = 0x01; /* CPU CLOCK*/ msr.hi = 0x00; wrmsr(msrnum, msr); - + /* ;Set fifo ctl to BTM bits wide*/ msrnum = 0x04C00005E; /* FIFO_CTL*/ msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/ wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/ /* Bit [19] sets it up in slow data mode.*/ - + /* ;enable fifo loading - BTM sizing will constrain*/ /* ; only valid BTM packets to load - this action should always be on*/ - + msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/ msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/ msr.hi = 0x000000000; /* */ wrmsr(msrnum, msr); - + /* ;start storing diag data in the fifo*/ msrnum = 0x04C00005F; /* DIAG CTL*/ msr.lo = 0x080000000; /* enable actions*/ msr.hi = 0x000000000; wrmsr(msrnum, msr); - + /* Set up delay on data lines, so that the hold time*/ /* is 1 ns.*/ msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/ msr.lo = 0x082b5ad68; msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/ wrmsr(msrnum, msr); - + /* Set up DF to output diag information on DF pins.*/ msrnum = DF_GLD_MSR_MASTER_CONF; msr.lo = 0x0220; msr.hi = 0; wrmsr(msrnum, msr); - + msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/ msr.hi = 0x0; msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/ @@ -237,7 +237,7 @@ cpuRegInit (void){ /* */ /* This code disables the data cache. Don't execute this * unless you're testing something. - */ + */ /* Allow NVRam to override DM Setup*/ /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/ { @@ -249,7 +249,7 @@ cpuRegInit (void){ } /* This code disables the instruction cache. Don't execute * this unless you're testing something. - */ + */ /* Allow NVRam to override IM Setup*/ /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/ { diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c index 203d63b81e..e3b6e511ee 100644 --- a/src/cpu/amd/model_lx/cpubug.c +++ b/src/cpu/amd/model_lx/cpubug.c @@ -44,15 +44,15 @@ static void pcideadlock(void) msr_t msr; /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr); - /* write serialize memory hole to PCI. Need to unWS when something is + /* write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c index 492ee8fac0..62fa973a8c 100644 --- a/src/cpu/amd/model_lx/cpureginit.c +++ b/src/cpu/amd/model_lx/cpureginit.c @@ -248,8 +248,8 @@ void cpuRegInit(void) msr.hi |= ARB_UPPER_QUACK_EN_SET; wrmsr(msrnum, msr); - /* GLIU port active enable, limit south pole masters - * (AES and PCI) to one outstanding transaction. + /* GLIU port active enable, limit south pole masters + * (AES and PCI) to one outstanding transaction. */ print_debug(" GLIU port active enable\n"); msrnum = GLIU1_PORT_ACTIVE; diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index c7b45470e6..53c0a851dc 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -24,7 +24,7 @@ struct msrinit { msr_t msr; }; -static const struct msrinit msr_table[] = +static const struct msrinit msr_table[] = { {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. * Rom Properties: Write Serialize, WriteProtect. @@ -35,7 +35,7 @@ static const struct msrinit msr_table[] = {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ - + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index d5e8338cad..c113f3f8fa 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -5,7 +5,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -static unsigned long resk(uint64_t value) +static unsigned long resk(uint64_t value) { unsigned long resultk; if (value < (1ULL << 42)) { @@ -98,7 +98,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n", start_mtrr, last_mtrr); set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM); - + } void amd_setup_mtrrs(void) @@ -118,7 +118,7 @@ void amd_setup_mtrrs(void) printk(BIOS_DEBUG, "\n"); /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", + printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", 0, NUM_FIXED_RANGES); set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); @@ -162,7 +162,7 @@ void amd_setup_mtrrs(void) wrmsr(i, msr); } - /* Enable Variable Mtrrs + /* Enable Variable Mtrrs * Enable the RdMem and WrMem bits in the fixed mtrrs. * Disable access to the RdMem and WrMem in the fixed mtrr. */ diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index c56117485a..e6232a8eb4 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -65,13 +65,13 @@ void setupsc520(void) /* do this to see if MMCR will start acting right. we suspect * you have to do SOMETHING to get things going. I'm really - * starting to hate this processor. + * starting to hate this processor. */ - - /* no, that did not help. I wonder what will? + + /* no, that did not help. I wonder what will? * outl(0x800df0cb, 0xfffc); */ - + /* well, this is special! You have to do SHORT writes to the * locations, even though they are CHAR in size and CHAR aligned * and technically, a SHORT write will result in -- yoo ha! -- @@ -80,7 +80,7 @@ void setupsc520(void) * it now reliably comes up after power cycle with printk. Ah yi * yi. */ - + /* turn off the write buffer*/ /* per the note above, make this a short? Let's try it. */ sp = (unsigned short *)0xfffef040; @@ -92,7 +92,7 @@ void setupsc520(void) /* moved to romstage.c by Stepan, Ron says: */ /* NOTE: move this to mainboard.c ASAP */ setup_pars(); - + /* CPCSF register */ sp = (unsigned short *)0xfffefc24; *sp = 0xfe; @@ -120,7 +120,7 @@ void setupsc520(void) /*set the GP RD offset */ sp = (unsigned short *)0xfffefc0c; *sp = 0x00001; - /*set the GP WR pulse width*/ + /*set the GP WR pulse width*/ sp = (unsigned short *)0xfffefc0d; *sp = 0x00003; /*set the GP WR offset*/ @@ -164,19 +164,19 @@ void setupsc520(void) /*; set the interrupt mapping registers.*/ cp = (unsigned char *)0x0fffefd20; *cp = 0x01; - + cp = (unsigned char *)0x0fffefd28; *cp = 0x0c; - + cp = (unsigned char *)0x0fffefd29; *cp = 0x0b; - + cp = (unsigned char *)0x0fffefd30; *cp = 0x07; - + cp = (unsigned char *)0x0fffefd43; *cp = 0x03; - + cp = (unsigned char *)0x0fffefd51; *cp = 0x02; #endif @@ -186,8 +186,8 @@ void setupsc520(void) outl(0x08000683c, 0xcf8); outl(0xc, 0xcfc); /* set the interrupt line */ - - /* Set the SC520 PCI host bridge to target mode to + + /* Set the SC520 PCI host bridge to target mode to * allow external bus mastering events */ /* index the status command register on device 0*/ @@ -195,7 +195,7 @@ void setupsc520(void) outl(0x2, 0xcfc); /*set the memory access enable bit*/ OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */ } - + /* * @@ -228,7 +228,7 @@ void setupsc520(void) #define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/ #define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/ -void +void dummy_write(void){ volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ; *ptr = 0; @@ -247,16 +247,16 @@ static void dumpram(void){ print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n"); } -/* there is a lot of silliness in the amd code, and it is - * causing romcc real headaches, so we're going to be be a little +/* there is a lot of silliness in the amd code, and it is + * causing romcc real headaches, so we're going to be be a little * less silly. - * so, the order of ops is: + * so, the order of ops is: * for i in 3 to 0 - * see if bank is there. + * see if bank is there. * if we can write a word, and read it back, to hell with paranoia - * the bank is there. So write the magic byte, read it back, and - * use that to get size, etc. Try to keep things very simple, - * so people can actually follow the damned code. + * the bank is there. So write the magic byte, read it back, and + * use that to get size, etc. Try to keep things very simple, + * so people can actually follow the damned code. */ /* cache is assumed to be disabled */ @@ -273,14 +273,14 @@ int sizemem(void) /* no ecc interrupts of any kind. */ *eccctl = 0; /* Set SDRAM timing for slowest speed. */ - *drcmctl = 0x1e; + *drcmctl = 0x1e; /* setup dram register for all banks * with max cols and max banks * this is the oldest trick in the book. You are going to set up for max rows - * and cols, then do a write, then see if the data is wrapped to low memory. - * you can actually tell by which data gets to which low memory, - * exactly how many rows and cols you have. + * and cols, then do a write, then see if the data is wrapped to low memory. + * you can actually tell by which data gets to which low memory, + * exactly how many rows and cols you have. */ *drccfg=0xbbbb; @@ -339,24 +339,24 @@ int sizemem(void) *lp = 0xdeadbeef; print_err("assigned l ... \n"); if (*lp != 0xdeadbeef) { - print_err(" no memory at bank "); - // print_err_hex8(bank); + print_err(" no memory at bank "); + // print_err_hex8(bank); // print_err(" value "); print_err_hex32(*lp); - print_err("\n"); + print_err("\n"); // continue; } *drcctl = 2; dummy_write(); *drccfg = *drccfg >> 4; l = *drcbendadr; - l >>= 8; + l >>= 8; *drcbendadr = l; print_err("loop around\n"); *drcctl = 0; dummy_write(); } #if 0 - /* enable last bank and setup ending address + /* enable last bank and setup ending address * register for max ram in last bank */ *drcbendadr=0x0ff000000; @@ -410,10 +410,10 @@ int sizemem(void) bank = 3; - /* this is really ugly, it is right from assembly code. + /* this is really ugly, it is right from assembly code. * we need to clean it up later */ - + start: /* write col 11 wrap adr */ COL11_ADR=COL11_DATA; @@ -519,7 +519,7 @@ print_err("4b\n"); print_err("cols"); print_err_hex32(cols); print_err("\n"); cols -= COL08_DATA; - /* cols now is in the range of 0 1 2 3 ... + /* cols now is in the range of 0 1 2 3 ... */ i = cols&3; // i = cols + rows; @@ -533,22 +533,22 @@ print_err("4b\n"); /* what a fookin' mess this is */ if(banks==4) i+=8; /* <-- i holds merged value */ - /* i now has the col width in bits 0-1 and the bank count (2 or 4) + /* i now has the col width in bits 0-1 and the bank count (2 or 4) * in bit 3. - * this is the format for the drccfg register + * this is the format for the drccfg register */ - + /* fix ending addr mask*/ /*FIXME*/ /* let's just go with this to start ... see if we can get ANYWHERE */ /* need to get end addr. Need to do it with the bank in mind. */ /* - al = 3; + al = 3; al -= i&3; *drcbendaddr = rows >> al; - print_err("computed ending_adr = "); print_err_hex8(ending_adr); + print_err("computed ending_adr = "); print_err_hex8(ending_adr); print_err("\n"); - + */ bad_reinit: /* issue all banks recharge */ @@ -557,7 +557,7 @@ bad_reinit: /* update ending address register */ // *drcbendadr = ending_adr; - + /* update config register */ *drccfg &= ~(0xff << bank*4); if (ending_adr) @@ -579,11 +579,11 @@ bad_reinit: *drcctl=0x18; dummy_write(); return bank; - + bad_ram: print_info("bad ram!\n"); - /* you are here because the read-after-write failed, - * in most cases because: no ram in that bank! + /* you are here because the read-after-write failed, + * in most cases because: no ram in that bank! * set badbank to 1 and go to reinit */ ending_adr = 0; @@ -591,7 +591,7 @@ bad_ram: while(1) print_err("DONE NEXTBANK\n"); #endif -} +} /* note: based on AMD code*/ /* This code is known to work on the digital logic board and on the technologic @@ -600,7 +600,7 @@ bad_ram: int staticmem(void) { volatile unsigned long *zero = (unsigned long *) CACHELINESZ; - + /* set up 0x18 .. **/ *drcbendadr = 0x88; *drcmctl = 0x1e; @@ -609,7 +609,7 @@ int staticmem(void) *drcctl = 0x1; /* do the dummy write */ *zero = 0; - + /* precharge */ *drcctl = 2; *zero = 0; @@ -625,7 +625,7 @@ int staticmem(void) *drcctl = 3; *zero = 0; print_debug("DONE the load mode reg\n"); - + /* normal mode */ *drcctl = 0x0; *zero = 0; @@ -634,7 +634,7 @@ int staticmem(void) *zero = 0; print_debug("DONE the normal\n"); *zero = 0xdeadbeef; - if (*zero != 0xdeadbeef) + if (*zero != 0xdeadbeef) print_debug("NO LUCK\n"); else print_debug("did a store and load ...\n"); diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index e867fae3d7..4c93ebd295 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -16,10 +16,10 @@ #include "chip.h" /* - * set up basic things ... - * PAR should NOT go here, as it might change with the mainboard. + * set up basic things ... + * PAR should NOT go here, as it might change with the mainboard. */ -static void cpu_init(device_t dev) +static void cpu_init(device_t dev) { unsigned long *l = (unsigned long *) 0xfffef088; int i; @@ -30,9 +30,9 @@ static void cpu_init(device_t dev) } -/* Ollie says: make a northbridge/amd/sc520. Ron sez: - * there is no real northbridge, keep it here in cpu. - * Ron wins, he's writing the code. +/* Ollie says: make a northbridge/amd/sc520. Ron sez: + * there is no real northbridge, keep it here in cpu. + * Ron wins, he's writing the code. */ static void sc520_enable_resources(struct device *dev) { unsigned char command; @@ -141,16 +141,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); @@ -245,5 +245,5 @@ static void enable_dev(struct device *dev) struct chip_operations cpu_amd_sc520_ops = { CHIP_NAME("AMD Elan SC520 CPU") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 04c4d9ff58..870490c07d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other cpu files are included. # # Therefore: ONLY include Makefile.inc from socket directories! diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index f6a7e12e0d..41f3ce5b4d 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -305,11 +305,11 @@ lout: pushl %eax /* bist */ call main - /* + /* FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. It is only needed if we want to go back */ - + /* We don't need cache as ram for now on */ /* disable cache */ movl %cr0, %eax @@ -396,7 +396,7 @@ lout: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -404,7 +404,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 5e77a765a8..823d77c3a3 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -43,7 +43,7 @@ void intel_sibling_init(device_t cpu) } return; } - + /* I am the primary cpu start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; @@ -61,7 +61,7 @@ void intel_sibling_init(device_t cpu) } #if 1 - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", cpu->path.apic.apic_id, new->path.apic.apic_id); #endif @@ -72,6 +72,6 @@ void intel_sibling_init(device_t cpu) new->path.apic.apic_id); } } - + } diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 22c3a11503..93d2a687fb 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -59,7 +59,7 @@ void intel_update_microcode(const void *microcode_updates) const struct microcode *m; const char *c; msr_t msr; - + /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index fc20c6047f..8197898847 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -40,7 +40,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -77,7 +77,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -197,7 +197,7 @@ static void configure_pic_thermal_sensors(void) #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif - + static void model_1067x_init(device_t cpu) { char processor_name[49]; @@ -214,7 +214,7 @@ static void model_1067x_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 767c488d45..873c6e9479 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -206,7 +206,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -254,7 +254,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -262,7 +262,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 143a6f473a..65dfebba5b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -39,7 +39,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -64,7 +64,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -175,7 +175,7 @@ static void model_106cx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index f2605ebd79..b6ea237366 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -26,7 +26,7 @@ static void model_69x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index a921fbd368..783138ec83 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> * @@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -96,7 +96,7 @@ static void model_6bx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 936c67afc9..26c1b99499 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -26,7 +26,7 @@ static void model_6dx_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d4f5d8bf5e..623b0a30a1 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -206,7 +206,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -254,7 +254,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -262,7 +262,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index f879f34869..4f1d2043b6 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index f46e5bdc48..0717116d0a 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -213,7 +213,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -268,7 +268,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -276,7 +276,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index f00aba8e33..3d1e9ba9a3 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -58,7 +58,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -83,7 +83,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -214,7 +214,7 @@ static void configure_pic_thermal_sensors(void) #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif - + static void model_6fx_init(device_t cpu) { char processor_name[49]; @@ -231,7 +231,7 @@ static void model_6fx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6xx/microcode_MU16810d.h b/src/cpu/intel/model_6xx/microcode_MU16810d.h index ce207efa76..ef1ff7dd1d 100644 --- a/src/cpu/intel/model_6xx/microcode_MU16810d.h +++ b/src/cpu/intel/model_6xx/microcode_MU16810d.h @@ -1,12 +1,12 @@ /* - Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. - These microcode updates are distributed for the sole purpose of + These microcode updates are distributed for the sole purpose of installation in the BIOS or Operating System of computer systems which include an Intel P6 family microprocessor sold or distributed to or by you. You are authorized to copy and install this material on such systems. You are not authorized to use this material for - any other purpose. + any other purpose. */ /* MU16810d.inc */ diff --git a/src/cpu/intel/model_6xx/microcode_MU16830c.h b/src/cpu/intel/model_6xx/microcode_MU16830c.h index 2724e7bae4..602739c368 100644 --- a/src/cpu/intel/model_6xx/microcode_MU16830c.h +++ b/src/cpu/intel/model_6xx/microcode_MU16830c.h @@ -1,12 +1,12 @@ /* - Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. - These microcode updates are distributed for the sole purpose of + These microcode updates are distributed for the sole purpose of installation in the BIOS or Operating System of computer systems which include an Intel P6 family microprocessor sold or distributed to or by you. You are authorized to copy and install this material on such systems. You are not authorized to use this material for - any other purpose. + any other purpose. */ /* MU16830c.inc */ diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 7efdf2119e..6c795eab32 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -16,7 +16,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ -#include "microcode_MU16810d.h" +#include "microcode_MU16810d.h" #include "microcode_MU16830c.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_6xx_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index c4d1ef085e..568d4d70ee 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f0x/multiplier.h b/src/cpu/intel/model_f0x/multiplier.h index e2f81362e8..a3b1fcb309 100644 --- a/src/cpu/intel/model_f0x/multiplier.h +++ b/src/cpu/intel/model_f0x/multiplier.h @@ -1,5 +1,5 @@ -/* +/* ** NMI A20M IGNNE INTR * X8 H H H H * X9 H H H L projected @@ -8,7 +8,7 @@ * X12 H L H H * X13 H L H L * X14 H L L H - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L H H L * X18 L H L H @@ -18,7 +18,7 @@ * X22 L L L H projected * X23 L L L L projected * - ** NMI INTR IGNNE A20M + ** NMI INTR IGNNE A20M * X8 H H H H * X9 H L H H projected * X10 H H L H @@ -26,7 +26,7 @@ * X12 H H H L * X13 H L H L * X14 H H L L - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L L H H * X18 L H L H diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index a3a66783c4..f8dd1d85f7 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_f1x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f1x/multiplier.h b/src/cpu/intel/model_f1x/multiplier.h index e2f81362e8..a3b1fcb309 100644 --- a/src/cpu/intel/model_f1x/multiplier.h +++ b/src/cpu/intel/model_f1x/multiplier.h @@ -1,5 +1,5 @@ -/* +/* ** NMI A20M IGNNE INTR * X8 H H H H * X9 H H H L projected @@ -8,7 +8,7 @@ * X12 H L H H * X13 H L H L * X14 H L L H - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L H H L * X18 L H L H @@ -18,7 +18,7 @@ * X22 L L L H projected * X23 L L L L projected * - ** NMI INTR IGNNE A20M + ** NMI INTR IGNNE A20M * X8 H H H H * X9 H L H H projected * X10 H H L H @@ -26,7 +26,7 @@ * X12 H H H L * X13 H L H L * X14 H H L L - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L L H H * X18 L H L H diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index d7b77efb72..9c7af78969 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -37,7 +37,7 @@ static void model_f2x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f3x/microcode_M1DF340E.h b/src/cpu/intel/model_f3x/microcode_M1DF340E.h index a378fba8ac..55854b583a 100644 --- a/src/cpu/intel/model_f3x/microcode_M1DF340E.h +++ b/src/cpu/intel/model_f3x/microcode_M1DF340E.h @@ -9,7 +9,7 @@ */ /* M1DF340E.TXT - Noconoa D-0 */ - + 0x00000001, /* Header Version */ 0x0000000e, /* Patch ID */ diff --git a/src/cpu/intel/model_f3x/microcode_M1DF3413.h b/src/cpu/intel/model_f3x/microcode_M1DF3413.h index f2a0a8f79d..676d67c061 100644 --- a/src/cpu/intel/model_f3x/microcode_M1DF3413.h +++ b/src/cpu/intel/model_f3x/microcode_M1DF3413.h @@ -2,7 +2,7 @@ * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. These microcode updates are distributed for the sole purpose of @@ -12,9 +12,9 @@ on such systems. You are not authorized to use this material for any other purpose. */ - + /* M1DF3413.TXT - Noconoa D-0 */ - + 0x00000001, /* Header Version */ 0x00000013, /* Patch ID */ 0x07302004, /* DATE */ @@ -27,7 +27,7 @@ 0x00000000, /* reserved */ 0x00000000, /* reserved */ 0x00000000, /* reserved */ - + 0x9fbf327a, 0x2b41b451, 0xb2abaca8, diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index cbdd50ac2f..68b22c99a8 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + #include "microcode_M1DF3413.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -33,7 +33,7 @@ static void model_f3x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index a48c7592ba..d6acddee09 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + #include "microcode_MBDF410D.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -33,7 +33,7 @@ static void model_f4x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index faa74d3390..2fc27cff78 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,7 +8,7 @@ config CPU_INTEL_SOCKET_MPGA604 select UDELAY_TSC # mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on +# but the ramtest.c code on the Dell S1850 seems to choke on # enabling it, so disable it for now. config SSE2 bool diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 920984369e..33898e3280 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 8a12c8fa48..8bc274b381 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -179,12 +179,12 @@ testok: movb $0x40,%al pushl %eax /* bist */ call main - /* + /* * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we * get STACK up, we restore that. It is only needed if we * want to go back. */ - + /* We don't need cache as ram for now on */ /* disable cache */ movl %cr0, %eax @@ -207,7 +207,7 @@ testok: movb $0x40,%al movl $(0 | 6), %eax //movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr - + /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; * If 1M cacheable, then when S3 resume, there is stange color on * screen for 2 sec. suppose problem of a0000-dfffff and cache. @@ -218,7 +218,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax wrmsr - + movl $0x202, %ecx xorl %edx, %edx movl $(0x80000 | 6), %eax @@ -229,7 +229,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax wrmsr - + movl $0x204, %ecx xorl %edx, %edx movl $(0xc0000 | 6), %eax @@ -239,8 +239,8 @@ testok: movb $0x40,%al movl $0x205, %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax - wrmsr - + wrmsr + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl $0x206, %ecx xorl %edx, %edx @@ -267,7 +267,7 @@ testok: movb $0x40,%al __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -275,7 +275,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c index ef979198da..291e4afef9 100644 --- a/src/cpu/via/model_c3/model_c3_init.c +++ b/src/cpu/via/model_c3/model_c3_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c index da946957c2..5474b8d6c7 100644 --- a/src/cpu/via/model_c7/model_c7_init.c +++ b/src/cpu/via/model_c7/model_c7_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -36,7 +36,7 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0 static int c7a_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V @@ -51,7 +51,7 @@ static int c7a_speed_translation[] = { }; static int c7d_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 674315fbd2..1eb92c82d1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -21,8 +21,8 @@ it with the version available from LANL. */ -/** Start code to put an i386 or later processor into 32-bit - * protected mode. +/** Start code to put an i386 or later processor into 32-bit + * protected mode. */ /* .section ".rom.text" */ @@ -31,7 +31,7 @@ it with the version available from LANL. .globl _start .type _start, @function -_start: +_start: cli /* Save the BIST result */ movl %eax, %ebp @@ -68,13 +68,13 @@ _start: * pratical problem of being able to write code that can * be relocated. * - * An lgdt call before we have memory enabled cannot be + * An lgdt call before we have memory enabled cannot be * position independent, as we cannot execute a call * instruction to get our current instruction pointer. * So while this code is relocateable it isn't arbitrarily * relocatable. * - * The criteria for relocation have been relaxed to their + * The criteria for relocation have been relaxed to their * utmost, so that we can use the same code for both * our initial entry point and startup of the second cpu. * The code assumes when executing at _start that: diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds index 929740bd4c..cec03d6bc6 100644 --- a/src/cpu/x86/16bit/reset16.lds +++ b/src/cpu/x86/16bit/reset16.lds @@ -12,5 +12,5 @@ SECTIONS { *(.reset) . = 15 ; BYTE(0x00); - } + } } diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index bc5e4436ae..4e0f3b953a 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -18,23 +18,23 @@ gdtptr: .word 0 /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ /* selgdt 0x10,flat data segment */ - .word 0xffff, 0x0000 + .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 gdt_end: - + /* - * When we come here we are in protected mode. We expand + * When we come here we are in protected mode. We expand * the stack and copies the data segment from ROM to the * memory. * * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. + * does what is left of the chipset initialization. * * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. @@ -45,7 +45,7 @@ protected_start: lgdt %cs:gdtptr ljmp $ROM_CODE_SEG, $__protected_start - + __protected_start: /* Save the BIST value */ movl %eax, %ebp diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 555d74eecc..c8f83b0dd0 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -5,11 +5,11 @@ void setup_lapic(void) { - /* this is so interrupts work. This is very limited scope -- + /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... */ - /* this is the first way we learned to do it. It fails on real SMP - * stuff. So we have to do things differently ... + /* this is the first way we learned to do it. It fails on real SMP + * stuff. So we have to do things differently ... * see the Intel mp1.4 spec, page A-3 */ @@ -33,25 +33,25 @@ void setup_lapic(void) lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); /* Put the local apic in virtual wire mode */ - lapic_write_around(LAPIC_SPIV, + lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); - lapic_write_around(LAPIC_LVT0, - (lapic_read_around(LAPIC_LVT0) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + lapic_write_around(LAPIC_LVT0, + (lapic_read_around(LAPIC_LVT0) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | + | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_EXTINT) ); - lapic_write_around(LAPIC_LVT1, - (lapic_read_around(LAPIC_LVT1) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + lapic_write_around(LAPIC_LVT1, + (lapic_read_around(LAPIC_LVT1) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | + | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_NMI) ); diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dafc9a561c..5c1e7607e8 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -26,7 +26,7 @@ _secondary_start: movl %eax, %cr0 ljmpl $0x10, $1f -1: +1: .code32 movw $0x18, %ax movw %ax, %ds diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index d97cd93deb..1cbc544350 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -89,13 +89,13 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif - /* Set the default memory type and enable fixed and variable MTRRs + /* Set the default memory type and enable fixed and variable MTRRs */ /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; wrmsr(MTRRdefType_MSR, msr); - + } static inline void early_mtrr_init(void) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 94d7ca7d35..d44687a0e9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -68,7 +68,7 @@ static void enable_var_mtrr(void) /* setting variable mtrr, comes from linux kernel source */ static void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { msr_t base, mask; @@ -81,7 +81,7 @@ static void set_var_mtrr( // do this. if (sizek == 0) { disable_cache(); - + msr_t zero; zero.lo = zero.hi = 0; /* The invalid bit is kept in the mask, so we simply clear the @@ -109,8 +109,8 @@ static void set_var_mtrr( mask.lo = 0; } - // it is recommended that we disable and enable cache when we - // do this. + // it is recommended that we disable and enable cache when we + // do this. disable_cache(); /* Bit 32-35 of MTRRphysMask should be set to 1 */ @@ -228,7 +228,7 @@ static unsigned fixed_mtrr_index(unsigned long addrk) return index; } -static unsigned int range_to_mtrr(unsigned int reg, +static unsigned int range_to_mtrr(unsigned int reg, unsigned long range_startk, unsigned long range_sizek, unsigned long next_range_startk, unsigned char type, unsigned address_bits) { @@ -253,7 +253,7 @@ static unsigned int range_to_mtrr(unsigned int reg, unsigned long sizek; /* Compute the maximum size I can make a range */ max_align = fls(range_startk); - align = fms(range_sizek); + align = fms(range_sizek); if (align > max_align) { align = max_align; } @@ -274,7 +274,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } -static unsigned long resk(uint64_t value) +static unsigned long resk(uint64_t value) { unsigned long resultk; if (value < (1ULL << 42)) { @@ -298,7 +298,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", start_mtrr, last_mtrr); set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); - + } #ifndef CONFIG_VAR_MTRR_HOLE @@ -343,10 +343,10 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) return; } #endif - state->reg = range_to_mtrr(state->reg, state->range_startk, + state->reg = range_to_mtrr(state->reg, state->range_startk, state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits); #if CONFIG_VAR_MTRR_HOLE - state->reg = range_to_mtrr(state->reg, state->hole_startk, + state->reg = range_to_mtrr(state->reg, state->hole_startk, state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits); #endif state->range_startk = 0; @@ -356,7 +356,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) state->hole_sizek = 0; #endif } - /* Allocate an msr */ + /* Allocate an msr */ printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); state->range_startk = basek; state->range_sizek = sizek; @@ -365,7 +365,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) void x86_setup_fixed_mtrrs(void) { /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again + * mtrrs. If this doesn't work out we can get smart again * and clear out the mtrrs. */ @@ -390,20 +390,20 @@ void x86_setup_fixed_mtrrs(void) void x86_setup_var_mtrrs(unsigned address_bits) /* this routine needs to know how many address bits a given processor - * supports. CPUs get grumpy when you set too many bits in + * supports. CPUs get grumpy when you set too many bits in * their mtrr registers :( I would generically call cpuid here * and find out how many physically supported but some cpus are * buggy, and report more bits then they actually support. */ { /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again + * mtrrs. If this doesn't work out we can get smart again * and clear out the mtrrs. */ struct var_mtrr_state var_state; /* Cache as many memory areas as possible */ - /* FIXME is there an algorithm for computing the optimal set of mtrrs? + /* FIXME is there an algorithm for computing the optimal set of mtrrs? * In some cases it is definitely possible to do better. */ var_state.range_startk = 0; @@ -431,7 +431,7 @@ void x86_setup_var_mtrrs(unsigned address_bits) } #endif /* Write the last range */ - var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, + var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits); #if CONFIG_VAR_MTRR_HOLE var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 4440d7bd8c..0bec349444 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -43,7 +43,7 @@ static void paging_on(void *pdp) ); } -void *map_2M_page(unsigned long page) +void *map_2M_page(unsigned long page) { struct pde { uint32_t addr_lo; @@ -56,7 +56,7 @@ void *map_2M_page(unsigned long page) #if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) /* - pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, + pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, and that region need to be used as vga font buffer. Please make sure set CONFIG_RAMTOP=0x200000 in MB Config */ struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 9a2dfa599e..980ea69f51 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -72,14 +72,14 @@ static int uart_can_tx_byte(void) static void uart_wait_to_tx_byte(void) { - while(!uart_can_tx_byte()) + while(!uart_can_tx_byte()) ; } static void uart_wait_until_sent(void) { while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; + ; } static void uart_tx_byte(unsigned char data) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 1b25c2d2f8..d5c7127a15 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -4,7 +4,7 @@ CPUS = 4; SECTIONS { - /* This is the actual SMM handler. + /* This is the actual SMM handler. * * We just put code, rodata, data and bss all in a row. */ @@ -43,7 +43,7 @@ SECTIONS . = 0xa8000 - (( CPUS - 1) * 0x400); .jumptable : { *(.jumptable) - } + } /DISCARD/ : { *(.comment) diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index b443e5c1fe..3dd0b14c5a 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -38,11 +38,11 @@ * | | * | | * +--------------------------------+ 0xa8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0xa8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | * | ... | * +--------------------------------+ 0xa7400 * | | @@ -56,7 +56,7 @@ /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG * at which smm_handler_start lives. At the moment the handler - * lives right at 0xa0000, so the offset is 0. + * lives right at 0xa0000, so the offset is 0. */ #define SMM_HANDLER_OFFSET 0x0000 @@ -101,15 +101,15 @@ smm_handler_start: movl $LAPIC_ID, %esi movl (%esi), %ecx shr $24, %ecx - + /* calculate stack offset by multiplying the APIC ID * by 1024 (0x400), and save that offset in ebp. */ shl $10, %ecx movl %ecx, %ebp - /* We put the stack for each core right above - * its SMM entry point. Core 0 starts at 0xa8000, + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at 0xa8000, * we spare 0x10 bytes for the jump to be sure. */ movl $0xa8010, %eax @@ -155,11 +155,11 @@ smm_gdt: .long 0x00000000, 0x00000000 /* gdt selector 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ /* gdt selector 0x10, flat data segment */ - .word 0xffff, 0x0000 + .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 smm_gdt_end: @@ -168,7 +168,7 @@ smm_gdt_end: .section ".jumptable", "a", @progbits /* This is the SMM jump table. All cores use the same SMM handler - * for simplicity. But SMM Entry needs to be different due to the + * for simplicity. But SMM Entry needs to be different due to the * save state area. The jump table makes sure all CPUs jump into the * real handler on SMM entry. */ @@ -185,13 +185,13 @@ smm_gdt_end: .code16 jumptable: /* core 3 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 2 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 1 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 0 */ ljmp $0xa000, $SMM_HANDLER_OFFSET diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 14fdc639bc..50a8f28c3f 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,7 +22,7 @@ // Make sure no stage 2 code is included: #define __PRE_RAM__ -// FIXME: Is this piece of code southbridge specific, or +// FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? // It's needed right now because we get our PM_BASE from // here. @@ -73,7 +73,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 cpu cores before * we need to use the TSEG/HSEG for the actual SMM handler plus stack. * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. * @@ -101,7 +101,7 @@ smm_relocation_start: addr32 mov (%ebx), %al cmp $0x64, %al je 1f - + mov $0x38000 + 0x7ef8, %ebx jmp smm_relocate 1: @@ -112,8 +112,8 @@ smm_relocate: movl $LAPIC_ID, %esi addr32 movl (%esi), %ecx shr $24, %ecx - - /* calculate offset by multiplying the + + /* calculate offset by multiplying the * apic ID by 1024 (0x400) */ movl %ecx, %edx @@ -158,7 +158,7 @@ smm_relocate: outb %al, %dx /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ movb %cl, %al - addb $'0', %al + addb $'0', %al outb %al, %dx mov $']', %al outb %al, %dx diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc index a18ea18643..a42cb41259 100644 --- a/src/cpu/x86/sse_disable.inc +++ b/src/cpu/x86/sse_disable.inc @@ -2,7 +2,7 @@ * Put the processor back into a reset state * with respect to the xmm registers. */ - + xorps %xmm0, %xmm0 xorps %xmm1, %xmm1 xorps %xmm2, %xmm2 diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 4a8fd5287e..27c89e3a94 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -10,7 +10,7 @@ static unsigned long clocks_per_usec; #if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1) #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ -/* ------ Calibrate the TSC ------- +/* ------ Calibrate the TSC ------- * Too much 64-bit arithmetic here to do this cleanly in C, and for * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) * output busy loop as low as possible. We avoid reading the CTC registers @@ -88,13 +88,13 @@ bad_ctc: * this is the "no timer2" version. * to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80 * then we read TSC again, and divide the difference by 1,000,000 - * we have found on a wide range of machines that this gives us a a + * we have found on a wide range of machines that this gives us a a * good microsecond value * to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a * 267 Mhz. p5, it gives us 1.1 microseconds. * also, since gcc now supports long long, we use that. * also no unsigned long long / operator, so we play games. - * about the only thing you can do with long longs, it seems, + * about the only thing you can do with long longs, it seems, *is return them and assign them. * (and do asm on them, yuck) * so avoid all ops on long longs. @@ -103,7 +103,7 @@ static unsigned long long calibrate_tsc(void) { unsigned long long start, end, delta; unsigned long result, count; - + printk(BIOS_SPEW, "Calibrating delay loop...\n"); start = rdtscll(); // no udivdi3 because we don't like libgcc. (only in x86emu) @@ -130,7 +130,7 @@ static unsigned long long calibrate_tsc(void) result = delta; printk(BIOS_SPEW, "end %llx, start %llx\n", end, start); printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta); - + printk(BIOS_SPEW, "%s 32-bit result is %ld\n", __func__, result); diff --git a/src/devices/cardbus_device.c b/src/devices/cardbus_device.c index becdafd42f..044dfd274f 100644 --- a/src/devices/cardbus_device.c +++ b/src/devices/cardbus_device.c @@ -159,8 +159,8 @@ void cardbus_enable_resources(device_t dev) uint16_t ctrl; ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link[0].bridge_ctrl & ( - PCI_BRIDGE_CTL_PARITY | - PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | @@ -174,8 +174,8 @@ void cardbus_enable_resources(device_t dev) enable_childrens_resources(dev); } -unsigned int cardbus_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, +unsigned int cardbus_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn, unsigned int max) { return pci_scan_bus(bus, min_devfn, max_devfn, max); @@ -196,7 +196,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) /* Set up the primary, secondary and subordinate bus numbers. We have * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. + * subordinate bus number to 0xff for the moment. */ bus->secondary = ++max; bus->subordinate = 0xff; @@ -222,7 +222,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) ((unsigned int) (bus->subordinate) << 16)); pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses); - /* Now we can scan all subordinate buses + /* Now we can scan all subordinate buses * i.e. the bus behind the bridge. */ max = cardbus_scan_bus(bus, 0x00, 0xff, max); @@ -235,7 +235,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) ((unsigned int) (bus->subordinate) << 16); pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); - + printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); return max; } diff --git a/src/devices/device_util.c b/src/devices/device_util.c index e44a02e428..3e8cba2f98 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -79,7 +79,7 @@ struct device *dev_find_slot(unsigned int bus, unsigned int devfn) result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && - (dev->bus->secondary == bus) && + (dev->bus->secondary == bus) && (dev->path.pci.devfn == devfn)) { result = dev; break; @@ -92,32 +92,32 @@ struct device *dev_find_slot(unsigned int bus, unsigned int devfn) * @brief Given a smbus bus and a device number, find the device structure * * @param bus The bus number - * @param addr a device number + * @param addr a device number * @return pointer to the device structure */ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) { struct device *dev, *result; - + result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && - (dev->bus->secondary == bus) && + (dev->bus->secondary == bus) && (dev->path.i2c.device == addr)) { result = dev; - break; - } - } + break; + } + } return result; -} +} /** Find a device of a given vendor and type * @param vendor Vendor ID (e.g. 0x8086 for Intel) * @param device Device ID * @param from Pointer to the device structure, used as a starting point - * in the linked list of all_devices, which can be 0 to start at the + * in the linked list of all_devices, which can be 0 to start at the * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * @return Pointer to the device struct */ struct device *dev_find_device(unsigned int vendor, unsigned int device, struct device *from) { @@ -134,9 +134,9 @@ struct device *dev_find_device(unsigned int vendor, unsigned int device, struct /** Find a device of a given class * @param class Class of the device * @param from Pointer to the device structure, used as a starting point - * in the linked list of all_devices, which can be 0 to start at the + * in the linked list of all_devices, which can be 0 to start at the * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * @return Pointer to the device struct */ struct device *dev_find_class(unsigned int class, struct device *from) { @@ -167,11 +167,11 @@ const char *dev_path(device_t dev) case DEVICE_PATH_PCI: #if CONFIG_PCI_BUS_SEGN_BITS sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary>>8, dev->bus->secondary & 0xff, + dev->bus->secondary>>8, dev->bus->secondary & 0xff, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); #else sprintf(buffer, "PCI: %02x:%02x.%01x", - dev->bus->secondary, + dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); #endif break; @@ -408,7 +408,7 @@ resource_t resource_end(struct resource *resource) * the bridge. While the granularity is simply how many low bits of the * address cannot be set. */ - + /* Get the end (rounded up) */ end = base + align_up(resource->size, resource->gran) - 1; @@ -468,7 +468,7 @@ void report_resource_stored(device_t dev, struct resource *resource, const char sprintf(buf, "bus %02x ", dev->link[0].secondary); #endif } - printk(BIOS_DEBUG, + printk(BIOS_DEBUG, "%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index bb91249908..674971cb94 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -39,7 +39,7 @@ * so don't do it again */ #define OPT_HT_LINK 0 - + #if OPT_HT_LINK == 1 #include <cpu/amd/model_fxx_rev.h> #endif @@ -52,9 +52,9 @@ static device_t ht_scan_get_devs(device_t *old_devices) /* Extract the chain of devices to (first through last) * for the next hypertransport device. */ - while(last && last->sibling && + while(last && last->sibling && (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } @@ -101,11 +101,11 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) } /* AMD K8 Unsupported 1Ghz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { -#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 - #if CONFIG_K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT freq_cap &= ~(1 << HT_FREQ_1000Mhz); - } + } #endif #else freq_cap &= ~(1 << HT_FREQ_1000Mhz); @@ -129,7 +129,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; unsigned present_width_cap, upstream_width_cap; unsigned present_freq_cap, upstream_freq_cap; - unsigned ln_present_width_in, ln_upstream_width_in; + unsigned ln_present_width_in, ln_upstream_width_in; unsigned ln_present_width_out, ln_upstream_width_out; unsigned freq, old_freq; unsigned present_width, upstream_width, old_width; @@ -140,7 +140,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) /* Set the hypertransport link width and frequency */ reset_needed = 0; - /* See which side of the device our previous write to + /* See which side of the device our previous write to * set the unitid came from. */ cur->dev = dev; @@ -164,7 +164,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off); present_width_cap = pci_read_config8(cur->dev, cur->pos + cur->config_off); upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off); - + /* Calculate the highest useable frequency */ freq = log2(present_freq_cap & upstream_freq_cap); @@ -242,7 +242,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) } } #endif - + /* Remember the current link as the previous link, * But look at the other offsets. */ @@ -261,7 +261,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) } return reset_needed; - + } static unsigned ht_lookup_slave_capability(struct device *dev) @@ -355,7 +355,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti dummy.path.type = DEVICE_PATH_PCI; dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if ( (id == 0xffffffff) || (id == 0x00000000) || + if ( (id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { continue; } @@ -371,12 +371,12 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS); flags &= ~0x1f; pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); - printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", + printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", dev_path(&dummy), dummy.vendor, dummy.device); } } -unsigned int hypertransport_scan_chain(struct bus *bus, +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid) { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link @@ -410,7 +410,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, prev.config_off = PCI_HT_CAP_HOST_WIDTH; prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - + /* If present assign unitid to a hypertransport chain */ last_unitid = min_unitid -1; max_unitid = next_unitid = min_unitid; @@ -446,7 +446,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } } } while((ctrl & (1 << 5)) == 0); - + /* Get and setup the device_structure */ dev = ht_scan_get_devs(&old_devices); @@ -462,15 +462,15 @@ unsigned int hypertransport_scan_chain(struct bus *bus, /* Find the hypertransport link capability */ pos = ht_lookup_slave_capability(dev); if (pos == 0) { - printk(BIOS_ERR, "%s Hypertransport link capability not found", + printk(BIOS_ERR, "%s Hypertransport link capability not found", dev_path(dev)); break; } - + /* Update the Unitid of the current device */ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - - /* If the devices has a unitid set and is at devfn 0 we are done. + + /* If the devices has a unitid set and is at devfn 0 we are done. * This can happen with shadow hypertransport devices, * or if we have reached the bottom of a * hypertransport device chain. @@ -492,7 +492,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } } - } + } #endif flags |= next_unitid & 0x1f; @@ -502,12 +502,12 @@ unsigned int hypertransport_scan_chain(struct bus *bus, static_count = 1; for(func = dev; func; func = func->sibling) { func->path.pci.devfn += (next_unitid << 3); - static_count = (func->path.pci.devfn >> 3) + static_count = (func->path.pci.devfn >> 3) - (dev->path.pci.devfn >> 3) + 1; last_func = func; } /* Compute the number of unitids consumed */ - printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", + printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", dev_path(dev), count, static_count); if (count < static_count) { count = static_count; @@ -534,7 +534,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", dev_path(dev), - dev->vendor, dev->device, + dev->vendor, dev->device, (dev->enabled? "enabled": "disabled"), next_unitid); } while (last_unitid != next_unitid); @@ -562,7 +562,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one - + printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); @@ -573,11 +573,11 @@ unsigned int hypertransport_scan_chain(struct bus *bus, if (next_unitid > 0x20) { next_unitid = 0x20; } - if( (bus->secondary == 0) && (next_unitid > 0x18)) { + if( (bus->secondary == 0) && (next_unitid > 0x18)) { next_unitid = 0x18; /* avoid K8 on bus 0 */ } - /* Die if any leftover Static devices are are found. + /* Die if any leftover Static devices are are found. * There's probably a problem in the Config.lb. */ if(old_devices) { @@ -587,14 +587,14 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } printk(BIOS_ERR, "HT: Left over static devices. Check your Config.lb\n"); if(last_func && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it - last_func->sibling = old_devices; + last_func->sibling = old_devices; } /* Now that nothing is overlapping it is safe to scan the - * children. + * children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); - return max; + max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); + return max; } /** diff --git a/src/devices/oprom/include/x86emu/regs.h b/src/devices/oprom/include/x86emu/regs.h index 516b2ea836..d738974d4b 100644 --- a/src/devices/oprom/include/x86emu/regs.h +++ b/src/devices/oprom/include/x86emu/regs.h @@ -106,7 +106,7 @@ struct i386_special_regs { u32 FLAGS; }; -/* +/* * Segment registers here represent the 16 bit quantities * CS, DS, ES, SS. */ @@ -184,8 +184,8 @@ struct i386_segment_regs { #define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* - * Define a mask for only those flag bits we will ever pass back - * (via PUSHF) + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) */ #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) @@ -271,8 +271,8 @@ typedef struct { * Delayed flag set 3 bits (zero, signed, parity) * reserved 6 bits * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits * Extern interrupt 1 bits * Halted 1 bits */ diff --git a/src/devices/oprom/include/x86emu/x86emu.h b/src/devices/oprom/include/x86emu/x86emu.h index 493e494927..3ceee4985b 100644 --- a/src/devices/oprom/include/x86emu/x86emu.h +++ b/src/devices/oprom/include/x86emu/x86emu.h @@ -128,7 +128,7 @@ extern u32 X86API rdl(u32 addr); extern void X86API wrb(u32 addr, u8 val); extern void X86API wrw(u32 addr, u16 val); extern void X86API wrl(u32 addr, u32 val); - + #pragma pack() /*--------------------- type definitions -----------------------------------*/ @@ -175,10 +175,10 @@ void X86EMU_halt_sys(void); #define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 -#define DEBUG_MEM_TRACE_F 0x001000 -#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 -#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 #define DEBUG_SAVE_IP_CS_F 0x010000 #define DEBUG_TRACEJMP_F 0x020000 #define DEBUG_TRACEJMP_REGS_F 0x040000 diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 9e72a4a6a6..4d9604a581 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -45,16 +45,16 @@ int (*intXX_handler[256])(struct eregs *regs) = { NULL }; static int intXX_exception_handler(struct eregs *regs) { - printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", + printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); - x86_exception(regs); // Call coreboot exception handler + x86_exception(regs); // Call coreboot exception handler return 0; // Never returns? } static int intXX_unknown_handler(struct eregs *regs) { - printk(BIOS_INFO, "Unsupported software interrupt #0x%x\n", + printk(BIOS_INFO, "Unsupported software interrupt #0x%x\n", regs->vector); return -1; @@ -74,12 +74,12 @@ static void setup_interrupt_handlers(void) { int i; - /* The first 16 intXX functions are not BIOS services, + /* The first 16 intXX functions are not BIOS services, * but the CPU-generated exceptions ("hardware interrupts") */ for (i = 0; i < 0x10; i++) intXX_handler[i] = &intXX_exception_handler; - + /* Mark all other intXX calls as unknown first */ for (i = 0x10; i < 0x100; i++) { @@ -133,14 +133,14 @@ static void setup_realmode_idt(void) } /* Many option ROMs use the hard coded interrupt entry points in the - * system bios. So install them at the known locations. + * system bios. So install them at the known locations. */ - + /* int42 is the relocated int10 */ write_idt_stub((void *)0xff065, 0x42); /* VIA's VBIOS calls f000:f859 instead of int15 */ - write_idt_stub((void *)0xff859, 0x15); + write_idt_stub((void *)0xff859, 0x15); } void run_bios(struct device *dev, unsigned long addr) @@ -187,7 +187,7 @@ static u32 VSA_vrRead(u16 classIndex) "outl %%eax, %%dx\n" "addb $2, %%dl\n" "inw %%dx, %%ax\n" - : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "a"(classIndex) ); @@ -245,7 +245,7 @@ void do_vsmbios(void) } #endif -/* interrupt_handler() is called from assembler code only, +/* interrupt_handler() is called from assembler code only, * so there is no use in putting the prototype into a header file. */ int __attribute__((regparm(0))) interrupt_handler(u32 intnumber, @@ -308,7 +308,7 @@ int __attribute__((regparm(0))) interrupt_handler(u32 intnumber, // will later pop them. // What happens here is that we force (volatile!) changing // the values of the parameters of this function. We do this - // because we know that they stay alive on the stack after + // because we know that they stay alive on the stack after // we leave this function. Don't say this is bollocks. *(volatile u32 *)&eax = reg_info.eax; *(volatile u32 *)&ecx = reg_info.ecx; diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S index 724fe02c0d..469c42f90b 100644 --- a/src/devices/oprom/x86_asm.S +++ b/src/devices/oprom/x86_asm.S @@ -25,7 +25,7 @@ /* This is the intXX interrupt handler stub code. It gets copied * to the IDT and to some fixed addresses in the F segment. Before - * the code can used, it gets patched up by the C function copying + * the code can used, it gets patched up by the C function copying * it: byte 3 (the $0 in movb $0, %al) is overwritten with the int#. */ @@ -85,11 +85,11 @@ __run_optionrom = RELOCATED(.) * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax @@ -114,9 +114,9 @@ __run_optionrom = RELOCATED(.) lidt __realmode_idt /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs + mov %ax, %es + mov %ax, %fs + mov %ax, %gs mov $0x40, %ax mov %ax, %ds @@ -140,8 +140,8 @@ __run_optionrom = RELOCATED(.) data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 - movw $0x18, %ax - mov %ax, %ds + movw $0x18, %ax + mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs @@ -185,11 +185,11 @@ __run_vsa = RELOCATED(.) * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax @@ -214,9 +214,9 @@ __run_vsa = RELOCATED(.) lidt __realmode_idt /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs + mov %ax, %es + mov %ax, %fs + mov %ax, %gs mov $0x40, %ax mov %ax, %ds mov %cx, %ax // restore ax @@ -238,8 +238,8 @@ __run_vsa = RELOCATED(.) data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 - movw $0x18, %ax - mov %ax, %ds + movw $0x18, %ax + mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs @@ -275,17 +275,17 @@ __run_interrupt = RELOCATED(.) * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov $0x30, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protected mode */ - movl %cr0, %eax + movl %cr0, %eax andl $~PE, %eax - movl %eax, %cr0 + movl %eax, %cr0 /* Now really going into real mode */ data32 ljmp $0, $RELOCATED(1f) @@ -302,7 +302,7 @@ __run_interrupt = RELOCATED(.) movl %eax, %esp /* Load 16-bit intXX IDT */ - xor %ax, %ax + xor %ax, %ax mov %ax, %ds lidt __realmode_idt diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c index 90156334dc..49d69ee3a7 100644 --- a/src/devices/oprom/x86_interrupts.c +++ b/src/devices/oprom/x86_interrupts.c @@ -202,7 +202,7 @@ int int15_handler(struct eregs *regs) res = 0; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); } diff --git a/src/devices/oprom/x86emu/decode.c b/src/devices/oprom/x86emu/decode.c index 3d2ba23566..ed96dc66e6 100644 --- a/src/devices/oprom/x86emu/decode.c +++ b/src/devices/oprom/x86emu/decode.c @@ -732,7 +732,7 @@ RETURNS: Value of scale * index REMARKS: -Decodes scale/index of SIB byte and returns relevant offset part of +Decodes scale/index of SIB byte and returns relevant offset part of effective address. ****************************************************************************/ static unsigned decode_sib_si( diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c index f5cb6498b1..349a664f50 100644 --- a/src/devices/oprom/x86emu/ops2.c +++ b/src/devices/oprom/x86emu/ops2.c @@ -170,7 +170,7 @@ static void x86emuOp2_rdmsr(u8 op2) M.x86.R_EAX = 0; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); -} +} #define xorl(a,b) (((a) && !(b)) || (!(a) && (b))) diff --git a/src/devices/oprom/x86emu/sys.c b/src/devices/oprom/x86emu/sys.c index 957e0ca63b..7a9e3921ec 100644 --- a/src/devices/oprom/x86emu/sys.c +++ b/src/devices/oprom/x86emu/sys.c @@ -85,7 +85,7 @@ RETURNS: Byte value read from emulator memory. REMARKS: -Reads a byte value from the emulator memory. +Reads a byte value from the emulator memory. ****************************************************************************/ u8 X86API rdb(u32 addr) { @@ -130,7 +130,7 @@ addr - Emulator memory address to read RETURNS: Long value read from emulator memory. REMARKS: -Reads a long value from the emulator memory. +Reads a long value from the emulator memory. ****************************************************************************/ u32 X86API rdl(u32 addr) { @@ -189,7 +189,7 @@ addr - Emulator memory address to read val - Value to store REMARKS: -Writes a long value to emulator memory. +Writes a long value to emulator memory. ****************************************************************************/ void X86API wrl(u32 addr, u32 val) { diff --git a/src/devices/oprom/x86emu/x86emui.h b/src/devices/oprom/x86emu/x86emui.h index d693e335f4..8ad43bfa30 100644 --- a/src/devices/oprom/x86emu/x86emui.h +++ b/src/devices/oprom/x86emu/x86emui.h @@ -75,7 +75,7 @@ #include <xf86_ansic.h> #else #include <string.h> -#endif +#endif /*--------------------------- Inline Functions ----------------------------*/ #ifdef __cplusplus diff --git a/src/devices/oprom/yabel/biosemu.c b/src/devices/oprom/yabel/biosemu.c index 294d81f279..9cdd0f279b 100644 --- a/src/devices/oprom/yabel/biosemu.c +++ b/src/devices/oprom/yabel/biosemu.c @@ -250,7 +250,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad X86EMU_setupMemFuncs(&my_mem_funcs); //setup PMM struct in BIOS_DATA_SEGMENT, offset 0x0 - u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); if (pmm_length <= 0) { printf ("\nYABEL: Warning: PMM Area could not be setup. PMM not available (%x)\n", pmm_length); diff --git a/src/devices/oprom/yabel/biosemu.h b/src/devices/oprom/yabel/biosemu.h index 09ace729ec..39cc0a9b0e 100644 --- a/src/devices/oprom/yabel/biosemu.h +++ b/src/devices/oprom/yabel/biosemu.h @@ -38,7 +38,7 @@ // Address, there will only be a call to this INT and a RETF #define PNP_INT_NUM 0xFD -/* array of funtion pointers to override generic interrupt handlers +/* array of funtion pointers to override generic interrupt handlers * a YABEL caller can add functions to this array before calling YABEL * if a interrupt occurs, YABEL checks wether a function is set in * this array and only runs the generic interrupt handler code, if diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c index 035c8bc86e..c9ef0b7d77 100644 --- a/src/devices/oprom/yabel/compat/functions.c +++ b/src/devices/oprom/yabel/compat/functions.c @@ -61,6 +61,6 @@ u64 get_time(void) "rdtsc" : "=a"(eax), "=d"(edx) : /* no inputs, no clobber */); - act = ((u64) edx << 32) | eax; + act = ((u64) edx << 32) | eax; return act; } diff --git a/src/devices/oprom/yabel/compat/of.h b/src/devices/oprom/yabel/compat/of.h index 907139951f..6a00f7a316 100644 --- a/src/devices/oprom/yabel/compat/of.h +++ b/src/devices/oprom/yabel/compat/of.h @@ -19,7 +19,7 @@ #define phandle_t p32 #define ihandle_t p32 -typedef struct +typedef struct { unsigned int serv; int nargs; diff --git a/src/devices/oprom/yabel/compat/time.h b/src/devices/oprom/yabel/compat/time.h index 6f7099bd86..18dba3aa85 100644 --- a/src/devices/oprom/yabel/compat/time.h +++ b/src/devices/oprom/yabel/compat/time.h @@ -15,4 +15,4 @@ /* TODO: check how this works in x86 */ extern unsigned long tb_freq; u64 get_time(void); -#endif +#endif diff --git a/src/devices/oprom/yabel/debug.h b/src/devices/oprom/yabel/debug.h index d02930809d..fea1fb7a3b 100644 --- a/src/devices/oprom/yabel/debug.h +++ b/src/devices/oprom/yabel/debug.h @@ -39,7 +39,7 @@ static inline void set_ci(void) {}; * |||-Currently unused * ||||-Currently unused * |||||-Currently unused - * ||||||-DEBUG_PNP - Print Plug And Play access made by option rom + * ||||||-DEBUG_PNP - Print Plug And Play access made by option rom * |||||||-DEBUG_DISK - Print Disk I/O related messages, currently unused * ||||||||-DEBUG_PMM - Print messages related to POST Memory Manager (PMM) * |||||||||-DEBUG_VBE - Print messages related to VESA BIOS Extension (VBE) functions @@ -47,7 +47,7 @@ static inline void set_ci(void) {}; * |||||||||||-DEBUG_INTR - Print messages related to interrupt handling * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors) * |||||||||||||-DEBUG_MEM - Print memory access made by option rom (NOTE: this also includes accesses to fetch instructions) - * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom + * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom * 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours) */ diff --git a/src/devices/oprom/yabel/interrupt.c b/src/devices/oprom/yabel/interrupt.c index 9a796005bb..af79379f67 100644 --- a/src/devices/oprom/yabel/interrupt.c +++ b/src/devices/oprom/yabel/interrupt.c @@ -410,7 +410,7 @@ handleInt1a(void) M.x86.R_CL = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); -#else +#else (u8) rtas_pci_config_read(bios_device. puid, 1, bus, devfn, @@ -425,7 +425,7 @@ handleInt1a(void) M.x86.R_CX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); -#else +#else (u16) rtas_pci_config_read(bios_device. puid, 2, bus, devfn, @@ -440,7 +440,7 @@ handleInt1a(void) M.x86.R_ECX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); -#else +#else (u32) rtas_pci_config_read(bios_device. puid, 4, bus, devfn, @@ -478,7 +478,7 @@ handleInt1a(void) case 0xb10b: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config8(bios_device.dev, offs, M.x86.R_CL); -#else +#else rtas_pci_config_write(bios_device.puid, 1, bus, devfn, offs, M.x86.R_CL); #endif @@ -490,7 +490,7 @@ handleInt1a(void) case 0xb10c: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); -#else +#else rtas_pci_config_write(bios_device.puid, 2, bus, devfn, offs, M.x86.R_CX); #endif @@ -502,7 +502,7 @@ handleInt1a(void) case 0xb10d: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); -#else +#else rtas_pci_config_write(bios_device.puid, 4, bus, devfn, offs, M.x86.R_ECX); #endif @@ -576,7 +576,7 @@ handleInterrupt(int intNum) int_handled = 1; break; case PMM_INT_NUM: - /* the selfdefined PMM INT number, this is called by the code in PMM struct, it + /* the selfdefined PMM INT number, this is called by the code in PMM struct, it * is handled by pmm_handleInt() */ pmm_handleInt(); diff --git a/src/devices/oprom/yabel/pmm.c b/src/devices/oprom/yabel/pmm.c index ad4dc6834c..989bde4d27 100644 --- a/src/devices/oprom/yabel/pmm.c +++ b/src/devices/oprom/yabel/pmm.c @@ -19,8 +19,8 @@ #include "device.h" /* this struct is used to remember which PMM spaces - * have been assigned. MAX_PMM_AREAS defines how many - * PMM areas we can assign. + * have been assigned. MAX_PMM_AREAS defines how many + * PMM areas we can assign. * All areas are assigned in PMM_CONV_SEGMENT */ typedef struct { @@ -37,7 +37,7 @@ static pmm_allocation_t pmm_allocation_array[MAX_PMM_AREAS]; /* index into pmm_allocation_array */ static u32 curr_pmm_allocation_index = 0; -/* This function is used to setup the PMM struct in virtual memory +/* This function is used to setup the PMM struct in virtual memory * at a certain offset, the length of the PMM struct is returned */ u8 pmm_setup(u16 segment, u16 offset) { @@ -79,7 +79,7 @@ u8 pmm_setup(u16 segment, u16 offset) return sizeof(pmm_information_t); } -/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point +/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point * is executed, it must handle all PMM requests */ void pmm_handleInt() @@ -136,7 +136,7 @@ void pmm_handleInt() __func__, next_offset); if (length == 0) { /* largest possible block size requested, we have on segment - * to allocate, so largest possible is segment size (0xFFFF) + * to allocate, so largest possible is segment size (0xFFFF) * minus next_offset */ rval = 0xFFFF - next_offset; @@ -151,7 +151,7 @@ void pmm_handleInt() } align = 1 << lsb; } - /* always align at least to paragraph (16byte) boundary + /* always align at least to paragraph (16byte) boundary * hm... since the length is always in paragraphs, we cannot * align outside of paragraphs anyway... so this check might * be unnecessary...*/ diff --git a/src/devices/oprom/yabel/pmm.h b/src/devices/oprom/yabel/pmm.h index 95645dffdc..3cc3c17ac6 100644 --- a/src/devices/oprom/yabel/pmm.h +++ b/src/devices/oprom/yabel/pmm.h @@ -34,7 +34,7 @@ typedef struct { u8 code[3]; } __attribute__ ((__packed__)) pmm_information_t; -/* This function is used to setup the PMM struct in virtual memory +/* This function is used to setup the PMM struct in virtual memory * at a certain offset */ u8 pmm_setup(u16 segment, u16 offset); diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c index d80a97acc6..6ddeba613b 100644 --- a/src/devices/oprom/yabel/vbe.c +++ b/src/devices/oprom/yabel/vbe.c @@ -796,7 +796,7 @@ void vbe_set_graphics(void) mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); - unsigned char *framebuffer = + unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%08x\n", framebuffer); vbe_set_mode(&mode_info); @@ -807,9 +807,9 @@ void vbe_set_graphics(void) /* Switching Intel IGD to 1MB video memory will break this. Who * cares. */ // int imagesize = 1024*768*2; - + unsigned char *jpeg = cbfs_find_file("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH); - if (!jpeg) { + if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; } diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index b85ee53a72..8863c237a4 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -1187,7 +1187,7 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) #if CONFIG_PC80_SYSTEM == 1 /** - * + * * @brief Assign IRQ numbers * * This function assigns IRQs for all functions contained within the indicated @@ -1199,8 +1199,8 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) * @param bus * @param slot * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through - * PINTD of this slot. The particular irq #s that are passed in - * depend on the routing inside your southbridge and on your + * PINTD of this slot. The particular irq #s that are passed in + * depend on the routing inside your southbridge and on your * motherboard. */ void pci_assign_irqs(unsigned bus, unsigned slot, @@ -1229,7 +1229,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n", irq, bus, slot, funct); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, + pci_write_config8(pdev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); #ifdef PARANOID_IRQ_ASSIGNMENTS diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 0ed347b4e7..f13d9b6768 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -87,7 +87,7 @@ struct rom_header * pci_rom_probe(struct device *dev) rom_data->class_hi, rom_data->class_lo, rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { - printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", + printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); //return NULL; diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c index a14f00426f..790029ef1e 100644 --- a/src/devices/pciexp_device.c +++ b/src/devices/pciexp_device.c @@ -46,8 +46,8 @@ static void pciexp_tune_dev(device_t dev) #endif } -unsigned int pciexp_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, +unsigned int pciexp_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn, unsigned int max) { device_t child; diff --git a/src/devices/pcix_device.c b/src/devices/pcix_device.c index e6147c9ba8..d3af53eed0 100644 --- a/src/devices/pcix_device.c +++ b/src/devices/pcix_device.c @@ -86,12 +86,12 @@ const char *pcix_speed(unsigned sstatus) static const char pcix_266mhz[] = "266MHz PCI-X"; static const char pcix_533mhz[] = "533MHZ PCI-X"; static const char unknown[] = "Unknown"; - + const char *result; result = unknown; switch(PCI_X_SSTATUS_MFREQ(sstatus)) { - case PCI_X_SSTATUS_CONVENTIONAL_PCI: - result = conventional; + case PCI_X_SSTATUS_CONVENTIONAL_PCI: + result = conventional; break; case PCI_X_SSTATUS_MODE1_66MHZ: result = pcix_66mhz; @@ -99,17 +99,17 @@ const char *pcix_speed(unsigned sstatus) case PCI_X_SSTATUS_MODE1_100MHZ: result = pcix_100mhz; break; - + case PCI_X_SSTATUS_MODE1_133MHZ: result = pcix_133mhz; break; - + case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ: result = pcix_266mhz; break; - + case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ: diff --git a/src/devices/pnp_device.c b/src/devices/pnp_device.c index 721d1ce3dc..469487d1d2 100644 --- a/src/devices/pnp_device.c +++ b/src/devices/pnp_device.c @@ -172,11 +172,11 @@ static void pnp_get_ioresource(device_t dev, unsigned index, struct io_info *inf unsigned moving, gran, step; resource = new_resource(dev, index); - + /* Initilize the resource */ resource->limit = 0xffff; resource->flags |= IORESOURCE_IO; - + /* Get the resource size */ moving = info->mask; gran = 15; @@ -259,9 +259,9 @@ static void get_resources(device_t dev, struct pnp_info *info) resource->size = 1; resource->flags |= IORESOURCE_IRQ; } -} +} -void pnp_enable_devices(device_t base_dev, struct device_operations *ops, +void pnp_enable_devices(device_t base_dev, struct device_operations *ops, unsigned functions, struct pnp_info *info) { struct device_path path; @@ -270,7 +270,7 @@ void pnp_enable_devices(device_t base_dev, struct device_operations *ops, path.type = DEVICE_PATH_PNP; path.pnp.port = base_dev->path.pnp.port; - + /* Setup the ops and resources on the newly allocated devices */ for(i = 0; i < functions; i++) { /* Skip logical devices this Super I/O doesn't have. */ @@ -279,9 +279,9 @@ void pnp_enable_devices(device_t base_dev, struct device_operations *ops, path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path); - + /* Don't initialize a device multiple times */ - if (dev->ops) + if (dev->ops) continue; if (info[i].ops == 0) { diff --git a/src/devices/root_device.c b/src/devices/root_device.c index 3e3249e85e..b9369bcd1d 100644 --- a/src/devices/root_device.c +++ b/src/devices/root_device.c @@ -27,7 +27,7 @@ #include <device/pci.h> #include <reset.h> -/** +/** * Read the resources for the root device, * that encompass the resources for the entire system. * @param root Pointer to the device structure for the system root device @@ -54,9 +54,9 @@ void root_dev_set_resources(device_t root) * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time - * and is specified in the config file. Typical examples are the 'PNP' - * devices on a legacy ISA/LPC bus. There is no need of probing of any kind, - * the only thing we have to do is to walk through the bus and + * and is specified in the config file. Typical examples are the 'PNP' + * devices on a legacy ISA/LPC bus. There is no need of probing of any kind, + * the only thing we have to do is to walk through the bus and * enable or disable devices as indicated in the config file. * * On the other hand, some devices are virtual and their existence is @@ -93,7 +93,7 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) child->ops->enable(child); } if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev), child->bus->link ); } printk(BIOS_DEBUG, "%s %s\n", diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 3d9a8c5aa1..99a87b3371 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -1,7 +1,7 @@ /* * ATI Frame Buffer Device Driver Core Definitions */ - + #define PLL_CRTC_DECODE 0 #define EINVAL -1 diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h index 01f2887707..48d0f0172f 100644 --- a/src/drivers/ati/ragexl/fb.h +++ b/src/drivers/ati/ragexl/fb.h @@ -119,7 +119,7 @@ struct fb_fix_screeninfo { u32 smem_len; /* Length of frame buffer mem */ u32 type; /* see FB_TYPE_* */ u32 type_aux; /* Interleave for interleaved Planes */ - u32 visual; /* see FB_VISUAL_* */ + u32 visual; /* see FB_VISUAL_* */ u16 xpanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */ u16 ywrapstep; /* zero if no hardware ywrap */ @@ -142,8 +142,8 @@ struct fb_fix_screeninfo { struct fb_bitfield { u32 offset; /* beginning of bitfield */ u32 length; /* length of bitfield */ - u32 msb_right; /* != 0 : Most significant bit is */ - /* right */ + u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ }; #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ @@ -191,7 +191,7 @@ struct fb_var_screeninfo { struct fb_bitfield red; /* bitfield in fb mem if true color, */ struct fb_bitfield green; /* else only length is significant */ struct fb_bitfield blue; - struct fb_bitfield transp; /* transparency */ + struct fb_bitfield transp; /* transparency */ u32 nonstd; /* != 0 Non standard pixel format */ @@ -326,7 +326,7 @@ struct fb_info { devfs_handle_t devfs_handle; /* Devfs handle for new name */ devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ int (*changevar)(int); /* tell console var has changed */ - int (*switch_con)(int, struct fb_info*); + int (*switch_con)(int, struct fb_info*); /* tell fb to switch consoles */ int (*updatevar)(int, struct fb_info*); /* tell fb to update the vars */ @@ -338,7 +338,7 @@ struct fb_info { the cursor's color for non palette mode */ /* From here on everything is device dependent */ - void *par; -}; + void *par; +}; #endif /* _LINUX_FB_H */ diff --git a/src/drivers/ati/ragexl/fbcon.h b/src/drivers/ati/ragexl/fbcon.h index 974e373215..d6f122cbb0 100644 --- a/src/drivers/ati/ragexl/fbcon.h +++ b/src/drivers/ati/ragexl/fbcon.h @@ -16,7 +16,7 @@ struct display { struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ /* are updated by fbcon.c */ struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ + char *screen_base; /* pointer to top of virtual screen */ /* (virtual address) */ int visual; int type; /* see FB_TYPE_* */ @@ -96,11 +96,11 @@ struct display { ((s) & 0x400) #define attr_blink(p,s) \ ((s) & 0x8000) - + /* * Scroll Method */ - + /* Internal flags */ #define __SCROLL_YPAN 0x001 #define __SCROLL_YWRAP 0x002 diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h index c3afff28aa..e0dae0df28 100644 --- a/src/drivers/ati/ragexl/mach64.h +++ b/src/drivers/ati/ragexl/mach64.h @@ -5,7 +5,7 @@ * written with much help from Jon Howell * * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c index ca5283de27..b34be821fb 100644 --- a/src/drivers/ati/ragexl/mach64_ct.c +++ b/src/drivers/ati/ragexl/mach64_ct.c @@ -5,7 +5,7 @@ #if 0 #define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0) #else -#define FAIL(x) +#define FAIL(x) #endif static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, @@ -34,7 +34,7 @@ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, #if DEBUG_PLL==1 printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult); #endif - + /* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */ xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div * (u32)pll->vclk_post_div_real * 64) << 11; @@ -98,11 +98,11 @@ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, t_rp = ((memcntl >> 8) & 0x03) + 1; t_ras = ((memcntl >> 16) & 0x07) + 1; t_lat = (memcntl >> 4) & 0x03; - + t_pfc = t_rp + t_rcd + t_crd; t_rcc = max(t_rp + t_ras, t_pfc + n); - + /* fifo_on<<6 */ fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6; @@ -125,9 +125,9 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, int pllmclk, pllsclk; #endif u32 q; - + pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per; - + /* FIXME: use the VTB/GTB /3 post divider if it's better suited */ /* actually 8*q */ @@ -145,14 +145,14 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, pll->mclk_post_div_real = 1; pll->sclk_fb_div = q*pll->mclk_post_div_real/8; -#if DEBUG_PLL==1 +#if DEBUG_PLL==1 pllsclk = (1000000 * 2 * pll->sclk_fb_div) / (info->ref_clk_per * pll->pll_ref_div); printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n", pllsclk, pllsclk / pll->mclk_post_div_real); #endif - + pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2; /* actually 8*q */ @@ -177,7 +177,7 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n", pllmclk, pllmclk / pll->xclk_post_div_real); #endif - + /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */ if (q < 16*8 || q > 255*8) @@ -199,7 +199,7 @@ static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) u8 xpostdiv = 0; u8 mpostdiv = 0; u8 vpostdiv = 0; - + if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM)) pll->pll_gen_cntl = 0x64; /* mclk = sclk */ else @@ -221,7 +221,7 @@ static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) } pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */ - + switch (pll->xclk_post_div_real) { case 1: xpostdiv = 0; @@ -316,12 +316,12 @@ void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll) aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info); aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK - + aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info); aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info); - + aty_st_pll(EXT_VPLL_CNTL, 0, info); aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info); aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info); diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index d776c26a78..8b02239833 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -96,7 +96,7 @@ static const struct xl_card_cfg_t { 0x10, 0x19 } }; - + typedef struct { u8 lcd_reg; u32 val; @@ -202,7 +202,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) u32 temp; union aty_pll pll; const struct xl_card_cfg_t * card = &card_cfg[xl_card]; - + aty_st_8(CONFIG_STAT0, 0x85, info); mdelay(10); @@ -222,7 +222,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) info->features &= ~M64F_MFB_TIMES_4; } #endif - + /* * Calculate mclk and xclk dividers, etc. The passed * pixclock and bpp values don't matter yet, the vclk @@ -243,7 +243,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info); aty_st_pll(SPLL_CNTL2, 0x03, info); aty_st_pll(PLL_GEN_CNTL, 0x44, info); - + reset_clocks(info, &pll.ct, 0); mdelay(10); @@ -302,7 +302,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_8(LCD_INDEX, 0x08, info); aty_st_8(LCD_DATA, 0x0B, info); mdelay(2); - + // enable display requests, enable CRTC aty_st_8(CRTC_GEN_CNTL+3, 0x02, info); // disable display @@ -482,7 +482,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(device_t dev) { u32 chip_id; int j; @@ -513,9 +513,9 @@ static void ati_ragexl_init(device_t dev) #endif /*CONFIG_CONSOLE_BTEXT==1 */ struct fb_info_aty *info; - struct fb_info_aty info_t; - struct resource *res; - info = &info_t; + struct fb_info_aty info_t; + struct resource *res; + info = &info_t; #define USE_AUX_REG 1 @@ -529,12 +529,12 @@ static void ati_ragexl_init(device_t dev) info->frame_buffer = res->base; #endif /* CONFIG_CONSOLE_BTEXT */ -#if USE_AUX_REG==0 +#if USE_AUX_REG==0 info->ati_regbase = res->base+0x7ff000+0xc00; -#else +#else res = &dev->resource[2]; if(res->flags & IORESOURCE_MEM) { - info->ati_regbase = res->base+0x400; //using auxiliary register + info->ati_regbase = res->base+0x400; //using auxiliary register } #endif @@ -570,7 +570,7 @@ found: /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ if (mclk == 67 && info->ram_type < SDRAM) mclk = 63; - } + } #endif #if CONFIG_CONSOLE_BTEXT==1 aty_calc_mem_refresh(info, type, xclk); @@ -583,14 +583,14 @@ found: // info->dac_ops = &aty_dac_ct; // info->pll_ops = &aty_pll_ct; info->bus_type = PCI; - + atyfb_xl_init(info); #if CONFIG_CONSOLE_BTEXT==1 info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07); - + info->ref_clk_per = 1000000000000ULL/14318180; xtal = "14.31818"; #if 0 @@ -719,7 +719,7 @@ found: } if (atyfb_decode_var(&var, &info->default_par, info)) { -#if 0 +#if 0 printk(BIOS_DEBUG, "atyfb: can't set default video mode\n"); #endif return ; @@ -779,7 +779,7 @@ found: #endif btext_clearscreen(); - + map_boot_text(); #if 0 @@ -791,7 +791,7 @@ found: #endif #endif /* CONFIG_CONSOLE_BTEXT */ - + } #if CONFIG_CONSOLE_BTEXT==1 @@ -856,13 +856,13 @@ static void aty_set_crtc(const struct fb_info_aty *info, static int aty_var_to_crtc(const struct fb_info_aty *info, const struct fb_var_screeninfo *var, struct crtc *crtc) -{ +{ u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; u32 left, right, upper, lower, hslen, vslen, sync, vmode; u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; u32 pix_width, dp_pix_width, dp_chain_mask; - + /* input */ xres = var->xres; yres = var->yres; @@ -877,9 +877,9 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, lower = var->lower_margin; hslen = var->hsync_len; vslen = var->vsync_len; - sync = var->sync; + sync = var->sync; vmode = var->vmode; - + /* convert (and round up) and validate */ xres = (xres+7) & ~7; xoffset = (xoffset+7) & ~7; @@ -887,7 +887,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, if (vxres < xres+xoffset) vxres = xres+xoffset; h_disp = xres/8-1; - if (h_disp > 0xff) + if (h_disp > 0xff) FAIL("h_disp too large"); h_sync_strt = h_disp+(right/8); if (h_sync_strt > 0x1ff) @@ -924,7 +924,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, pix_width = CRTC_PIX_WIDTH_8BPP; dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; dp_chain_mask = 0x8080; - } + } #if SUPPORT_8_BPP_ABOVE==1 else if (bpp <= 16) { bpp = 16; @@ -943,7 +943,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | BYTE_ORDER_LSB_TO_MSB; dp_chain_mask = 0x8080; - } + } #endif else FAIL("invalid bpp"); @@ -1123,7 +1123,7 @@ static int encode_fix(struct fb_fix_screeninfo *fix, fix->smem_start = info->frame_buffer; fix->smem_len = (u32)info->total_vram; - /* + /* * Reg Block 0 (CT-compatible block) is at ati_regbase_phys * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400 */ @@ -1158,11 +1158,11 @@ static int encode_fix(struct fb_fix_screeninfo *fix, #endif /* * Set the User Defined Part of the Display - */ -#if PLL_CRTC_DECODE==1 + */ +#if PLL_CRTC_DECODE==1 static int atyfb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb) -{ +{ struct fb_info_aty *info = (struct fb_info_aty *)fb; struct atyfb_par par; #if 0 @@ -1171,8 +1171,8 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con, #endif int err; int activate = var->activate; - -#if 0 + +#if 0 if (con >= 0) display = &fb_display[con]; else @@ -1180,13 +1180,13 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con, #if 0 display = fb->disp; /* used during initialization */ #endif - + if ((err = atyfb_decode_var(var, &par, info))) return err; - + atyfb_encode_var(var, &par, (struct fb_info_aty *)info); - -#if 0 + +#if 0 printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK); #endif @@ -1262,7 +1262,7 @@ static void atyfb_set_par(const struct atyfb_par *par, #if PLL_CRTC_DECODE==1 info->current_par = *par; -#endif +#endif if (info->blitter_may_be_busy) wait_for_idle(info); @@ -1344,7 +1344,7 @@ static void atyfb_set_par(const struct atyfb_par *par, } #if 0 -static u16 red2[] = { +static u16 red2[] = { 0x0000, 0xaaaa }; static u16 green2[] = { @@ -1356,14 +1356,14 @@ static u16 blue2[] = { static u16 red4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; +}; static u16 green4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; +}; static u16 blue4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; - +}; + static u16 red8[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -1405,12 +1405,12 @@ static struct fb_cmap default_16_colors = { static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info_aty *info) -{ +{ int i, scale; - + if (regno > 255) return 1; - red >>= 8; + red >>= 8; green >>= 8; blue >>= 8; #if 0 @@ -1418,7 +1418,7 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, info->palette[regno].red = red; info->palette[regno].green = green; info->palette[regno].blue = blue; -#endif +#endif i = aty_ld_8(DAC_CNTL, info) & 0xfc; if (M64_HAS(EXTRA_BRIGHT)) i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/ @@ -1440,11 +1440,11 @@ int fb_set_cmap(struct fb_cmap *cmap, int kspc, int (*setcolreg)(u_int, u_int, u_int, u_int, u_int, struct fb_info_aty *), struct fb_info_aty *info) -{ +{ int i, start; u16 *red, *green, *blue, *transp; u_int hred, hgreen, hblue, htransp; - + red = cmap->red; green = cmap->green; blue = cmap->blue; @@ -1480,13 +1480,13 @@ struct fb_cmap *fb_default_cmap(int len) return &default_8_colors; #endif return &default_16_colors; -} +} static void do_install_cmap(int con, struct fb_info_aty *info) { #if PLL_CRTC_DECODE==1 int size = info->current_par.crtc.bpp == 16 ? 32 : 256; -#else +#else int size = 256; #endif fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); diff --git a/src/drivers/emulation/qemu/fb.h b/src/drivers/emulation/qemu/fb.h index 01f2887707..48d0f0172f 100644 --- a/src/drivers/emulation/qemu/fb.h +++ b/src/drivers/emulation/qemu/fb.h @@ -119,7 +119,7 @@ struct fb_fix_screeninfo { u32 smem_len; /* Length of frame buffer mem */ u32 type; /* see FB_TYPE_* */ u32 type_aux; /* Interleave for interleaved Planes */ - u32 visual; /* see FB_VISUAL_* */ + u32 visual; /* see FB_VISUAL_* */ u16 xpanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */ u16 ywrapstep; /* zero if no hardware ywrap */ @@ -142,8 +142,8 @@ struct fb_fix_screeninfo { struct fb_bitfield { u32 offset; /* beginning of bitfield */ u32 length; /* length of bitfield */ - u32 msb_right; /* != 0 : Most significant bit is */ - /* right */ + u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ }; #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ @@ -191,7 +191,7 @@ struct fb_var_screeninfo { struct fb_bitfield red; /* bitfield in fb mem if true color, */ struct fb_bitfield green; /* else only length is significant */ struct fb_bitfield blue; - struct fb_bitfield transp; /* transparency */ + struct fb_bitfield transp; /* transparency */ u32 nonstd; /* != 0 Non standard pixel format */ @@ -326,7 +326,7 @@ struct fb_info { devfs_handle_t devfs_handle; /* Devfs handle for new name */ devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ int (*changevar)(int); /* tell console var has changed */ - int (*switch_con)(int, struct fb_info*); + int (*switch_con)(int, struct fb_info*); /* tell fb to switch consoles */ int (*updatevar)(int, struct fb_info*); /* tell fb to update the vars */ @@ -338,7 +338,7 @@ struct fb_info { the cursor's color for non palette mode */ /* From here on everything is device dependent */ - void *par; -}; + void *par; +}; #endif /* _LINUX_FB_H */ diff --git a/src/drivers/emulation/qemu/fbcon.h b/src/drivers/emulation/qemu/fbcon.h index 8b83a3682b..0656c6f462 100644 --- a/src/drivers/emulation/qemu/fbcon.h +++ b/src/drivers/emulation/qemu/fbcon.h @@ -19,7 +19,7 @@ struct display { struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ /* are updated by fbcon.c */ struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ + char *screen_base; /* pointer to top of virtual screen */ /* (virtual address) */ int visual; int type; /* see FB_TYPE_* */ @@ -108,11 +108,11 @@ struct display { ((s) & 0x400) #define attr_blink(p,s) \ ((s) & 0x8000) - + /* * Scroll Method */ - + /* Internal flags */ #define __SCROLL_YPAN 0x001 #define __SCROLL_YWRAP 0x002 diff --git a/src/drivers/emulation/qemu/init.c b/src/drivers/emulation/qemu/init.c index 20e080b4f7..ae38d2b9ed 100644 --- a/src/drivers/emulation/qemu/init.c +++ b/src/drivers/emulation/qemu/init.c @@ -57,7 +57,7 @@ static void qemu_init(void) int width=640, height=480, depth=8; printk(BIOS_DEBUG, "Initializing VGA!\n"); - + vbe_outw(VBE_DISPI_INDEX_XRES, width); vbe_outw(VBE_DISPI_INDEX_YRES, height); vbe_outw(VBE_DISPI_INDEX_BPP, depth); diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 6af5325926..5c5dc8b16e 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -16,7 +16,7 @@ static void print_pci_regs(struct device *dev) for(i=0;i<256;i++) { byte = pci_read_config8(dev, i); - + if((i & 0xf)==0) printk(BIOS_DEBUG, "\n%02x:",i); printk(BIOS_DEBUG, " %02x",byte); } @@ -51,7 +51,7 @@ static void print_pci_regs_all(void) if(!dev->enabled) { continue; } - printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", + printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", bus, device, function, dev_path(dev)); print_pci_regs(dev); } @@ -83,7 +83,7 @@ static void print_cpuid(void) } static void print_smbus_regs(struct device *dev) -{ +{ int j; printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link); printk(BIOS_DEBUG, "%s", dev_path(dev)); @@ -97,7 +97,7 @@ static void print_smbus_regs(struct device *dev) } if ((j & 0xf) == 0) { printk(BIOS_DEBUG, "\n%02x: ", j); - } + } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } @@ -113,12 +113,12 @@ static void print_smbus_regs_all(struct device *dev) // Here don't need to call smbus_set_link, because we scan it from top to down if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) { - if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) + if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link); } } - - if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); + + if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); } for(i=0; i< dev->links; i++) { @@ -142,7 +142,7 @@ static void print_msr_dualcore(void) printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", index, eax, ebx, ecx, edx); - printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); + printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); index = 0xc001001f; printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); @@ -217,7 +217,7 @@ static tsc_t rdtsc(void) } static void print_tsc(void) { - + tsc_t tsc; tsc = rdtsc(); printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n", @@ -245,29 +245,29 @@ static void debug_init(device_t dev) printk(BIOS_DEBUG, "\n"); } break; - + case 1: print_pci_regs_all(); break; - case 2: + case 2: print_mem(); break; case 3: print_cpuid(); break; - case 4: + case 4: print_smbus_regs_all(&dev_root); break; - case 5: + case 5: print_msr_dualcore(); break; - case 6: + case 6: print_cache_size(); break; case 7: print_tsc(); break; - case 8: + case 8: hard_reset(); break; } @@ -291,5 +291,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_generic_debug_ops = { CHIP_NAME("Debug device") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 8cf6281bda..14b07aa90c 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -27,10 +27,10 @@ static void adm1026_init(device_t dev) if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux adm1026_enable_monitoring(dev); } - + } } @@ -65,5 +65,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_adm1026_ops = { CHIP_NAME("adm1026") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index 8329f08414..bca2c0dbc8 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -44,7 +44,7 @@ static void adm1027_init(device_t dev) if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { if (dev->bus->dev->path.type == DEVICE_PATH_I2C) - smbus_set_link(dev); // it is under mux + smbus_set_link(dev); // it is under mux adm1027_enable_monitoring(dev); } diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 512b19f48a..cd68a01ebf 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -15,7 +15,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) smbus_write_byte(dev, 0x01, 1<<link); // output value smbus_write_byte(dev, 0x03, 0); // all output } - + } } @@ -40,5 +40,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_i2cmux_ops = { CHIP_NAME("i2cmux") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index 30656eafca..4d2eeb99e6 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -14,7 +14,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) if(ops_smbus_bus(get_pbus_smbus(dev))) { smbus_send_byte(dev, link); // output value } - + } } @@ -39,5 +39,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_i2cmux2_ops = { CHIP_NAME("i2cmux2") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index e67409d01b..05302a68da 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -14,13 +14,13 @@ static void lm63_init(device_t dev) if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux result = smbus_read_byte(dev, 0x03); // result &= ~0x04; result |= 0x04; smbus_write_byte(dev, 0x03, result & 0xff); // config lm63 } - + } } @@ -42,5 +42,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_lm63_ops = { CHIP_NAME("National Semiconductor LM63") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/si/3114/si_sata.c b/src/drivers/si/3114/si_sata.c index 8d06fb6fbc..6661c2046d 100644 --- a/src/drivers/si/3114/si_sata.c +++ b/src/drivers/si/3114/si_sata.c @@ -29,10 +29,10 @@ static void si_sata_init(struct device *dev) /* some driver change class code to 0x104, but not change deviceid without reason*/ /* restore it so we don't need to unplug AC power to restore it*/ - + word = pci_read_config16(dev, 0x0a); if(word!=0x0180) { - /* enble change device id and class id*/ + /* enble change device id and class id*/ dword = pci_read_config32(dev,0x40); dword |= (1<<0); pci_write_config32(dev, 0x40, dword); @@ -49,7 +49,7 @@ static void si_sata_init(struct device *dev) } - + } static struct device_operations si_sata_ops = { .read_resources = pci_dev_read_resources, @@ -64,4 +64,4 @@ static const struct pci_driver si_sata_driver __pci_driver = { .vendor = 0x1095, .device = 0x3114, }; - + diff --git a/src/drivers/trident/blade3d/blade3d.c b/src/drivers/trident/blade3d/blade3d.c index e50d40514b..1d79766b9c 100644 --- a/src/drivers/trident/blade3d/blade3d.c +++ b/src/drivers/trident/blade3d/blade3d.c @@ -65,7 +65,7 @@ typedef struct Reg_struct { BYTE rMask; } Def_Reg_struct; -typedef Def_Reg_struct* lpDef_Reg_struct; +typedef Def_Reg_struct* lpDef_Reg_struct; // , *pDef_Reg_struct, far * lpDef_Reg_struct; static Def_Reg_struct Mode3_temp[] = { //mode3 temp @@ -209,7 +209,7 @@ static Def_Reg_struct Init_reg[] = { {Port_GRX, 0x33, 0x20, 0x00}, {Port_GRX, 0x30, 0x00, 0x00}, // - {Port_GRX, 0x28, 0x18, 0x00}, + {Port_GRX, 0x28, 0x18, 0x00}, {Port_CRX, 0x0F, 0x20, 0x40}, {Port_CRX, 0x1F, 0x00, 0x00}, @@ -806,7 +806,7 @@ static void config_OEM_regs(void) lpInit_reg = &Init_reg[0]; printk(BIOS_DEBUG, "blade3d: config_OEM_regs()\n"); - + outp(Port_GRX, 0x24); outp(Port_GRX + 1, 0xe0); //MCLK VCLK to 16 bit @@ -1025,4 +1025,4 @@ static const struct pci_driver trident_blade3d_driver __pci_driver = { .vendor = 0x1023, .device = 0x9880, }; - + diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index cec394e474..19d2881f43 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -33,7 +33,7 @@ /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a - * 64bit system, a uint64_t would be aligned to 64bit boundaries, + * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * * lb_uint64 will keep 64bit coreboot table values aligned to 32bit @@ -216,7 +216,7 @@ struct cmos_entries { uint32_t config; /* e=enumeration, h=hex, r=reserved */ uint32_t config_id; /* a number linking to an enumeration record */ #define CMOS_MAX_NAME_LENGTH 32 - uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, + uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, variable length int aligned */ }; @@ -232,7 +232,7 @@ struct cmos_enums { uint32_t config_id; /* a number identifying the config id */ uint32_t value; /* the value associated with the text */ #define CMOS_MAX_TEXT_LENGTH 32 - uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, + uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, variable length int aligned */ }; diff --git a/src/include/boot/elf_boot.h b/src/include/boot/elf_boot.h index ee6750d293..b119babc00 100644 --- a/src/include/boot/elf_boot.h +++ b/src/include/boot/elf_boot.h @@ -1,5 +1,5 @@ -#ifndef ELF_BOOT_H -#define ELF_BOOT_H +#ifndef ELF_BOOT_H +#define ELF_BOOT_H #include <stdint.h> @@ -32,7 +32,7 @@ typedef struct Elf_Half b_records; } Elf_Bhdr; -typedef struct +typedef struct { Elf_Word n_namesz; /* Length of the note's name. */ Elf_Word n_descsz; /* Length of the note's descriptor. */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 6eb706284c..c17d13f64f 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -84,7 +84,7 @@ struct cbfs_header { u32 magic; - u32 version; + u32 version; u32 romsize; u32 bootblocksize; u32 align; diff --git a/src/include/console/btext.h b/src/include/console/btext.h index 88d93931b9..1d2e37e1fc 100644 --- a/src/include/console/btext.h +++ b/src/include/console/btext.h @@ -3,7 +3,7 @@ * (for MacOS) when it is used to boot Linux. * * Written by Benjamin Herrenschmidt. - * + * * Move to coreboot by LYH yhlu@tyan.com * */ diff --git a/src/include/console/console.h b/src/include/console/console.h index be91988291..36661c25c7 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -30,7 +30,7 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; #else /* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack +/* Using a global varible can cause problems when we reset the stack * from cache as ram to ram. If we make this a define USE_SHARED_STACK * we could use the same code on all architectures. */ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index f7d58bbd6a..2cf44de7ea 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h index 28158a6c38..3ae35fd17d 100644 --- a/src/include/cpu/amd/amdk8_sysconf.h +++ b/src/include/cpu/amd/amdk8_sysconf.h @@ -20,7 +20,7 @@ struct amdk8_sysconf_t { int apicid_offset; void *mb; // pointer for mb releated struct - + }; extern struct amdk8_sysconf_t sysconf; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index ec99b95395..681b90cca0 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -284,20 +284,20 @@ #define SMM_INST_EN_SET (1<<3) #define INTL_SMI_EN_SET (1<<4) #define EXTL_SMI_EN_SET (1<<5) - + #define CPU_FPU_MSR_MODE 0x1A00 #define FPU_IE_SET (1<<0) - + #define CPU_FP_UROM_BIST 0x1A03 - + #define CPU_BC_CONF_0 0x1900 #define TSC_SUSP_SET (1<<5) #define SUSP_EN_SET (1<<12) - + /**/ /* VG GLIU0 port4*/ /**/ - + #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) #define VG_GLD_MSR_PM (MSR_VG + 0x2004) @@ -332,7 +332,7 @@ #define RSTPLL_UPPER_MDIV_SHIFT 9 #define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_FBDIV_SHIFT 0 - + #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 161092248c..d312c0e6da 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -285,11 +285,11 @@ #define CPU_L2TB_ENTRY 0x189E #define CPU_L2TB_ENTRY_I 0x189F #define CPU_DM_BIST 0x18C0 - + #define CPU_BC_CONF_0 0x1900 #define TSC_SUSP_SET (1<<5) #define SUSP_EN_SET (1<<12) - + #define CPU_BC_CONF_1 0x1901 #define CPU_BC_MSR_LOCK 0x1908 #define CPU_BC_L2_CONF 0x1920 @@ -342,11 +342,11 @@ #define CPU_CPUID12 0x3012 #define CPU_CPUID13 0x3013 - + /* VG GLIU0 port4*/ - + #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) diff --git a/src/include/cpu/amd/sc520.h b/src/include/cpu/amd/sc520.h index b0fa5680b7..c79e99efac 100644 --- a/src/include/cpu/amd/sc520.h +++ b/src/include/cpu/amd/sc520.h @@ -2,8 +2,8 @@ /* default location of the MMCR */ #define MMCR 0xfffef000 -/* the PAR register struct definition, the location in memory, - * and a handy pointer for you to use +/* the PAR register struct definition, the location in memory, + * and a handy pointer for you to use */ struct parreg { @@ -25,7 +25,7 @@ struct parreg { /* here is the real mmcr struct */ struct memregs { - /* make these shorts, we are lsb and the hardware seems to like it + /* make these shorts, we are lsb and the hardware seems to like it * better */ unsigned short drcctl; @@ -46,7 +46,7 @@ struct dbctl { unsigned char dbctl; unsigned char pad4[15]; }; - + struct romregs { unsigned char bootcs; unsigned char pad5[3]; @@ -55,7 +55,7 @@ struct romregs { unsigned char romcs2; unsigned char pad7[6]; }; - + struct hostbridge { unsigned short ctl; @@ -169,7 +169,7 @@ struct ssi { unsigned char pad[0x2b]; }; - + /* interrupt control registers */ /* defined this way for portability. Shame we can't just use plan 9 c. */ struct pic { @@ -225,7 +225,7 @@ struct pic { unsigned char gp9imap; unsigned char gp10imap; unsigned char padend[0x14]; -}; +}; struct reset { unsigned char sysinfo; @@ -282,7 +282,7 @@ struct dmacontrol { }; - + struct mmcr { unsigned short revid; diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index e98ac86409..805b977cd7 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -7,7 +7,7 @@ #ifndef CPU_AMD_VR_H #define CPU_AMD_VR_H -#define VRC_INDEX 0xAC1C // Index register +#define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register #define VR_UNLOCK 0xFC53 // Virtual register unlock code #define NO_VR -1 // No virtual registers @@ -24,7 +24,7 @@ #define GET_ERROR 0x05 #define SET_VSM_TYPE 0x06 #define SIGNATURE 0x03 - #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX + #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX #define GET_HW_INFO 0x04 #define VSM_VERSION 0x05 @@ -32,7 +32,7 @@ #define MSR_ACCESS 0x07 #define GET_DESCR_INFO 0x08 #define PCI_INT_AB 0x09 // GPIO pins for INTA# and INTB# - #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# + #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# #define WATCHDOG 0x0B // Watchdog timer #define MAX_MISC WATCHDOG @@ -48,7 +48,7 @@ #define CODEC_TYPE 0x05 #define STATE_INDEX 0x06 #define STATE_DATA 0x07 - #define AUDIO_IRQ 0x08 // For use by native audio drivers + #define AUDIO_IRQ 0x08 // For use by native audio drivers #define STATUS_PTR 0x09 // For use by native audio drivers #define MAX_AUDIO STATUS_PTR @@ -86,7 +86,7 @@ #define VG_CFG_DPMS_V 0x0080 // VSYNC mask bit #define VG_VESA_SV_RST 0x0020 // VESA Save/Restore state flag #define VG_VESA_RST 0x0000 // VESA Restore state - #define VG_VESA_SV 0x0020 // VESA Save state + #define VG_VESA_SV 0x0020 // VESA Save state #define VG_FRSH_MODE 0x0002 // Mode refresh flag #define VG_FRSH_TIMINGS 0x0001 // Timings only refresh flag @@ -183,7 +183,7 @@ #define VG_TV_PAL 0x0010 // PAL output format #define VG_TV_HDTV 0x0020 // HDTV output format - // The meaning of the VG_TV_RES field is dependent on the selected + // The meaning of the VG_TV_RES field is dependent on the selected // encoder and output format. The translations are: // ADV7171 - Not Used // SAA7127 - Not Used @@ -191,7 +191,7 @@ // LO -> 720x480p // MED -> 1280x720p // HI -> 1920x1080i - // FS454 - Both SD and HD resolutions + // FS454 - Both SD and HD resolutions // SD Resolutions - NTSC and PAL // LO -> 640x480 // MED -> 800x600 @@ -331,8 +331,8 @@ #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space #define SLPB_CLEAR 0x07 // clear sleep button GPIO status's #define PIRQ_ROUTING 0x08 // read the PCI IRQ routing based on BIOS setup - #define ACPI_UNUSED2 0x09 - #define ACPI_UNUSED3 0x0A + #define ACPI_UNUSED2 0x09 + #define ACPI_UNUSED3 0x0A #define PIC_INTERRUPT 0x0B #define ACPI_PRESENT 0x0C #define ACPI_GEN_COMMAND 0x0D @@ -380,7 +380,7 @@ #define VRC_DEBUGGER 0x0E #define MAX_DEBUGGER NO_VR - + #define VRC_STR 0x0F // Virtual Register class #define RESTORE_ADDR 0x00 // Physical address of MSR restore table @@ -404,7 +404,7 @@ #define VRC_SYSINFO 0x12 // Virtual Register class #define VRC_SI_VERSION 0x00 // Sysinfo VSM version - #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ + #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ #define VRC_SI_CHIPSET_BASE_LOW 0x02 #define VRC_SI_CHIPSET_BASE_HI 0x03 #define VRC_SI_CHIPSET_ID 0x04 diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index be27f1d9ea..f3ac2ed11f 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2004 Eric W. Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index cbbd5cfd85..daa7e18422 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -17,7 +17,7 @@ static void wrmsr(unsigned long index, msr_t msr) #else -typedef struct msr_struct +typedef struct msr_struct { unsigned lo; unsigned hi; diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index c1eb022886..eb8fa5a91c 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,5 +1,5 @@ #ifndef CPU_X86_PAE_H -#define CPU_X86_PAE_H +#define CPU_X86_PAE_H #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2954ecd1f7..155f666b3c 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* AMD64 SMM State-Save Area +/* AMD64 SMM State-Save Area * starts @ 0x7e00 */ typedef struct { @@ -115,7 +115,7 @@ typedef struct { } __attribute__((packed)) amd64_smm_state_save_area_t; -/* Intel Core 2 (EM64T) SMM State-Save Area +/* Intel Core 2 (EM64T) SMM State-Save Area * starts @ 0x7d00 */ typedef struct { @@ -193,7 +193,7 @@ typedef struct { } __attribute__((packed)) em64t_smm_state_save_area_t; -/* Legacy x86 SMM State-Save Area +/* Legacy x86 SMM State-Save Area * starts @ 0x7e00 */ diff --git a/src/include/cpu/x86/stack.h b/src/include/cpu/x86/stack.h index d39764a7d6..158b670251 100644 --- a/src/include/cpu/x86/stack.h +++ b/src/include/cpu/x86/stack.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/device/agp.h b/src/include/device/agp.h index 073858ae10..564b0bb4e6 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -2,7 +2,7 @@ #define DEVICE_AGP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int agp_scan_bus(struct bus *bus, +unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int agp_scan_bridge(device_t dev, unsigned int max); diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 07cc46a54a..5b003d3217 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -3,7 +3,7 @@ /* (c) 2005 Linux Networx GPL see COPYING for details */ void cardbus_read_resources(device_t dev); -unsigned int cardbus_scan_bus(struct bus *bus, +unsigned int cardbus_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int cardbus_scan_bridge(device_t dev, unsigned int max); void cardbus_enable_resources(device_t dev); diff --git a/src/include/device/device.h b/src/include/device/device.h index df8fb5f6d5..59dd0815e6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -49,8 +49,8 @@ struct bus { unsigned disable_relaxed_ordering : 1; }; -#define MAX_RESOURCES 24 -#define MAX_LINKS 8 +#define MAX_RESOURCES 24 +#define MAX_LINKS 8 /* * There is one device structure for each slot-number/function-number * combination: @@ -78,7 +78,7 @@ struct device { unsigned int resources; /* links are (downstream) buses attached to the device, usually a leaf - * device with no children have 0 buses attached and a bridge has 1 bus + * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; /* number of buses attached to the device */ @@ -139,10 +139,10 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char* msg); -/* Rounding for boundaries. +/* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ -#define DEVICE_IO_ALIGN 16 +#define DEVICE_IO_ALIGN 16 #define DEVICE_MEM_ALIGN 4096 extern struct device_operations default_dev_ops_root; diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 6a350f8232..e927d617fd 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -3,7 +3,7 @@ #include <device/hypertransport_def.h> -unsigned int hypertransport_scan_chain(struct bus *bus, +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_ht_ops_bus; diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 6c12dcf39f..d6276ba003 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -11,7 +11,7 @@ #define HT_FREQ_1200Mhz 7 #define HT_FREQ_1400Mhz 8 #define HT_FREQ_1600Mhz 9 -#define HT_FREQ_1800Mhz 10 +#define HT_FREQ_1800Mhz 10 #define HT_FREQ_2000Mhz 11 #define HT_FREQ_2200Mhz 12 #define HT_FREQ_2400Mhz 13 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5485644393..131564c8c5 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -61,7 +61,7 @@ void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, + unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); unsigned int pci_scan_bridge(device_t bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index ba972547ea..a5aa3a1c3b 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -26,7 +26,7 @@ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ -#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ @@ -55,8 +55,8 @@ /* * Base addresses specify locations in memory or I/O space. - * Decoded size can be determined by writing a value of - * 0xffffffff to the register, and reading it back. Only + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ @@ -80,7 +80,7 @@ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) @@ -189,7 +189,7 @@ /* Hypertransport Registers */ #define PCI_HT_CAP_SIZEOF 4 -#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ +#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ #define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ #define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 9ea662d490..becc800934 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,7 +2,7 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pciexp_scan_bus(struct bus *bus, +unsigned int pciexp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 8bf193530a..e017922ef1 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,7 +2,7 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, +unsigned int pcix_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pcix_scan_bridge(device_t dev, unsigned int max); const char *pcix_speed(unsigned sstatus); diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 09a77e72f1..8da08a2250 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -11,40 +11,40 @@ typedef struct { int counter; } atomic_t; /** * atomic_read - read atomic variable * @v: pointer of type atomic_t - * + * * Atomically reads the value of @v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value - * + * * Atomically sets the value of @v to @i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable * @v: pointer of type atomic_t - * + * * Atomically increments @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_inc(v) (((v)->counter)++) /** * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t - * + * * Atomically decrements @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_dec(v) (((v)->counter)--) diff --git a/src/include/string.h b/src/include/string.h index b4edf432ac..04c3733f8b 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -12,10 +12,10 @@ int memcmp(const void *s1, const void *s2, size_t n); int sprintf(char * buf, const char *fmt, ...); #endif -// simple string functions +// simple string functions -static inline size_t strnlen(const char *src, size_t max) -{ +static inline size_t strnlen(const char *src, size_t max) +{ size_t i = 0; while((*src++) && (i < max)) { i++; @@ -37,13 +37,13 @@ static inline char *strchr(const char *s, int c) for (; *s; s++) { if (*s == c) return (char *) s; - } + } return 0; } #if !defined(__PRE_RAM__) static inline char *strdup(const char *s) -{ +{ size_t sz = strlen(s) + 1; char *d = malloc(sz); memcpy(d, s, sz); @@ -69,7 +69,7 @@ static inline char *strncpy(char *to, const char *from, int count) } static inline int strcmp(const char *s1, const char *s2) -{ +{ int r; while ((r = (*s1 - *s2)) == 0 && *s1) { @@ -77,7 +77,7 @@ static inline int strcmp(const char *s1, const char *s2) s2++; } return r; -} +} static inline int strncmp(const char *s1, const char *s2, int maxlen) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 390e7796e8..690033e6b0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -160,11 +160,11 @@ void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest) if (orom == NULL) return NULL; - /* They might have specified a dest address. If so, we can decompress. + /* They might have specified a dest address. If so, we can decompress. * If not, there's not much hope of decompressing or relocating the rom. * in the common case, the expansion rom is uncompressed, we - * pass 0 in for the dest, and all we have to do is find the rom and - * return a pointer to it. + * pass 0 in for the dest, and all we have to do is find the rom and + * return a pointer to it. */ /* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ @@ -193,9 +193,9 @@ void * cbfs_load_stage(const char *name) if (stage == NULL) return (void *) -1; - printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", + printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (u32) stage->load, stage->memlen, + (u32) stage->load, stage->memlen, stage->entry); memset((void *) (u32) stage->load, 0, stage->memlen); @@ -235,9 +235,9 @@ int cbfs_execute_stage(const char *name) /** * run_address is passed the address of a function taking no parameters and - * jumps to it, returning the result. - * @param f the address to call as a function. - * @return value returned by the function. + * jumps to it, returning the result. + * @param f the address to call as a function. + * @return value returned by the function. */ int run_address(void *f) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 9e8aff3e67..7e3e20123a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -67,7 +67,7 @@ void cbmem_init(u64 baseaddr, u64 size) #ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif - + debug("Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); if (size < (64 * 1024)) { @@ -103,7 +103,7 @@ void *cbmem_add(u32 id, u64 size) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) { return NULL; } @@ -121,7 +121,7 @@ void *cbmem_add(u32 id, u64 size) /* Align size to 512 byte blocks */ - size = ALIGN(size, 512) < cbmem_toc[0].size ? + size = ALIGN(size, 512) < cbmem_toc[0].size ? ALIGN(size, 512) : cbmem_toc[0].size; /* Now look for the first free/usable TOC entry */ @@ -155,7 +155,7 @@ void *cbmem_find(u32 id) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) return NULL; @@ -197,7 +197,7 @@ void cbmem_list(void) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) return; diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 9306baf5d0..48f93d4699 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -39,7 +39,7 @@ unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned sum = ~sum & 0xFFFF; new = ~new & 0xFFFF; if (offset & 1) { - /* byte swap the sum if it came from an odd offset + /* byte swap the sum if it came from an odd offset * since the computation is endian independant this * works. */ diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c index 2fe1ea305b..32a572e44c 100644 --- a/src/lib/generic_dump_spd.c +++ b/src/lib/generic_dump_spd.c @@ -12,8 +12,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -38,8 +38,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index edecc06850..8a06252170 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -45,7 +45,7 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl) } /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for us while on others + * Some chipsets do the work for us while on others * we need to it by hand. */ print_debug("Ram3\n"); diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 1e917c2b40..4297299ee5 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -270,7 +270,7 @@ int jpeg_check_size(unsigned char *buf, int width, int height) return 1; } -int jpeg_decode(unsigned char *buf, unsigned char *pic, +int jpeg_decode(unsigned char *buf, unsigned char *pic, int width, int height, int depth, struct jpeg_decdata *decdata) { int i, j, m, tac, tdc; diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 532a2b2614..be0f386bdf 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -1,4 +1,4 @@ -/* +/* Coreboot interface to memory-saving variant of LZMA decoder diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 65819b53cf..1cf647d27b 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -37,7 +37,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -47,9 +47,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -72,7 +72,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -161,7 +161,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + RC_INIT(inStream, inSize); @@ -170,7 +170,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos ) & posStateMask); @@ -179,9 +179,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos ) & literalPosMask) << lc) + (previousByte >> (8 - lc)))); @@ -212,7 +212,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -236,10 +236,10 @@ int LzmaDecode(CLzmaDecoderState *vs, IfBit0(prob) { UpdateBit0(prob); - + if (nowPos == 0) return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; previousByte = outStream[nowPos - rep0]; outStream[nowPos++] = previousByte; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -322,7 +322,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) diff --git a/src/lib/lzmadecode.h b/src/lib/lzmadecode.h index dedde0de67..34c9f14c33 100644 --- a/src/lib/lzmadecode.h +++ b/src/lib/lzmadecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ diff --git a/src/lib/nrv2b.c b/src/lib/nrv2b.c index c91eda5047..d84e99ec0b 100644 --- a/src/lib/nrv2b.c +++ b/src/lib/nrv2b.c @@ -1,4 +1,4 @@ -// This GETBIT is supposed to work on little endian +// This GETBIT is supposed to work on little endian // 32bit systems. The algorithm will definitely need // some fixing on other systems, but it might not be // a problem since the nrv2b binary behaves the same.. @@ -37,7 +37,7 @@ static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p) // skip length src += 4; - /* FIXME: check olen with the length stored in first 4 bytes */ + /* FIXME: check olen with the length stored in first 4 bytes */ for (;;) { unsigned int m_off, m_len; diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 605d555e46..98872a47d7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -48,7 +48,7 @@ static void phys_memory_barrier(void) static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; - /* + /* * Fill. */ #if CONFIG_USE_PRINTK_IN_CAR @@ -85,7 +85,7 @@ static void ram_verify(unsigned long start, unsigned long stop) { unsigned long addr; int i = 0; - /* + /* * Verify. */ #if CONFIG_USE_PRINTK_IN_CAR @@ -168,7 +168,7 @@ void ram_check(unsigned long start, unsigned long stop) #else print_debug("Testing DRAM : "); print_debug_hex32(start); - print_debug("-"); + print_debug("-"); print_debug_hex32(stop); print_debug("\n"); #endif diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 79eb1c51c1..3dbee0b464 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -33,7 +33,7 @@ static inline void uart8250_wait_to_tx_byte(unsigned base_port) static inline void uart8250_wait_until_sent(unsigned base_port) { - while(!(inb(base_port + UART_LSR) & 0x40)) + while(!(inb(base_port + UART_LSR) & 0x40)) ; } diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c index cb70c625e2..d2e46729d1 100644 --- a/src/lib/usbdebug_direct.c +++ b/src/lib/usbdebug_direct.c @@ -87,7 +87,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) /* Stop when the transaction is finished */ if (ctrl & DBGP_DONE) break; - } while(--loop>0); + } while(--loop>0); if (!loop) return -1000; @@ -132,7 +132,7 @@ retry: */ if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET)) dbgp_breath(); - + /* If I get a NACK reissue the transmission */ if (lpid == USB_PID_NAK) { if (--loop > 0) goto retry; @@ -179,7 +179,7 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, un pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_OUT); - + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl |= DBGP_OUT; @@ -213,12 +213,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, uns pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_IN); - + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl &= ~DBGP_OUT; ctrl |= DBGP_GO; - + write32(&ehci_debug->address, addr); write32(&ehci_debug->pids, pids); ret = dbgp_wait_until_done(ehci_debug, ctrl); @@ -234,7 +234,7 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size) return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_in, data, size); } -static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, +static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, int value, int index, void *data, int size) { unsigned pids, addr, ctrl; @@ -245,7 +245,7 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i read = (requesttype & USB_DIR_IN) != 0; if (size > (read?DBGP_MAX_PACKET:0)) return -1; - + /* Compute the control message */ req.bRequestType = requesttype; req.bRequest = request; @@ -298,7 +298,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) loop = 2; write32(&ehci_regs->port_status[port - 1], portsc & ~(PORT_RWC_BITS | PORT_RESET)); - do { + do { dbgp_mdelay(delay); portsc = read32(&ehci_regs->port_status[port - 1]); delay_time += delay; @@ -395,7 +395,7 @@ try_next_port: set_debug_port(debug_port); goto try_next_time; } - return; + return; } /* Reset the EHCI controller */ @@ -492,7 +492,7 @@ try_next_port: USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, (void *)0, 0); if (ret < 0) { - dbgp_printk("Could not move attached device to %d.\n", + dbgp_printk("Could not move attached device to %d.\n", USB_DEBUG_DEVNUM); goto err; } @@ -525,7 +525,7 @@ try_next_port: info->devnum = devnum; info->endpoint_out = dbgp_endpoint_out; info->endpoint_in = dbgp_endpoint_in; - + return; err: /* Things didn't work so remove my claim */ diff --git a/src/lib/xmodem.c b/src/lib/xmodem.c index 465d6670a3..2d553bed03 100644 --- a/src/lib/xmodem.c +++ b/src/lib/xmodem.c @@ -143,7 +143,7 @@ int xmodemReceive(unsigned char *dest, int destsz) *p++ = c; } - if (xbuff[1] == (unsigned char)(~xbuff[2]) && + if (xbuff[1] == (unsigned char)(~xbuff[2]) && (xbuff[1] == packetno || xbuff[1] == (unsigned char)packetno-1) && check(crc, &xbuff[3], bufsz)) { if (xbuff[1] == packetno) { diff --git a/src/mainboard/a-trend/Kconfig b/src/mainboard/a-trend/Kconfig index f5a379f84d..7cb53924dd 100644 --- a/src/mainboard/a-trend/Kconfig +++ b/src/mainboard/a-trend/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_A_TREND - + source "src/mainboard/a-trend/atc-6220/Kconfig" source "src/mainboard/a-trend/atc-6240/Kconfig" diff --git a/src/mainboard/abit/Kconfig b/src/mainboard/abit/Kconfig index 982cc9eee7..1f704b84c3 100644 --- a/src/mainboard/abit/Kconfig +++ b/src/mainboard/abit/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_ABIT - + source "src/mainboard/abit/be6-ii_v2_0/Kconfig" endchoice diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 0c0c8f0c31..bc84dc0373 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index adb1786678..0e7bbb66e7 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -19,7 +19,7 @@ static void init(struct device *dev) { printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__); if (nicirq) { - printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", __func__, bus, devfn, nicirq); nic = dev_find_slot(bus, devfn); if (! nic){ diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 813b009471..958cf3196c 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -35,7 +35,7 @@ static inline unsigned int fls(unsigned int x) return r; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -86,7 +86,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr = rdmsr(0x20000019); msr.hi = 0x18000108; msr.lo = 0x696332a3; - wrmsr(0x20000019, msr); + wrmsr(0x20000019, msr); } @@ -122,7 +122,7 @@ static void main(unsigned long bist) }; SystemPreInit(); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -134,7 +134,7 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); msr_init(); diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl index b2474e2a20..77958b2063 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl @@ -4,17 +4,17 @@ //AMD8111 Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) @@ -34,16 +34,16 @@ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - + Store (0x00, ^DNCG) - + } - If (LNot (PICF)) { - Return (PICM) + If (LNot (PICF)) { + Return (PICM) } Else { - Return (APIC) + Return (APIC) } } @@ -57,7 +57,7 @@ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) Field (PIRQ, ByteAcc, Lock, Preserve) { - PIBA, 8, + PIBA, 8, PIDC, 8 } /* @@ -144,7 +144,7 @@ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } }) - + Name (PICM, Package (0x0C) { Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 9d93e34e92..9e952c80bd 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -5,7 +5,7 @@ Device (ISA) { - /* lpc 0x00040000 */ + /* lpc 0x00040000 */ Method (_ADR, 0, NotSerialized) { Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) @@ -15,11 +15,11 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, + , 1, ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), + Offset (0x01), Z001, 3, // Serial Port A Range SAEN, 1, // Serial Post A Enabled Z002, 3, // Serial Port B Range @@ -106,7 +106,7 @@ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error }) Method (_CRS, 0, NotSerialized) @@ -134,7 +134,7 @@ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS }) - // Read the Video Memory length + // Read the Video Memory length CreateDWordField (BUF0, 0x14, CLEN) CreateDWordField (BUF0, 0x10, CBAS) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl index e209665e48..172f0bf9d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,60 +19,60 @@ Name (APIC, Package (0x14) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - + //Cypress Slot A - PIRQ BCDA Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, //Cypress Slot B - PIRQ CDAB Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, //Cypress Slot C - PIRQ DABC Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, //Cypress Slot D - PIRQ ABCD Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) @@ -100,15 +100,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl index 163c0f6061..8b8bc9fab9 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl index 75ef72343a..e5cfe3c951 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl index 001d45b0fe..ce85502296 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl @@ -1,4 +1,4 @@ -// AMD8151 +// AMD8151 Device (AGPB) { Method (_ADR, 0, NotSerialized) @@ -8,16 +8,16 @@ Name (APIC, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index c2b8e8c7b3..f132ec727c 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -4,7 +4,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index b9742b4a46..c1748697f4 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8132 # the on/off keyword is mandatory @@ -56,7 +56,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -120,7 +120,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl index ee87023ff8..a549d70297 100644 --- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah/dsdt.asl @@ -100,11 +100,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } #include "acpi/pci0_hc.asl" - + } Device (PCI1) { @@ -138,7 +138,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Notify (\_SB.PCI0.PG0B, 0x02) } - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { Notify (\_SB.PCI0.PG0A, 0x02) } @@ -183,14 +183,14 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), + Offset (0x10), FLG0, 8 } OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, + , 4, IRQR, 1 } diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index d4c6622847..6b6107070b 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -30,7 +30,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ // 3=Workstation,4=Enterprise Server, 7=Performance Server fadt->preferred_pm_profile=0x03; fadt->sci_int=9; - // disable system management mode by setting to 0: + // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe0_blk_len = 4; fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->century = 0; // 0x7f to make rtc alrm work fadt->iapc_boot_arch = 0x3; // See table 5-11 fadt->flags = 0x25; - + fadt->res2 = 0; fadt->reset_reg.space_id = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 436044e69a..3674ff0076 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -15,7 +15,7 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -27,7 +27,7 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -88,17 +88,17 @@ void get_bus_conf(void) get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; - + m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } - + get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -209,8 +209,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index d872b0a0db..637f980055 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -13,11 +13,11 @@ #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -50,7 +50,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - + m = sysconf.mb; /* Align the table to be 16 byte aligned. */ @@ -62,25 +62,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; - + { device_t dev; dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); @@ -126,11 +126,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) j++; } - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2b2f65c39b..fe2f9440e2 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -101,8 +101,8 @@ static void *smp_write_config_table(void *v) } } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt index 41988c8ede..685cd7a2ce 100644 --- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt +++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt @@ -6,7 +6,7 @@ At this time, For acpi support We got The developers need to change for different MB -Change dsdt.asl, according to MB layout +Change dsdt.asl, according to MB layout pci1, pci2, pci3, pci4, ...., pci8 if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c @@ -17,7 +17,7 @@ Change acpi_tables.c Regarding pci bridge apic and pic need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c -About other chipsets, need to develop their special asl such as +About other chipsets, need to develop their special asl such as ck804.asl --- NB ck804 bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000 @@ -27,4 +27,4 @@ use c to delele hex file yhlu 09/18/2005 - + diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 9b19503360..be11b689da 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -143,7 +143,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -207,7 +207,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 00d4b3b21a..6fcaa90875 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -107,7 +107,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -201,21 +201,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl index 582ef97621..791454c190 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl index 583e945740..28fe5f45a3 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl index fd7224d17a..93abb7f520 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/arima/Kconfig b/src/mainboard/arima/Kconfig index d1979b00a2..8895433a55 100644 --- a/src/mainboard/arima/Kconfig +++ b/src/mainboard/arima/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARIMA - + source "src/mainboard/arima/hdama/Kconfig" endchoice diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index 0db327c5c6..a6f0d558a8 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -12,8 +12,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -32,7 +32,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -51,8 +51,8 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -77,10 +77,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel0[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -109,10 +109,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel1[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index a812814782..0ab47a4f0b 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -6,14 +6,14 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on # PCIX bridge ## On board NIC A #chip drivers/generic/generic - # device pci 3.0 on + # device pci 3.0 on # irq 0 = 0x13 # end #end @@ -31,7 +31,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 4 #chip drivers/generic/generic # device pci 2.0 on @@ -40,7 +40,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 0.1 on end # IOAPIC device pci 1.0 on # PCIX bridge @@ -61,7 +61,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 1.1 on end # IOAPIC end @@ -82,7 +82,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 6 (correct?) #chip drivers/generic/generic # device pci 4.0 on @@ -91,13 +91,13 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x12 # irq 3 = 0x13 # end - #end + #end end # LPC bridge device pci 1.0 on chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -124,7 +124,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end # IDE @@ -132,8 +132,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on # System Management chip drivers/generic/generic #phillips pca9545 smbus mux - device i2c 70 on - # analog_devices adm1026 + device i2c 70 on + # analog_devices adm1026 chip drivers/generic/generic device i2c 2c on end end @@ -147,33 +147,33 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end + device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end device pci 1.5 off end # AC97 Audio device pci 1.6 on end # AC97 Modem register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end # LDT1 device pci 18.0 on end # LDT2 device pci 18.1 on end @@ -188,6 +188,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index 2ca98066d0..ba516f88e2 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 643dfabd5d..11b8063f95 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -4,7 +4,7 @@ #include <string.h> #include <stdint.h> #include <cpu/x86/lapic.h> -#include <arch/cpu.h> +#include <arch/cpu.h> #include <arch/io.h> #define HT_INIT_CONTROL 0x6c @@ -26,7 +26,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -57,7 +57,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) } } } - + static unsigned node_link_to_bus(unsigned node, unsigned link) { device_t dev; @@ -79,12 +79,12 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) + if ((dst_node == node) && (dst_link == link)) { return bus_base; } diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig index 5f1a6e906f..e95e56a055 100644 --- a/src/mainboard/artecgroup/Kconfig +++ b/src/mainboard/artecgroup/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARTEC_GROUP - + source "src/mainboard/artecgroup/dbe61/Kconfig" endchoice diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 33c9237836..73c777c9c4 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -27,7 +27,7 @@ struct spd_entry { /* Save space by using a short list of SPD values used by Geode LX Memory init */ /* 128MB */ -const struct spd_entry spd_table [] = +const struct spd_entry spd_table [] = { {SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ {SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c index 0c0d3467a2..ce15efd1a8 100644 --- a/src/mainboard/asus/a8n_e/irq_tables.c +++ b/src/mainboard/asus/a8n_e/irq_tables.c @@ -67,7 +67,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v, sum = 0; int i; - /* get_bus_conf() will find out all bus num and APIC that share with + /* get_bus_conf() will find out all bus num and APIC that share with * mptable.c and mptable.c. */ get_bus_conf(); diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index de957a8f78..e7e6bb40f7 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -71,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ec90f8010..f571bae472 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) - * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 46a6c1f6a4..1862bc993f 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index fd4d42d378..493f1d6c8f 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -60,7 +60,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) - + External (BUSN) External (MMIO) External (PCIO) @@ -95,7 +95,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } /* PCI Routing Table */ @@ -185,7 +185,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) /* two LSB bits are blink rate */ LEDR, 2, } - + /* PS/2 keyboard (seems to be important for WinXP install) */ Device (KBD) { diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 04a5206437..ea9870798c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) - * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index a5415a2bfe..29d706c62a 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/intel/i82810 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video # device pci 1.0 on end diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 3bd0d7195f..259b0e4938 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x7120, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x89, /* u8 checksum , this has to set to some value + 0x89, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ diff --git a/src/mainboard/azza/Kconfig b/src/mainboard/azza/Kconfig index f7109ecbf7..0c0be97d46 100644 --- a/src/mainboard/azza/Kconfig +++ b/src/mainboard/azza/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_AZZA - + source "src/mainboard/azza/pt-6ibd/Kconfig" endchoice diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 73bdfc20d8..85fad0a4f1 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_BIOSTAR - + source "src/mainboard/biostar/m6tba/Kconfig" endchoice diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig index bf956ecdb3..d7406c0b45 100644 --- a/src/mainboard/broadcom/Kconfig +++ b/src/mainboard/broadcom/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_BROADCOM - + source "src/mainboard/broadcom/blast/Kconfig" endchoice diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index a9cabe6bea..d06c590bf8 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm5780 # HT2000 device pci 0.0 on end # PXB 1 0x0130 @@ -95,7 +95,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.10 on #RTC io 0x60 = 0x70 io 0x62 = 0x72 - end + end end end device pci 1.3 on end # WDTimer 0x0238 @@ -110,7 +110,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 9d1a4b1bf0..06f42f4092 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -21,7 +21,7 @@ unsigned char bus_bcm5785_1_1 = 9; unsigned apicid_bcm5785[3]; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -115,9 +115,9 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - for(i=0;i<3;i++) + for(i=0;i<3;i++) apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 3f6f73893e..406419d6d8 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -16,7 +16,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -64,22 +64,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_bcm5785_0; pirq->rtr_devfn = (sysconf.sbdn<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1166; pirq->rtr_device = 0x0036; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c pirq_info = (void *) ( &pirq->checksum + 1); @@ -87,11 +87,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 8a1b133bfb..d24630844e 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -72,12 +72,12 @@ static void *smp_write_config_table(void *v) } } } - + } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_bcm5785[0], 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_bcm5785[0], 0x4); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_bcm5785[0], 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_bcm5785[0], 0xd); -//IDE +//IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE @@ -97,14 +97,14 @@ static void *smp_write_config_table(void *v) //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); - + //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); for(i=0;i<3;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // } - + /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ @@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v) } -//pci slot (on bcm5785) +//pci slot (on bcm5785) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // } -//onboard ati +//onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 @@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v) } -// Second PCI-E x8 +// Second PCI-E x8 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // } diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c index 438605c701..71f0bba010 100644 --- a/src/mainboard/broadcom/blast/resourcemap.c +++ b/src/mainboard/broadcom/blast/resourcemap.c @@ -119,7 +119,7 @@ static void setup_blast_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -144,7 +144,7 @@ static void setup_blast_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -181,7 +181,7 @@ static void setup_blast_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -200,7 +200,7 @@ static void setup_blast_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_blast_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -252,8 +252,8 @@ static void setup_blast_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 35823bd47c..13f5f97414 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -3,7 +3,7 @@ #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -75,7 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // post_code(0x33); - + uart_init(); // post_code(0x34); @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_blast_resource_map(); - + #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 +#if 0 int i; for(i=4;i<8;i++) { change_i2c_mux(i); diff --git a/src/mainboard/compaq/Kconfig b/src/mainboard/compaq/Kconfig index 160048f30f..c2bbb57120 100644 --- a/src/mainboard/compaq/Kconfig +++ b/src/mainboard/compaq/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_COMPAQ - + source "src/mainboard/compaq/deskpro_en_sff_p600/Kconfig" endchoice diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c index 2ea3db32ea..45315618b7 100644 --- a/src/mainboard/dell/s1850/debug.c +++ b/src/mainboard/dell/s1850/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,7 +215,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -228,7 +228,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -248,7 +248,7 @@ void show_dram_slots(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + status = smbus_read_byte(device, 0); if (status < 0) { print_debug("bad device: "); @@ -272,7 +272,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -280,7 +280,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -288,4 +288,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index ab95e54a7b..bd7b3a3773 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,23 +1,23 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/nsc/pc8374 device pnp 2e.0 off end device pnp 2e.1 off end device pnp 2e.2 off end - device pnp 2e.3 on + device pnp 2e.3 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -30,22 +30,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x8a07030b" register "pirq_e_h" = "0x85808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c index 8b4773df66..1f56ed30b9 100644 --- a/src/mainboard/dell/s1850/irq_tables.c +++ b/src/mainboard/dell/s1850/irq_tables.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. + * Copyright (C) by the coreboot pirq tool. + * This file was programatically generated. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c index c7fd52af3e..4cdd0f1e7b 100644 --- a/src/mainboard/dell/s1850/mptable.c +++ b/src/mainboard/dell/s1850/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 199c6ea5d5..07fbef282d 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static inline void ibfzero(void) { - while(inb(ipmicsr) & (1<<IBF)) + while(inb(ipmicsr) & (1<<IBF)) ; } static inline void clearobf(void) @@ -75,7 +75,7 @@ static inline void clearobf(void) static inline void waitobf(void) { - while((inb(ipmicsr) & (1<<OBF)) == 0) + while((inb(ipmicsr) & (1<<OBF)) == 0) ; } /* quite possibly the stupidest interface ever designed. */ @@ -162,8 +162,8 @@ static void main(unsigned long bist) u32 l; int do_reset; /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -192,9 +192,9 @@ static void main(unsigned long bist) 0, }; - /* using SerialICE, we've seen this basic reset sequence on the dell. + /* using SerialICE, we've seen this basic reset sequence on the dell. * we don't understand it as it uses undocumented registers, but - * we're going to clone it. + * we're going to clone it. */ /* enable a hidden device. */ b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); @@ -217,11 +217,11 @@ static void main(unsigned long bist) b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); b &= ~0x8; pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - + /* set up LPC bridge bits, some of which reply on undocumented * registers */ - + b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); b |= 4; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); @@ -244,9 +244,9 @@ static void main(unsigned long bist) w = inw(0x866); outw(w|2, 0x866); -#if 0 +#if 0 /*seriaice shows - dell does this so leave it here so I don't forget + dell does this so leave it here so I don't forget */ /* SMBUS */ pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); @@ -260,7 +260,7 @@ static void main(unsigned long bist) b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); b |= 2; pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - + /* ?? */ l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); do_reset = l & 0x8000000; @@ -334,7 +334,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 @@ -345,7 +345,7 @@ static void main(unsigned long bist) // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 1 // temporarily disabled +#if 1 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -357,8 +357,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c index 9827120056..7ef9ce163b 100644 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ b/src/mainboard/dell/s1850/s1850_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } static void mainboard_set_ich5(void) @@ -28,8 +28,8 @@ static void mainboard_set_ich5(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. + * dell settings via lspci + * Note that they leave SMBUS disabled -- 8f6f. * we leave it enabled and visible in config space -- 8f66 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); @@ -38,7 +38,7 @@ static void mainboard_set_ich5(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports + /* factory config from IO ports * It has a few more things enabled than default! */ outl(0x1ae0f183, 0x880); diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c index 50e9e6e7b0..43f4029b5e 100644 --- a/src/mainboard/dell/s1850/watchdog.c +++ b/src/mainboard/dell/s1850/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig index 7c8fb1164e..7e115fc402 100644 --- a/src/mainboard/digitallogic/Kconfig +++ b/src/mainboard/digitallogic/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_DIGITAL_LOGIC - + source "src/mainboard/digitallogic/adl855pc/Kconfig" source "src/mainboard/digitallogic/msm586seg/Kconfig" source "src/mainboard/digitallogic/msm800sev/Kconfig" diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 5365b3f538..6b52633382 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/intel/i855 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end device pci 1.0 on end chip southbridge/intel/i82801dx @@ -51,7 +51,7 @@ chip northbridge/intel/i855 end end end - device apic_cluster 0 on + device apic_cluster 0 on chip cpu/intel/socket_mPGA479M device apic 0 on end end diff --git a/src/mainboard/digitallogic/adl855pc/irq_tables.c b/src/mainboard/digitallogic/adl855pc/irq_tables.c index f3978d5e81..8b4352d25a 100644 --- a/src/mainboard/digitallogic/adl855pc/irq_tables.c +++ b/src/mainboard/digitallogic/adl855pc/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 731e681253..a137a3fd6f 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -15,7 +15,7 @@ #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -45,7 +45,7 @@ void main(unsigned long bist) init_timer(); #endif } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -66,7 +66,7 @@ void main(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); - } + } #if 0 dump_pci_devices(); @@ -76,7 +76,7 @@ void main(unsigned long bist) ram_check(0x00000000, msr.lo+(msr.hi<<32)); // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB + // Check 16MB of memory @ 2GB ram_check(0x80000000, 0x81000000); #endif } diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb index 05067ca632..1ccf39f5b8 100644 --- a/src/mainboard/digitallogic/msm586seg/devicetree.cb +++ b/src/mainboard/digitallogic/msm586seg/devicetree.cb @@ -1,5 +1,5 @@ chip cpu/amd/sc520 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end device pci 12.0 on end # enet device pci 14.0 on end # 69000 diff --git a/src/mainboard/digitallogic/msm586seg/irq_tables.c b/src/mainboard/digitallogic/msm586seg/irq_tables.c index 9b49747ead..22d5820a62 100644 --- a/src/mainboard/digitallogic/msm586seg/irq_tables.c +++ b/src/mainboard/digitallogic/msm586seg/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index fefe553de3..2361059a7d 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -14,10 +14,10 @@ static void irqdump(void) int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, + 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, + 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, + 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, -1}; mmcr = (void *) 0xfffef000; @@ -37,7 +37,7 @@ static void enable_dev(struct device *dev) //volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; - /* msm586seg has this register set to a weird value. + /* msm586seg has this register set to a weird value. * follow the board, not the manual! */ @@ -47,7 +47,7 @@ static void enable_dev(struct device *dev) /* from fuctory bios */ /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet + * for hard drive, and serial, but not for ethernet */ /* just do what they say and nobody gets hurt. */ mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE; @@ -78,7 +78,7 @@ static void enable_dev(struct device *dev) printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22); /* The following block has NOT proven sufficient to get - * the VGA hardware to talk to us + * the VGA hardware to talk to us */ /* let's set some mmcr stuff per the BIOS settings */ mmcr->dbctl.dbctl = 0x10; @@ -100,20 +100,20 @@ static void enable_dev(struct device *dev) */ mmcr->sysmap.adddecctl = 0x10; - /* VGA now talks to us, so this adddecctl was the trick. - * still no interrupts from enet. - * Let's try fixing the piodata stuff, as there may be + /* VGA now talks to us, so this adddecctl was the trick. + * still no interrupts from enet. + * Let's try fixing the piodata stuff, as there may be * some wire there not documented. */ mmcr->pio.data31_16 = 0xffbf; /* also, our sl?picmode needs to match fuctory bios */ mmcr->pic.sl1picmode = 0x80; mmcr->pic.sl2picmode = 0x0; - /* and, finally, they do set gp5imap and we don't. + /* and, finally, they do set gp5imap and we don't. */ mmcr->pic.gp5imap = 0xd; /* remaining problem: almost certainly, the irq table is bogus - * NO SHOCK as it came from fuctory bios. + * NO SHOCK as it came from fuctory bios. * but let's try these 4 changes for now and see what shakes. */ /* still not interrupts. */ diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 2035993be8..ae964fea93 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -74,7 +74,7 @@ static inline void irqinit(void){ /* these values taken from the msm board itself. * and they cause the board to not even come out of calibrating_delay_loop * if you can believe it. Our problem right now is no IDE or serial interrupts - * So we'll try to put interrupts in, one at a time. IDE first. + * So we'll try to put interrupts in, one at a time. IDE first. */ cp = (volatile unsigned char *) 0xfffefd00; *cp = 0x11; @@ -179,9 +179,9 @@ static void main(unsigned long bist) print_err("HI THERE!\n"); // sizemem(); staticmem(); - print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); + print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); print_err("\n"); - + // while(1) print_err("STATIC MEM DONE\n"); outb(0xee, 0x80); @@ -198,18 +198,18 @@ static void main(unsigned long bist) "jnz 1b\n\t" : : "a" (0), "D" (0), "c" (1024*1024) - ); - - + ); + + #endif - + #if 0 dump_pci_devices(); #endif #if 0 dump_pci_device(PCI_DEV(0, 0, 0)); #endif - + #if 0 print_err("RAM CHECK!\n"); // Check 16MB of memory @ 0 @@ -223,10 +223,10 @@ static void main(unsigned long bist) #if 1 { volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; - volatile unsigned char *dst = (unsigned char *) 0x4000; + volatile unsigned char *dst = (unsigned char *) 0x4000; for(i = 0; i < 0x20000; i++) { /* - print_err("Set dst "); print_err_hex32((unsigned long) dst); + print_err("Set dst "); print_err_hex32((unsigned long) dst); print_err(" to "); print_err_hex32(*src); print_err("\n"); */ *dst = *src; @@ -244,10 +244,10 @@ static void main(unsigned long bist) "jmp *%%edi\n\t" : : "a" (0x4000) - ); - + ); + print_err("Oh dear, I'm afraid it didn't work...\n"); - + while(1); #endif } diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 9636dee678..6890e83327 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/lx - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -57,7 +57,7 @@ chip northbridge/amd/lx io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 4598e89ad9..379f5517bc 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -93,7 +93,7 @@ void main(unsigned long bist) print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); - /* we are finding the return does not work on this board. Explicitly call the label that is + /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ void done_cache_as_ram_main(void); diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb index 2e0c8161fc..7e55bca54d 100644 --- a/src/mainboard/eaglelion/5bcm/devicetree.cb +++ b/src/mainboard/eaglelion/5bcm/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/gx1 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5530 device pci 12.0 on diff --git a/src/mainboard/eaglelion/5bcm/irq_tables.c b/src/mainboard/eaglelion/5bcm/irq_tables.c index d58662365d..bcc53b4a26 100644 --- a/src/mainboard/eaglelion/5bcm/irq_tables.c +++ b/src/mainboard/eaglelion/5bcm/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 633c23cd5a..11fe81250a 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -28,11 +28,11 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - + cs5530_enable_rom(); sdram_init(); - + /* Check all of memory */ #if 0 ram_check(0x00000000, msr.lo); diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index 2e18d790c9..471cc331e1 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -1,5 +1,5 @@ chip mainboard/emulation/qemu-x86 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/intel/i82371eb # southbridge diff --git a/src/mainboard/emulation/qemu-x86/irq_tables.c b/src/mainboard/emulation/qemu-x86/irq_tables.c index 8402602abd..27a48ec5ff 100644 --- a/src/mainboard/emulation/qemu-x86/irq_tables.c +++ b/src/mainboard/emulation/qemu-x86/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index be17698d7d..7ab02d93c4 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -25,8 +25,8 @@ static void qemu_init(device_t dev) */ pc_keyboard_init(0); - /* The PIRQ table is not working well for interrupt routing purposes. - * so we'll just set the IRQ directly. + /* The PIRQ table is not working well for interrupt routing purposes. + * so we'll just set the IRQ directly. */ printk(BIOS_INFO, "setting ethernet\n"); pci_assign_irqs(0, 3, enetIrqs); diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index 1d6eeded11..0543815a6d 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -17,10 +17,10 @@ static void main(void) { /* init_timer();*/ post_code(0x05); - + uart_init(); console_init(); - + //print_pci_devices(); //dump_pci_devices(); } diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index 483e3fc8a6..9323da7dd6 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_GIGABYTE - + source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index d08414f217..728c40caf9 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -14,7 +14,7 @@ config BOARD_GIGABYTE_GA_2761GXDK select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default gigabyte/ga_2761gxdk @@ -24,7 +24,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_GIGABYTE_GA_2761GXDK - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -36,7 +36,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_GIGABYTE_GA_2761GXDK config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_GIGABYTE_GA_2761GXDK @@ -76,7 +76,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_GIGABYTE_GA_2761GXDK config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_GIGABYTE_GA_2761GXDK @@ -86,12 +86,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_GIGABYTE_GA_2761GXDK config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_GIGABYTE_GA_2761GXDK config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_GIGABYTE_GA_2761GXDK diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 2790427080..b36261e533 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -17,17 +17,17 @@ config BOARD_GIGABYTE_M57SLI select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string - default gigabyte/m57sli + default gigabyte/m57sli depends on BOARD_GIGABYTE_M57SLI config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_GIGABYTE_M57SLI - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -39,7 +39,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_GIGABYTE_M57SLI config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_GIGABYTE_M57SLI @@ -79,7 +79,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_GIGABYTE_M57SLI config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_GIGABYTE_M57SLI @@ -89,12 +89,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_GIGABYTE_M57SLI config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_GIGABYTE_M57SLI config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_GIGABYTE_M57SLI diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc index 00075834e1..36be8066fa 100644 --- a/src/mainboard/gigabyte/m57sli/Makefile.inc +++ b/src/mainboard/gigabyte/m57sli/Makefile.inc @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c index 1bd302271a..60b041a953 100644 --- a/src/mainboard/gigabyte/m57sli/acpi_tables.c +++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -47,14 +47,14 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned int gsi_base = 0x18; extern unsigned char bus_mcp55[8]; extern unsigned apicid_mcp55; - + unsigned sbdn; struct resource *res; device_t dev; get_bus_conf(); sbdn = sysconf.sbdn; - + /* Create all subtables for processors. */ current = acpi_create_madt_lapics(current); @@ -84,7 +84,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 28f47597e9..8429286bc7 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/gigabyte/m57sli/cmos.layout +++ b/src/mainboard/gigabyte/m57sli/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index c9b969de0e..a8c4242bff 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -53,7 +53,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) External (HCLK) External (SBDN) External (HCDN) - + Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () @@ -274,7 +274,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) IRQNoFlags () {7} }) Return (BUF1) @@ -291,7 +291,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) IO (Decode16, 0x0778, 0x0778, 0x01, 0x04) IRQNoFlags() {7} DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3} diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index 4d381a6e8e..cad922f16a 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -39,7 +39,7 @@ unsigned apicid_mcp55; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -51,7 +51,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -62,7 +62,7 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned bus_type[256]; +unsigned bus_type[256]; @@ -95,13 +95,13 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0;i<256; i++) { bus_type[i] = 0; } bus_type[0] = 1; //pci - + bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_type[bus_mcp55[0]] = 1; @@ -139,8 +139,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 93e6c274c9..3aad7e281f 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -32,7 +32,7 @@ extern unsigned char bus_mcp55[8]; //1 extern unsigned apicid_mcp55; -extern unsigned bus_type[256]; +extern unsigned bus_type[256]; @@ -94,7 +94,7 @@ static void *smp_write_config_table(void *v) } } - /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); /* ISA ints are edge-triggered, and usually originate from the ISA bus, @@ -122,7 +122,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin)) - PCI_INT(0,sbdn+1,1, 10); /* SMBus */ + PCI_INT(0,sbdn+1,1, 10); /* SMBus */ PCI_INT(0,sbdn+2,0, 22); /* USB */ PCI_INT(0,sbdn+2,1, 23); /* USB */ PCI_INT(0,sbdn+4,0, 21); /* IDE */ @@ -144,8 +144,8 @@ static void *smp_write_config_table(void *v) } /* On bus 1: the PCI bus slots... - pyhsical PCI slots are j = 7,8 - FireWire is j = 10 + pyhsical PCI slots are j = 7,8 + FireWire is j = 10 */ k=2; for(i=0; i<4; i++){ diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c index 847cd86e65..43ff3ed11a 100644 --- a/src/mainboard/gigabyte/m57sli/resourcemap.c +++ b/src/mainboard/gigabyte/m57sli/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 1e3bee8845..3f2f5e6f53 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -39,7 +39,7 @@ #endif #define DBGP_DEFAULT 7 - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -142,13 +142,13 @@ static void sio_setup(void) uint8_t byte; byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) (0xa<<3)|5, (0xa<<3)|7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; @@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); uart_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -281,7 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); + enable_smbus(); /* all ap stopped? */ diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig index f216a7e58d..36857e5f87 100644 --- a/src/mainboard/hp/Kconfig +++ b/src/mainboard/hp/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_HP - + source "src/mainboard/hp/dl145_g3/Kconfig" source "src/mainboard/hp/e_vectra_p2706t/Kconfig" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 2e4d4109df..799e3fa7e1 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; diff --git a/src/mainboard/ibm/Kconfig b/src/mainboard/ibm/Kconfig index d3d4f292e1..d9d1774532 100644 --- a/src/mainboard/ibm/Kconfig +++ b/src/mainboard/ibm/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_IBM - + source "src/mainboard/ibm/e325/Kconfig" source "src/mainboard/ibm/e326/Kconfig" diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb index 4db7c0005e..1b63301c09 100644 --- a/src/mainboard/ibm/e325/devicetree.cb +++ b/src/mainboard/ibm/e325/devicetree.cb @@ -18,7 +18,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -45,7 +45,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end @@ -54,7 +54,7 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 off end device pci 1.6 off end end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT2 device pci 18.1 on end device pci 18.2 on end @@ -68,7 +68,7 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c index a9e8d07166..e537b65ab1 100644 --- a/src/mainboard/ibm/e325/irq_tables.c +++ b/src/mainboard/ibm/e325/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c index b80347eb0c..85aafbf5a7 100644 --- a/src/mainboard/ibm/e325/resourcemap.c +++ b/src/mainboard/ibm/e325/resourcemap.c @@ -134,7 +134,7 @@ static void setup_ibm_e325_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ @@ -143,8 +143,8 @@ static void setup_ibm_e325_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0, // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, - PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, + PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, + PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0, @@ -153,19 +153,19 @@ static void setup_ibm_e325_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, + PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003, //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 * F1:0xCC i = 1 @@ -205,7 +205,7 @@ static void setup_ibm_e325_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -213,17 +213,17 @@ static void setup_ibm_e325_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, - PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, - PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, + PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, + PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, /* Config Base and Limit i Registers * F1:0xE0 i = 0 * F1:0xE4 i = 1 @@ -260,10 +260,10 @@ static void setup_ibm_e325_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, - PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, + PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; max = ARRAY_SIZE(register_values); diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 0200fcd040..7697450b0e 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_ibm_e325_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index a8576968cb..f1759dd81e 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -52,7 +52,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end @@ -63,12 +63,12 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c index a9e8d07166..e537b65ab1 100644 --- a/src/mainboard/ibm/e326/irq_tables.c +++ b/src/mainboard/ibm/e326/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c index a37496879b..98fdcc0ec6 100644 --- a/src/mainboard/ibm/e326/resourcemap.c +++ b/src/mainboard/ibm/e326/resourcemap.c @@ -134,7 +134,7 @@ static void setup_ibm_e326_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ @@ -143,8 +143,8 @@ static void setup_ibm_e326_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0, // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, - PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, + PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, + PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0, @@ -153,19 +153,19 @@ static void setup_ibm_e326_resource_map(void) //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, + PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003, //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0, //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, - PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, - PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0, + PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0, + PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 * F1:0xCC i = 1 @@ -205,7 +205,7 @@ static void setup_ibm_e326_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -213,17 +213,17 @@ static void setup_ibm_e326_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, - PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, - PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, - PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010, + PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33, + PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0, + PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0, /* Config Base and Limit i Registers * F1:0xE0 i = 0 * F1:0xE4 i = 1 @@ -260,10 +260,10 @@ static void setup_ibm_e326_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, - PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, - PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103, + PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, + PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, }; int max; max = ARRAY_SIZE(register_values); diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 527db2fa3e..0b38ec78fa 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_ibm_e326_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/iei/nova4899r/irq_tables.c b/src/mainboard/iei/nova4899r/irq_tables.c index 5886c20077..7893e1032f 100644 --- a/src/mainboard/iei/nova4899r/irq_tables.c +++ b/src/mainboard/iei/nova4899r/irq_tables.c @@ -118,7 +118,7 @@ const struct irq_routing_table intel_irq_routing_table = { .slot = 0x2, }, */ - + /* * Definition for "slot#2". There is no real slot, * the network device is soldered... diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index 5180b84cf1..2678c149b1 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -13,7 +13,7 @@ config BOARD_IEI_PCISA_LX_800_R10 config MAINBOARD_DIR string - default iei/pcisa-lx-800-r10 + default iei/pcisa-lx-800-r10 depends on BOARD_IEI_PCISA_LX_800_R10 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl index 93e4b87fee..de2ec481fb 100644 --- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl index b3b60d6ece..931fbfdeb4 100644 --- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 3d1ad0ea29..d321771c0a 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -28,7 +28,7 @@ Device (SLPB) Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) - + // Wake Name(_PRW, Package(){0x1d, 0x04}) } diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 7c5b9da429..0a7930a3cc 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -74,12 +74,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl index fb9d940955..fc79a35f61 100644 --- a/src/mainboard/intel/d945gclf/acpi/thermal.asl +++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl @@ -25,7 +25,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index b7f92114c5..afa695502f 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h index 90e8c27999..4e1432de69 100644 --- a/src/mainboard/intel/d945gclf/chip.h +++ b/src/mainboard/intel/d945gclf/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index e99c43d79b..9997584a54 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -1,6 +1,6 @@ # # This file is part of the coreboot project. -# +# # Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index af5f22b302..01a0bc67a5 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or @@ -25,7 +25,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller @@ -66,7 +66,7 @@ chip northbridge/intel/i945 device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47m15x diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 1b025994f0..bf57e74b21 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( // General Purpose Events //#include "acpi/gpe.asl" - + // mainboard specific devices #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c index fc4c508194..c07a24c399 100644 --- a/src/mainboard/intel/d945gclf/mainboard_smi.c +++ b/src/mainboard/intel/d945gclf/mainboard_smi.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 5d57f3d743..62850ebf1c 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index e3e5814d3e..45e9fb1341 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -105,7 +105,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_lpc47m15x(void) { device_t dev; - + dev=PNP_DEV(0x2e, LPC47M15X_SP1); pnp_enter_conf_state(dev); @@ -276,7 +276,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -286,8 +286,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -331,7 +331,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/intel/d945gclf/rtl8168.c b/src/mainboard/intel/d945gclf/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/intel/d945gclf/rtl8168.c +++ b/src/mainboard/intel/d945gclf/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 991fddf0e2..d04e79eafe 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -57,7 +57,7 @@ config MAX_CPUS int default 4 depends on BOARD_INTEL_EAGLEHEIGHTS - + config MAX_PHYSICAL_CPUS int default 2 diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb index 32f70e3e85..3a40899b29 100644 --- a/src/mainboard/intel/jarrell/devicetree.cb +++ b/src/mainboard/intel/jarrell/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/e7520 - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end device pci 00.1 on end device pci 01.0 on end - device pci 02.0 on + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 device pci 00.0 on end device pci 00.1 on end @@ -28,7 +28,7 @@ chip northbridge/intel/e7520 device pci 0c.0 on end end end - device pci 1f.0 on + device pci 1f.0 on chip superio/nsc/pc87427 device pnp 2e.0 off end device pnp 2e.2 on @@ -60,7 +60,7 @@ chip northbridge/intel/e7520 end device pci 1f.1 on end device pci 1f.2 off end - device pci 1f.3 on end + device pci 1f.3 on end device pci 1f.5 off end device pci 1f.6 off end register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index 7fb5a20dbb..1261e61046 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -21,7 +21,7 @@ static void mch_reset(void) value = inl(base); value |= (1 <<19); outl(value, base); - + /* Pull GPIO 19 low */ value = inl(base + 0x0c); value &= ~(1 << 19); @@ -38,7 +38,7 @@ static void mainboard_set_e7520_pll(unsigned bits) /* currently only handle the Jarrell/PC87427 case */ dev = PC87427_GPIO_DEV; - + pnp_set_logical_device(dev); gpio_index = pnp_read_iobase(dev, 0x60); @@ -66,7 +66,7 @@ static void mainboard_set_e7520_pll(unsigned bits) // mch_reset(); full_reset(); } - return; + return; } static void mainboard_set_e7520_leds(void) @@ -77,7 +77,7 @@ static void mainboard_set_e7520_leds(void) /* currently only handle the Jarrell/PC87427 case */ dev = PC87427_GPIO_DEV; - + pnp_set_logical_device(dev); /* enable */ @@ -88,17 +88,17 @@ static void mainboard_set_e7520_leds(void) /* Set auto mode for dimm leds and post */ outb(0xf0,0x2e); - outb(0x70,0x2f); + outb(0x70,0x2f); outb(0xf4,0x2e); - outb(0x30,0x2f); + outb(0x30,0x2f); outb(0xf5,0x2e); - outb(0x88,0x2f); + outb(0x88,0x2f); outb(0xf6,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf7,0x2e); - outb(0x90,0x2f); + outb(0x90,0x2f); outb(0xf8,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); /* Turn the leds off */ outb(0x00,0x88); @@ -106,12 +106,12 @@ static void mainboard_set_e7520_leds(void) /* Disable the ports */ outb(0xf5,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf7,0x2e); - outb(0x00,0x2f); + outb(0x00,0x2f); outb(0xf4,0x2e); - outb(0x00,0x2f); - - return; + outb(0x00,0x2f); + + return; } diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 73aa575540..1386c16183 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v) } } } - + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x08, 0x00); diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index d3f6c7a707..823519984e 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -51,8 +51,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) disable_watchdogs(); power_down_reset_check(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); ich5_watchdog_on(); #if 0 @@ -128,7 +128,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -138,9 +138,9 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - + #endif -#if 0 +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 90782d9fbf..f7c42caa78 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -29,17 +29,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -83,7 +83,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); - + } static void disable_watchdogs(void) @@ -114,12 +114,12 @@ static void ich5_watchdog_on(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -132,7 +132,7 @@ static void ich5_watchdog_on(void) /* clear bit 11 in TCO1_CNT to start watchdog */ value = inw(base + 0x08); value &= ~(1 << 11); - outw(value, base + 0x08); + outw(value, base + 0x08); print_debug("Watchdog ICH5 enabled\n"); } diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c index fd43eb693b..1188467f20 100644 --- a/src/mainboard/intel/xe7501devkit/acpi_tables.c +++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c @@ -38,21 +38,21 @@ unsigned long acpi_fill_madt(unsigned long current) device_t dev = 0; struct resource* res = NULL; - + // SJM: Hard-code CPU LAPIC entries for now // Use SourcePoint numbering of processors current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1); - + // Southbridge IOAPIC current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#2 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -60,7 +60,7 @@ unsigned long acpi_fill_madt(unsigned long current) irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#2 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current) // P64H2#1 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#1 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -104,7 +104,7 @@ unsigned long write_acpi_tables(unsigned long start) /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -115,10 +115,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout index 494af5bb61..baae5eb617 100644 --- a/src/mainboard/intel/xe7501devkit/cmos.layout +++ b/src/mainboard/intel/xe7501devkit/cmos.layout @@ -1,4 +1,4 @@ -# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: +# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: # "Error - Name is an invalid identifier in line" entries diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 30ae8e7a73..9ac2aee3f8 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,6 +1,6 @@ -// IOAPIC addresses determined by coreboot enumeration. +// IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. - + #define IOAPIC_ICH3 2 #define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010 #define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010 diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c index b329351b6b..951b08f5f8 100644 --- a/src/mainboard/intel/xe7501devkit/irq_tables.c +++ b/src/mainboard/intel/xe7501devkit/irq_tables.c @@ -35,17 +35,17 @@ const struct irq_routing_table intel_irq_routing_table = { // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 // Not sure why IRQ9 isn't routable (inherited from Tyan S2735) - + // INTA# INTB# INTC# INTD# // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu - + {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1 - + // P64H2#2 Bus A {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI // NOTE: Hotplug disabled on this bus - + // P64H2#2 Bus B {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23) {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24) @@ -61,7 +61,7 @@ const struct irq_routing_table intel_irq_routing_table = { {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21) // NOTE: Hotplug disabled on this bus - + // ICH-3 PCI bus {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11) diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index ee8299389d..2f48e83285 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -40,14 +40,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc) smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address // P64H2#2 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base); // P64H2#2 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -55,14 +55,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc) // P64H2#1 Bus A IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base); // P64H2#1 Bus B IOAPIC - dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); + dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); if (!dev) BUG(); // Config.lb error? res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -98,11 +98,11 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12) - + // P64H2#2 Bus A smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI - + // P64H2#1 Bus B smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21) @@ -117,13 +117,13 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20) // ICH-3 - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11) - + // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode? // Super I/O (ISA interrupts) diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 003a37f31c..99f00212c1 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -48,7 +48,7 @@ static void main(unsigned long bist) }, }; - if (bist == 0) + if (bist == 0) { // Skip this if there was a built in self test failure early_mtrr_init(); @@ -68,14 +68,14 @@ static void main(unsigned long bist) // If this is a warm boot, some initialization can be skipped - if (!bios_reset_detected()) + if (!bios_reset_detected()) { enable_smbus(); // dump_spd_registers(&memctrl[0]); // dump_smbus_registers(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - + // NOTE: ROMCC dies with an internal compiler error // if the following line is removed. print_debug("SDRAM is up.\n"); diff --git a/src/mainboard/iwill/Kconfig b/src/mainboard/iwill/Kconfig index cfb986f7eb..4a157954ab 100644 --- a/src/mainboard/iwill/Kconfig +++ b/src/mainboard/iwill/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_IWILL - + source "src/mainboard/iwill/dk8_htx/Kconfig" source "src/mainboard/iwill/dk8s2/Kconfig" source "src/mainboard/iwill/dk8x/Kconfig" diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl index 19011dc47b..38aaea1525 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl @@ -4,17 +4,17 @@ //AMD8111 Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) @@ -34,16 +34,16 @@ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - + Store (0x00, ^DNCG) - + } - If (LNot (PICF)) { - Return (PICM) + If (LNot (PICF)) { + Return (PICM) } Else { - Return (APIC) + Return (APIC) } } @@ -57,7 +57,7 @@ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) Field (PIRQ, ByteAcc, Lock, Preserve) { - PIBA, 8, + PIBA, 8, PIDC, 8 } /* @@ -144,7 +144,7 @@ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } }) - + Name (PICM, Package (0x0C) { Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl index 9d93e34e92..9e952c80bd 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl @@ -5,7 +5,7 @@ Device (ISA) { - /* lpc 0x00040000 */ + /* lpc 0x00040000 */ Method (_ADR, 0, NotSerialized) { Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) @@ -15,11 +15,11 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, + , 1, ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), + Offset (0x01), Z001, 3, // Serial Port A Range SAEN, 1, // Serial Post A Enabled Z002, 3, // Serial Port B Range @@ -106,7 +106,7 @@ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error }) Method (_CRS, 0, NotSerialized) @@ -134,7 +134,7 @@ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS }) - // Read the Video Memory length + // Read the Video Memory length CreateDWordField (BUF0, 0x14, CLEN) CreateDWordField (BUF0, 0x10, CBAS) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl index fbc0b30e42..dd82e38df5 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,60 +19,60 @@ Name (APIC, Package (0x14) { // Slot 3 - PIRQ BCDA ---- verified - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - + //Slot 4 - PIRQ CDAB ---- verified Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, //Onboard NIC 1 - PIRQ DABC Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, // NIC 2 - PIRQ ABCD -- verified Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, //SERIAL ATA - PIRQ BCDA Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } }) Method (_PRT, 0, NotSerialized) @@ -100,15 +100,15 @@ { // Slot A - PIRQ CDAB -- verfied Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl index 163c0f6061..8b8bc9fab9 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl index 75ef72343a..e5cfe3c951 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl index 001d45b0fe..ce85502296 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl @@ -1,4 +1,4 @@ -// AMD8151 +// AMD8151 Device (AGPB) { Method (_ADR, 0, NotSerialized) @@ -8,16 +8,16 @@ Name (APIC, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl index 95a4860c63..1035a7edfd 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl @@ -1,7 +1,7 @@ /* * Copyright 2006 AMD */ - + Device (HTXA) { /* HTX */ diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 05664e31a5..9113c5acc9 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -25,7 +25,7 @@ #if DUMP_ACPI_TABLES == 1 static void dump_mem(unsigned start, unsigned end) { - + unsigned i; print_debug("dump_mem:"); for(i=start;i<end;i++) { @@ -63,10 +63,10 @@ unsigned long acpi_fill_madt(unsigned long current) struct mb_sysconf_t *m; m = sysconf.mb; - + /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - + /* Write 8111 IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0); @@ -102,7 +102,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 - + switch (sysconf.hcid[i]) { case 1: d = 7; @@ -145,7 +145,7 @@ unsigned long acpi_fill_madt(unsigned long current) current, 0, 0, 2, 5 ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ - /* 2: APIC 2 */ + /* 2: APIC 2 */ /* 5 mean: 0101 --> Edige-triggered, Active high*/ @@ -185,7 +185,7 @@ unsigned long write_acpi_tables(unsigned long start) /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -196,7 +196,7 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index cfddca953d..734a93fe0a 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on end @@ -57,7 +57,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 on # GPIO2 io 0x07 = 0x08ff io 0x30 = 0x01ff diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl index ee87023ff8..a549d70297 100644 --- a/src/mainboard/iwill/dk8_htx/dsdt.asl +++ b/src/mainboard/iwill/dk8_htx/dsdt.asl @@ -100,11 +100,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } #include "acpi/pci0_hc.asl" - + } Device (PCI1) { @@ -138,7 +138,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Notify (\_SB.PCI0.PG0B, 0x02) } - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { Notify (\_SB.PCI0.PG0A, 0x02) } @@ -183,14 +183,14 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), + Offset (0x10), FLG0, 8 } OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, + , 4, IRQR, 1 } diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c index d4c6622847..6b6107070b 100644 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ b/src/mainboard/iwill/dk8_htx/fadt.c @@ -30,7 +30,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ // 3=Workstation,4=Enterprise Server, 7=Performance Server fadt->preferred_pm_profile=0x03; fadt->sci_int=9; - // disable system management mode by setting to 0: + // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe0_blk_len = 4; fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->century = 0; // 0x7f to make rtc alrm work fadt->iapc_boot_arch = 0x3; // See table 5-11 fadt->flags = 0x25; - + fadt->res2 = 0; fadt->reset_reg.space_id = 1; diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index d6141158ac..30b9e368ab 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -15,10 +15,10 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, // SB chain m + 0x0000ff0, // SB chain m 0x0000000, // HTX 0x0000100, // co processor on socket 1 // 0x0000ff0, @@ -27,7 +27,7 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -88,17 +88,17 @@ void get_bus_conf(void) get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; - + m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } - + get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -209,8 +209,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index d872b0a0db..637f980055 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -13,11 +13,11 @@ #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -50,7 +50,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - + m = sysconf.mb; /* Align the table to be 16 byte aligned. */ @@ -62,25 +62,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; - + { device_t dev; dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); @@ -126,11 +126,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) j++; } - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index 1b0cea02ab..061f3d8ece 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -101,8 +101,8 @@ static void *smp_write_config_table(void *v) } } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); @@ -149,14 +149,14 @@ static void *smp_write_config_table(void *v) //Slot 4 PCI-X 133/100/66 for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 } //Onboard NICS smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24 -//Onboard SATA +//Onboard SATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25 j = 0; diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c index 992510215c..d60c379669 100644 --- a/src/mainboard/iwill/dk8_htx/resourcemap.c +++ b/src/mainboard/iwill/dk8_htx/resourcemap.c @@ -143,7 +143,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -207,7 +207,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -252,7 +252,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index bddc5be7b0..af4c7b021c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -97,7 +97,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/ramtest.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/iwill/dk8_htx/ssdt2.asl b/src/mainboard/iwill/dk8_htx/ssdt2.asl index 582ef97621..791454c190 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt2.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt2.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt3.asl b/src/mainboard/iwill/dk8_htx/ssdt3.asl index 583e945740..28fe5f45a3 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt3.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt3.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt4.asl b/src/mainboard/iwill/dk8_htx/ssdt4.asl index fd7224d17a..93abb7f520 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt4.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt4.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl index 7592301902..5910e0fac2 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt5.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt5.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c index 75f1790abd..c3928f06ff 100644 --- a/src/mainboard/iwill/dk8s2/irq_tables.c +++ b/src/mainboard/iwill/dk8s2/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 8dc9dc0049..9a2fede061 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb index 77c96aa944..a275425751 100644 --- a/src/mainboard/iwill/dk8x/devicetree.cb +++ b/src/mainboard/iwill/dk8x/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on end @@ -28,15 +28,15 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.4 on end device pnp 2e.5 on end device pnp 2e.6 on end - device pnp 2e.7 on end - device pnp 2e.8 on end - device pnp 2e.9 on end - device pnp 2e.a on end + device pnp 2e.7 on end + device pnp 2e.8 on end + device pnp 2e.9 on end + device pnp 2e.a on end end end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end end @@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c index 1f35cbaef2..06b9cfb6b5 100644 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ b/src/mainboard/iwill/dk8x/irq_tables.c @@ -12,13 +12,13 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT * devices on the bus */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ @@ -28,7 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x00, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x00, /* u8 checksum , mod 256 checksum must give - * zero, will be corrected later + * zero, will be corrected later */ { diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 8dc9dc0049..9a2fede061 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl index a6043867b9..e466658dd4 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl index e86df0f973..c108d3f5b2 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/kontron/986lcd-m/acpi/platform.asl b/src/mainboard/kontron/986lcd-m/acpi/platform.asl index 39faa5d729..2e4223c19c 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/platform.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/platform.asl @@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -74,12 +74,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl index ad653bc5fc..d1774d4756 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/thermal.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/thermal.asl @@ -25,7 +25,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 55f02b10c2..6adff9f56b 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/kontron/986lcd-m/chip.h b/src/mainboard/kontron/986lcd-m/chip.h index 9d7e5968e1..800384aca4 100644 --- a/src/mainboard/kontron/986lcd-m/chip.h +++ b/src/mainboard/kontron/986lcd-m/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 18867e514d..2217cb365a 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -102,7 +102,7 @@ entries 968 1 e 2 ethernet1 969 1 e 2 ethernet2 970 1 e 2 ethernet3 - + #971 13 r 0 unused # coreboot config options: check sums diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index f1f771ad72..f4e6b9318a 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller @@ -46,7 +46,7 @@ chip northbridge/intel/i945 device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/winbond/w83627thg diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 653cd5b266..f06b225fe0 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( // General Purpose Events //#include "acpi/gpe.asl" - + //#include "acpi/thermal.asl" Scope (\_SB) { diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index c7f2ee00e4..28d6de18e1 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -104,7 +104,7 @@ struct fan_speed { u16 fan_speed; }; -// FANIN Target Speed Register +// FANIN Target Speed Register // FANIN = 337500 / RPM struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, @@ -119,7 +119,7 @@ struct temperature { }; struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } @@ -144,7 +144,7 @@ static void hwm_setup(void) sysfan_speed = FAN_SPEED_5625; //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) // sysfan_temperature = FAN_TEMPERATURE_30DEGC; - + // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit @@ -223,10 +223,10 @@ static void verb_setup(void) cim_verb_data_size = 0; } -// mainboard_enable is executed as first thing after +// mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(device_t dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* Install custom int15 handler for VGA OPROM */ diff --git a/src/mainboard/kontron/986lcd-m/mainboard_smi.c b/src/mainboard/kontron/986lcd-m/mainboard_smi.c index 6e4b5ad8d1..1aac802f2e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard_smi.c +++ b/src/mainboard/kontron/986lcd-m/mainboard_smi.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index dbf36bd51c..28c506f132 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2); @@ -158,11 +158,11 @@ static void *smp_write_config_table(void *v) return smp_next_mpe_entry(mc); } -/* MP table generation in coreboot is not very well designed; - * One of the issues is that it knows nothing about Virtual +/* MP table generation in coreboot is not very well designed; + * One of the issues is that it knows nothing about Virtual * Wire mode, which everyone uses since a decade or so. This * function fixes up our floating table. This spares us doing - * a half-baked fix of adding a new parameter to 200+ calls + * a half-baked fix of adding a new parameter to 200+ calls * to smp_write_floating_table() */ static void fixup_virtual_wire(void *v) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d29b23bde7..5c7724828e 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -21,7 +21,7 @@ /* Configuration of the i945 driver */ #define CHIPSET_I945GM 1 -/* Usually system firmware turns off system memory clock signals to +/* Usually system firmware turns off system memory clock signals to * unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock signals to * be disabled. If other similar mainboard occur, it would make sense @@ -107,7 +107,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); // COM4 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -119,7 +119,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_w83627thg(void) { device_t dev; - + dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_ext_func_mode(dev); @@ -194,7 +194,7 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); + dev=PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); @@ -249,7 +249,7 @@ static void rcba_config(void) * would essentially disable all three ethernet ports of the mainboard. * It's possible to rename the ports to achieve compatibility to the * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. + * interrupt routing information. * To avoid this, we enable (unused) port 6 and swap it with port 1 * in the case that ethernet port 1 is disabled. Since no devices * are connected to that port, we don't have to worry about interrupt @@ -413,7 +413,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -423,8 +423,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -470,7 +470,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/kontron/986lcd-m/rtl8168.c b/src/mainboard/kontron/986lcd-m/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/kontron/986lcd-m/rtl8168.c +++ b/src/mainboard/kontron/986lcd-m/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/kontron/kt690/acpi/routing.asl b/src/mainboard/kontron/kt690/acpi/routing.asl index 4b6b111f05..2315120310 100644 --- a/src/mainboard/kontron/kt690/acpi/routing.asl +++ b/src/mainboard/kontron/kt690/acpi/routing.asl @@ -92,38 +92,38 @@ Scope(\_SB) { /* Bus 0, Dev 0 - RS690 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){ 0x0002FFFF, 0, 0, 18 }, - Package(){ 0x0002FFFF, 1, 0, 19 }, - Package(){ 0x0002FFFF, 2, 0, 16 }, - Package(){ 0x0002FFFF, 3, 0, 17 }, + Package(){ 0x0002FFFF, 0, 0, 18 }, + Package(){ 0x0002FFFF, 1, 0, 19 }, + Package(){ 0x0002FFFF, 2, 0, 16 }, + Package(){ 0x0002FFFF, 3, 0, 17 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){ 0x0003FFFF, 0, 0, 19 }, - Package(){ 0x0003FFFF, 1, 0, 16 }, - Package(){ 0x0003FFFF, 2, 0, 17 }, - Package(){ 0x0003FFFF, 3, 0, 18 }, - + Package(){ 0x0003FFFF, 0, 0, 19 }, + Package(){ 0x0003FFFF, 1, 0, 16 }, + Package(){ 0x0003FFFF, 2, 0, 17 }, + Package(){ 0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){ 0x0004FFFF, 0, 0, 16 }, - Package(){ 0x0004FFFF, 1, 0, 17 }, - Package(){ 0x0004FFFF, 2, 0, 18 }, - Package(){ 0x0004FFFF, 3, 0, 19 }, + Package(){ 0x0004FFFF, 0, 0, 16 }, + Package(){ 0x0004FFFF, 1, 0, 17 }, + Package(){ 0x0004FFFF, 2, 0, 18 }, + Package(){ 0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){ 0x0005FFFF, 0, 0, 17 }, - Package(){ 0x0005FFFF, 1, 0, 18 }, - Package(){ 0x0005FFFF, 2, 0, 19 }, - Package(){ 0x0005FFFF, 3, 0, 16 }, + Package(){ 0x0005FFFF, 0, 0, 17 }, + Package(){ 0x0005FFFF, 1, 0, 18 }, + Package(){ 0x0005FFFF, 2, 0, 19 }, + Package(){ 0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){ 0x0006FFFF, 0, 0, 18 }, - Package(){ 0x0006FFFF, 1, 0, 19 }, - Package(){ 0x0006FFFF, 2, 0, 16 }, - Package(){ 0x0006FFFF, 3, 0, 17 }, + Package(){ 0x0006FFFF, 0, 0, 18 }, + Package(){ 0x0006FFFF, 1, 0, 19 }, + Package(){ 0x0006FFFF, 2, 0, 16 }, + Package(){ 0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){ 0x0007FFFF, 0, 0, 19 }, - Package(){ 0x0007FFFF, 1, 0, 16 }, + Package(){ 0x0007FFFF, 0, 0, 19 }, + Package(){ 0x0007FFFF, 1, 0, 16 }, Package(){ 0x0007FFFF, 2, 0, 17 }, Package(){ 0x0007FFFF, 3, 0, 18 }, diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 82c0b282e3..792a1430b7 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_LIPPERT - + source "src/mainboard/lippert/frontrunner/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 28c6af67a1..1386de9d77 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/amd/gx2 register "setupflash" = "0" #register "irqmap" = "0xaa5b" - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 device pci 12.0 on diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 4c3f615da0..87337a2be9 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -19,7 +19,7 @@ #include "northbridge/amd/gx2/raminit.h" /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { msr_t msr; /* 1. Initialize GLMC registers base on SPD values, diff --git a/src/mainboard/mitac/Kconfig b/src/mainboard/mitac/Kconfig index a02f150f9d..34cb1de7aa 100644 --- a/src/mainboard/mitac/Kconfig +++ b/src/mainboard/mitac/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_MITAC - + source "src/mainboard/mitac/6513wu/Kconfig" endchoice diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 7377da7f65..fd836987e3 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_MSI - + source "src/mainboard/msi/ms6119/Kconfig" source "src/mainboard/msi/ms6147/Kconfig" source "src/mainboard/msi/ms6156/Kconfig" diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index b3cd1194a6..d41e9b7115 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -35,7 +35,7 @@ const struct irq_routing_table intel_irq_routing_table = { { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x00<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */ diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index ae7a7f1a03..6ccd97587d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -47,7 +47,7 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO 0x0000ff0, //no HTIO for ms7135 }; unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, //ms7135 has only one ht-chain + 0x20202020, //ms7135 has only one ht-chain }; unsigned bus_type[256]; @@ -100,7 +100,7 @@ void get_bus_conf(void) switch (i) { case 1: dn = 9; break; case 2: dn = 13; break; - case 3: dn = 14; break; + case 3: dn = 14; break; default: dn = -1; break; } dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + dn, 0)); diff --git a/src/mainboard/msi/ms7135/irq_tables.c b/src/mainboard/msi/ms7135/irq_tables.c index f43af44bf5..e4a717ba72 100644 --- a/src/mainboard/msi/ms7135/irq_tables.c +++ b/src/mainboard/msi/ms7135/irq_tables.c @@ -78,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) int i; unsigned sbdn; - /* get_bus_conf() will find out all bus num and apic that share with + /* get_bus_conf() will find out all bus num and apic that share with * mptable.c and mptable.c */ get_bus_conf(); @@ -112,7 +112,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//Slot1 PCIE 16x +//Slot1 PCIE 16x write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); pirq_info++; @@ -130,7 +130,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; -//Slot4 PCIE 4x +//Slot4 PCIE 4x write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); @@ -229,7 +229,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[0] = 10; /* Ethernet */ pci_assign_irqs(bus_ck804[0], 10, irq); - + /* physical slots */ irq[0] = 5; /* PCI E1 - x1 */ @@ -237,7 +237,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[0] = 11; /* PCI E2 - x16 */ pci_assign_irqs(bus_ck804[3], 0, irq); - + /* AGP-on-PCI "AGR" ignored */ irq[0] = 10; /* PCI1 */ @@ -257,7 +257,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) irq[2] = 11; irq[3] = 0; pci_assign_irqs(bus_ck804[1], 9, irq); -#endif +#endif return (unsigned long)pirq_info; } diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 9752597d7a..cce07a7f94 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -15,7 +15,7 @@ config BOARD_MSI_MS7260 select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default msi/ms7260 @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_MSI_MS7260 - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_MSI_MS7260 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_MSI_MS7260 @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_MSI_MS7260 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_MSI_MS7260 @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_MSI_MS7260 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_MSI_MS7260 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_MSI_MS7260 diff --git a/src/mainboard/msi/ms7260/cmos.layout b/src/mainboard/msi/ms7260/cmos.layout index 51f4a6c598..5266518e56 100644 --- a/src/mainboard/msi/ms7260/cmos.layout +++ b/src/mainboard/msi/ms7260/cmos.layout @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## # TODO: Check and fix up the values as needed. diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c index d72530a3ae..a051500c64 100644 --- a/src/mainboard/msi/ms7260/resourcemap.c +++ b/src/mainboard/msi/ms7260/resourcemap.c @@ -163,7 +163,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -201,7 +201,7 @@ static void setup_mb_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -219,7 +219,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -227,7 +227,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -272,9 +272,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 3f7b69dc1b..a5fbffbe4b 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index bd73487313..cf1896d2d7 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -14,7 +14,7 @@ config BOARD_MSI_MS9282 select HAVE_HARD_RESET select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default msi/ms9282 @@ -24,7 +24,7 @@ config DCACHE_RAM_BASE hex default 0xcc000 depends on BOARD_MSI_MS9282 - + config DCACHE_RAM_SIZE hex default 0x04000 @@ -36,7 +36,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_MSI_MS9282 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_MSI_MS9282 @@ -71,7 +71,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_MSI_MS9282 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_MSI_MS9282 @@ -81,12 +81,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_MSI_MS9282 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_MSI_MS9282 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_MSI_MS9282 diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc index 8f94666961..e94ce3fd0e 100644 --- a/src/mainboard/msi/ms9282/Makefile.inc +++ b/src/mainboard/msi/ms9282/Makefile.inc @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2008 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c index 54e8be4f67..c76f830d89 100644 --- a/src/mainboard/msi/ms9652_fam10/acpi_tables.c +++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer <stepan@openbios.org>. - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> @@ -49,7 +49,7 @@ unsigned long acpi_fill_madt(unsigned long current) struct mb_sysconf_t *m; //extern unsigned char bus_mcp55[8]; //extern unsigned apicid_mcp55; - + unsigned sbdn; struct resource *res; device_t dev; @@ -57,7 +57,7 @@ unsigned long acpi_fill_madt(unsigned long current) get_bus_conf(); sbdn = sysconf.sbdn; m = sysconf.mb; - + /* Create all subtables for processors. */ current = acpi_create_madt_lapics(current); @@ -87,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index 84e1a76630..e5361b6822 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -51,7 +51,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) External (HCLK) External (SBDN) External (HCDN) - + Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () @@ -272,7 +272,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) IRQNoFlags () {7} }) Return (BUF1) @@ -289,7 +289,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () { - IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) + IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) IO (Decode16, 0x0778, 0x0778, 0x01, 0x04) IRQNoFlags() {7} DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3} diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index bb14f3310b..a1de4c4f57 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h +++ b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/newisys/Kconfig b/src/mainboard/newisys/Kconfig index fd8f9176e1..308cced541 100644 --- a/src/mainboard/newisys/Kconfig +++ b/src/mainboard/newisys/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_NEWISYS - + source "src/mainboard/newisys/khepri/Kconfig" endchoice diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index cb8f356e5a..30e73f774d 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 + device pci 18.0 on end # LDT 0 device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end @@ -57,7 +57,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -69,7 +69,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 on end device pci 1.6 on end end @@ -87,6 +87,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/newisys/khepri/resourcemap.c b/src/mainboard/newisys/khepri/resourcemap.c index d533b6357e..81bdefa835 100644 --- a/src/mainboard/newisys/khepri/resourcemap.c +++ b/src/mainboard/newisys/khepri/resourcemap.c @@ -151,7 +151,7 @@ static void setup_khepri_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -207,7 +207,7 @@ static void setup_khepri_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -215,7 +215,7 @@ static void setup_khepri_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index e8c040950f..bf1186df46 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -1,10 +1,10 @@ /* * This code is derived from the Tyan s2882 romstage.c * Adapted by Stefan Reinauer <stepan@coresystems.de> - * Additional (C) 2007 coresystems GmbH + * Additional (C) 2007 coresystems GmbH */ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -81,7 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* newisys khepri does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -129,13 +129,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/nvidia/Kconfig b/src/mainboard/nvidia/Kconfig index 54a0c0a99c..ac3b92f915 100644 --- a/src/mainboard/nvidia/Kconfig +++ b/src/mainboard/nvidia/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_NVIDIA - + source "src/mainboard/nvidia/l1_2pvv/Kconfig" endchoice diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 80f9f16d33..ab361f175f 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -15,7 +15,7 @@ config BOARD_NVIDIA_L1_2PVV select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default nvidia/l1_2pvv @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_NVIDIA_L1_2PVV - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_NVIDIA_L1_2PVV config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_NVIDIA_L1_2PVV @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_NVIDIA_L1_2PVV config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_NVIDIA_L1_2PVV @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_NVIDIA_L1_2PVV config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_NVIDIA_L1_2PVV config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_NVIDIA_L1_2PVV diff --git a/src/mainboard/olpc/Kconfig b/src/mainboard/olpc/Kconfig index 658ebb51c6..a74f393774 100644 --- a/src/mainboard/olpc/Kconfig +++ b/src/mainboard/olpc/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_OLPC - + source "src/mainboard/olpc/rev_a/Kconfig" source "src/mainboard/olpc/btest/Kconfig" diff --git a/src/mainboard/olpc/btest/devicetree.cb b/src/mainboard/olpc/btest/devicetree.cb index e0da82836a..ca55ce1b7e 100644 --- a/src/mainboard/olpc/btest/devicetree.cb +++ b/src/mainboard/olpc/btest/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -18,7 +18,7 @@ chip northbridge/amd/gx2 # SIRQ Mode = continous , It would be better if the EC could operate in # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK #register "lpc_irq" = "0x00001002" #register "lpc_serirq_enable" = "0xEFFD0080" #register "enable_gpio0_inta" = "1" diff --git a/src/mainboard/olpc/btest/irq_tables.c b/src/mainboard/olpc/btest/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/olpc/btest/irq_tables.c +++ b/src/mainboard/olpc/btest/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/olpc/btest/mainboard.c b/src/mainboard/olpc/btest/mainboard.c index b184a566d0..1e5add3dc0 100644 --- a/src/mainboard/olpc/btest/mainboard.c +++ b/src/mainboard/olpc/btest/mainboard.c @@ -73,26 +73,26 @@ static void init_cafe_irq(void){ const unsigned char slots_cafe[4] = {11, 0, 0, 0}; - - /* CAFE PCI slots */ - pci_assign_irqs(0, 0x0C, slots_cafe); - - /* Make the pin assignments - NOTENOTENOTE: This should be - * configurable! - */ - - /* Configure the GPIO pins to use - class 0, index 9 to configure - * AB. Write 0xFF to disable - */ - - vrWrite(0x9, 0XFF00); - - /* Configure the GPIO pins to use - class 0, index A to configure - * CD. Write 0xFF to disable - */ - - vrWrite(0xA, 0xFFFF); - + + /* CAFE PCI slots */ + pci_assign_irqs(0, 0x0C, slots_cafe); + + /* Make the pin assignments - NOTENOTENOTE: This should be + * configurable! + */ + + /* Configure the GPIO pins to use - class 0, index 9 to configure + * AB. Write 0xFF to disable + */ + + vrWrite(0x9, 0XFF00); + + /* Configure the GPIO pins to use - class 0, index A to configure + * CD. Write 0xFF to disable + */ + + vrWrite(0xA, 0xFFFF); + } @@ -111,7 +111,7 @@ static void init(struct device *dev) { * conditional we can make it a config variable later. */ - printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", __func__, bus, devfn, usbirq); usb = dev_find_slot(bus, devfn); if (! usb){ diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c index 1503baa6ba..fc605d1a88 100644 --- a/src/mainboard/olpc/btest/romstage.c +++ b/src/mainboard/olpc/btest/romstage.c @@ -50,7 +50,7 @@ static inline unsigned int fls(unsigned int x) Trrd=2 (act2act) Tref=17.8ms */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -100,11 +100,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* timing and mode ... */ msr = rdmsr(0x20000019); - - /* per standard bios settings */ + + /* per standard bios settings */ msr.hi = 0x18000108; - msr.lo = + msr.lo = (6<<28) | // cas_lat (10<<24)| // ref2act (7<<20)| // act2pre @@ -114,8 +114,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) (2<<6)| // dplwr (2<<4)| // dplrd (3); // dal - /* the msr value reported by quanta is very, very different. - * we will go with that value for now. + /* the msr value reported by quanta is very, very different. + * we will go with that value for now. */ msr.lo = 0x286332a3; @@ -180,9 +180,9 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); - + /* Check all of memory */ //ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/olpc/rev_a/devicetree.cb b/src/mainboard/olpc/rev_a/devicetree.cb index e0da82836a..ca55ce1b7e 100644 --- a/src/mainboard/olpc/rev_a/devicetree.cb +++ b/src/mainboard/olpc/rev_a/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -18,7 +18,7 @@ chip northbridge/amd/gx2 # SIRQ Mode = continous , It would be better if the EC could operate in # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK #register "lpc_irq" = "0x00001002" #register "lpc_serirq_enable" = "0xEFFD0080" #register "enable_gpio0_inta" = "1" diff --git a/src/mainboard/olpc/rev_a/irq_tables.c b/src/mainboard/olpc/rev_a/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/olpc/rev_a/irq_tables.c +++ b/src/mainboard/olpc/rev_a/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/olpc/rev_a/mainboard.c b/src/mainboard/olpc/rev_a/mainboard.c index a02e583558..adfb957ab7 100644 --- a/src/mainboard/olpc/rev_a/mainboard.c +++ b/src/mainboard/olpc/rev_a/mainboard.c @@ -83,7 +83,7 @@ static void init(struct device *dev) { * conditional we can make it a config variable later. */ - printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", __func__, bus, devfn, usbirq); usb = dev_find_slot(bus, devfn); if (! usb){ diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c index 1503baa6ba..fc605d1a88 100644 --- a/src/mainboard/olpc/rev_a/romstage.c +++ b/src/mainboard/olpc/rev_a/romstage.c @@ -50,7 +50,7 @@ static inline unsigned int fls(unsigned int x) Trrd=2 (act2act) Tref=17.8ms */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -100,11 +100,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) /* timing and mode ... */ msr = rdmsr(0x20000019); - - /* per standard bios settings */ + + /* per standard bios settings */ msr.hi = 0x18000108; - msr.lo = + msr.lo = (6<<28) | // cas_lat (10<<24)| // ref2act (7<<20)| // act2pre @@ -114,8 +114,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) (2<<6)| // dplwr (2<<4)| // dplrd (3); // dal - /* the msr value reported by quanta is very, very different. - * we will go with that value for now. + /* the msr value reported by quanta is very, very different. + * we will go with that value for now. */ msr.lo = 0x286332a3; @@ -180,9 +180,9 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); - + /* Check all of memory */ //ram_check(0x00000000, 640*1024); } diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index 23b46536c8..c1b0168505 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_PC_ENGINES - + source "src/mainboard/pcengines/alix1c/Kconfig" endchoice diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 3e1237a47c..0ba52ce937 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -14,7 +14,7 @@ config BOARD_PCENGINES_ALIX1C config MAINBOARD_DIR string - default pcengines/alix1c + default pcengines/alix1c depends on BOARD_PCENGINES_ALIX1C config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 34668d1025..f40e302956 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/lx - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 @@ -57,7 +57,7 @@ chip northbridge/amd/lx io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 on end # GPIO2 device pnp 2e.9 on end # GPIO3 device pnp 2e.a on end # ACPI diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig index e4e913559d..bd272be17e 100644 --- a/src/mainboard/rca/Kconfig +++ b/src/mainboard/rca/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_RCA - + source "src/mainboard/rca/rm4100/Kconfig" endchoice diff --git a/src/mainboard/rca/rm4100/chip.h b/src/mainboard/rca/rm4100/chip.h index 14d6677a22..c46c318c29 100644 --- a/src/mainboard/rca/rm4100/chip.h +++ b/src/mainboard/rca/rm4100/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> + * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index a27b7bb327..0f7512c1b2 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -58,13 +58,13 @@ static void mb_gpio_init(void) outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); + outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN1_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); + outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x36); @@ -79,7 +79,7 @@ static void mb_gpio_init(void) outl(0x00, PME_IO_BASE_ADDR + 0x3a); /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); + outl(0x00, PME_IO_BASE_ADDR + 0x3d); /* GP50 - SER2_RI */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2248ba791e..653b22ab76 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -38,7 +38,7 @@ static void mainboard_enable(device_t dev) // TODO Switch parport LEDs dev->ops->init = mainboard_init; } - + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, CHIP_NAME("RCA RM4100 Mainboard") diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 5830af0b40..554d7f125b 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -88,11 +88,11 @@ static void mb_early_setup(void) /* CPU Frequency Strap */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); /* ACPI base address and enable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); /* Enable the SMBUS */ enable_smbus(); /* ACPI base address and disable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR)); /* ACPI Enable */ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index 77269ad143..df61526867 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -113,7 +113,7 @@ Device (BAT1) } } } - + Store (CBA1, Local0) Store (Local0, Index(PBST, 2)) Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) @@ -130,7 +130,7 @@ Device (BAT1) Store (1, Local1) } } - + Store (Local1, Index(PBST, 0)) If (\_SB.PCI0.LPCB.EC0.P63S) { Store (0x16, Index(PBST, 1)) @@ -253,7 +253,7 @@ Device (BAT2) } } } - + Store (CBA2, Local0) Store (Local0, Index(PBST, 2)) Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) @@ -270,7 +270,7 @@ Device (BAT2) Store (1, Local1) } } - + Store (Local1, Index(PBST, 0)) If (\_SB.PCI0.LPCB.EC0.P62S) { Store (0x16, Index(PBST, 1)) diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 2b8c7ea429..fc0ae547e2 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -81,14 +81,14 @@ Device(EC0) { // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - + If (LEqual(Arg0, 0x03)) { Store (Arg1, ECON) } } // EC Query methods - + Method (_Q11, 0) { Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl index 6a16b5b887..674c3d41f0 100644 --- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl index 4c4edd7c17..dc1f9da6f6 100644 --- a/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl index 7a2dea76a2..4be20c3ed8 100644 --- a/src/mainboard/roda/rk886ex/acpi/mainboard.asl +++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl @@ -36,7 +36,7 @@ Device (SLPB) Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) - + // Wake Name(_PRW, Package(){0x1d, 0x04}) } diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index 9e86d0b7a7..5de4a83324 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -48,9 +48,9 @@ Method(TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -80,12 +80,12 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - // Are we going to S3? + // Are we going to S3? If (LEqual(Arg0, 3)) { // .. } - // Are we going to S4? + // Are we going to S4? If (LEqual(Arg0, 4)) { // .. } diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 67ff1f91f7..31cb44ad64 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -138,7 +138,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) // Why? CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQL) - + Store (READ(0, 0x24, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) @@ -297,7 +297,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQL) - + Store (READ(0, 0x25, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index cea3e8ea7b..b7efc53c3a 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -27,7 +27,7 @@ Scope (\_TZ) { // FIXME these could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x04) Name(TC2V, 0x03) diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index d89adf5e8b..00088f7b65 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -161,7 +161,7 @@ unsigned long acpi_fill_madt(unsigned long current) MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | + current, 1, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); /* INT_SRC_OVR */ @@ -277,7 +277,7 @@ unsigned long write_acpi_tables(unsigned long start) current += dsdt->length; memcpy(dsdt, &AmlCode, dsdt->length); - /* Fix up global NVS region for SMI handler. The GNVS region lives + /* Fix up global NVS region for SMI handler. The GNVS region lives * in the (high) table area. The low memory map looks like this: * * 0x00000000 - 0x000003ff Real Mode IVT diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/roda/rk886ex/chip.h index 538f91425e..9fcb67fddb 100644 --- a/src/mainboard/roda/rk886ex/chip.h +++ b/src/mainboard/roda/rk886ex/chip.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 985aa14275..b5ae473ac6 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -1,6 +1,6 @@ # # This file is part of the coreboot project. -# +# # Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index b578e19a55..9ce265955e 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or @@ -27,7 +27,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port @@ -79,7 +79,7 @@ chip northbridge/intel/i945 device pci 3.3 off end # smartcard end end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47n227 diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index 67539cce53..593b8d351f 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock( // General Purpose Events #include "acpi/gpe.asl" - + // mainboard specific devices #include "acpi/mainboard.asl" diff --git a/src/mainboard/roda/rk886ex/ec.c b/src/mainboard/roda/rk886ex/ec.c index f2d23ad6c5..4c39a8419e 100644 --- a/src/mainboard/roda/rk886ex/ec.c +++ b/src/mainboard/roda/rk886ex/ec.c @@ -35,7 +35,7 @@ int send_ec_command(u8 command) printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", command); // return -1; } diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 62752e9065..5173ecfd39 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -54,7 +54,7 @@ static u8 variables[] = { 0x1e, 0xff, 0x87, // FuncKey Task = c5 Command Data (funcTsk) 0x1f, 0xff, 0x9f, // Delayed Task = c5 Command Data (dlyTsk1) 0x20, 0xff, 0x9f, // Wake-Up Task = c5 Command Data (wakeTsk) - // + // 0x21, 0xff, 0x08, // WigglePin Pulse Width * 2.4ms (tmPulse) 0x24, 0xff, 0x30, // Keyboard State Flags (kState7) // @@ -121,7 +121,7 @@ static int send_kbd_command(u8 command) printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", + printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", command); // return -1; } @@ -249,7 +249,7 @@ void m3885_configure_multikey(void) m3885_set_proc_ram(i + 0x80, matrix[i]); } - + /* ram bank 2 */ m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4)); @@ -303,7 +303,7 @@ void m3885_configure_multikey(void) /* Critical Task */ m3885_set_proc_ram(0xf3, 0x5d); - + /* Thermal Polling Period */ m3885_set_proc_ram(0xf9, 0x0a); @@ -316,21 +316,21 @@ void m3885_configure_multikey(void) else reg8 = 0x9a; m3885_set_proc_ram(0xd0, reg8); // P60SPEC - + /* SENSE1# */ if (m3885_read_port() & (1 << 2)) reg8 = 0x8a; else reg8 = 0x9a; m3885_set_proc_ram(0xd2, reg8); // P62SPEC - + /* SENSE2# */ if (m3885_read_port() & (1 << 3)) reg8 = 0x8a; else reg8 = 0x9a; m3885_set_proc_ram(0xd3, reg8); // P63SPEC - + /* Low Active Port */ m3885_set_proc_ram(0xd1, 0x88); // P61SPEC m3885_set_proc_ram(0xd6, 0x88); // P66SPEC diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index f23a15932e..acfdfaa67b 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -114,7 +114,7 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(device_t dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c index 947f642802..a87d99da47 100644 --- a/src/mainboard/roda/rk886ex/mainboard_smi.c +++ b/src/mainboard/roda/rk886ex/mainboard_smi.c @@ -25,7 +25,7 @@ #include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" -/* The southbridge SMI handler checks whether gnvs has a +/* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index c9de525d11..027be50b99 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -71,7 +71,7 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index c888871e5f..044107cd5a 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -184,7 +184,7 @@ static void rcba_config(void) RCBA32(0x3400) = (1 << 2); /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; RCBA32(0x3418) |= (1 << 0); // Required. @@ -266,7 +266,7 @@ static void init_artec_dongle(void) #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) @@ -330,7 +330,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -340,8 +340,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -385,7 +385,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ diff --git a/src/mainboard/roda/rk886ex/rtl8168.c b/src/mainboard/roda/rk886ex/rtl8168.c index e278bcfb4e..04fd56ccb1 100644 --- a/src/mainboard/roda/rk886ex/rtl8168.c +++ b/src/mainboard/roda/rk886ex/rtl8168.c @@ -28,7 +28,7 @@ static void nic_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep + // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } diff --git a/src/mainboard/soyo/Kconfig b/src/mainboard/soyo/Kconfig index bb20b7475a..224e9a7409 100644 --- a/src/mainboard/soyo/Kconfig +++ b/src/mainboard/soyo/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_SOYO - + source "src/mainboard/soyo/sy-6ba-plus-iii/Kconfig" endchoice diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig index b04d9053c0..8a42be7414 100644 --- a/src/mainboard/sunw/Kconfig +++ b/src/mainboard/sunw/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_SUNW - + source "src/mainboard/sunw/ultra40/Kconfig" endchoice diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb index afa6f66beb..e7917495b7 100644 --- a/src/mainboard/sunw/ultra40/devicetree.cb +++ b/src/mainboard/sunw/ultra40/devicetree.cb @@ -7,9 +7,9 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end # link 0 - device pci 18.0 on # link1 - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 + device pci 18.0 on # link1 + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/ck804 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/smsc/lpc47m10x @@ -40,29 +40,29 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -71,24 +71,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master CK804 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave CK804 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # ACI @@ -109,18 +109,18 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + chip northbridge/amd/amdk8 device pci 19.0 on end # link 0 - device pci 19.0 on + device pci 19.0 on # devices on link 1, link 1 == LDT 1 - chip southbridge/nvidia/ck804 + chip southbridge/nvidia/ck804 device pci 0.0 on end # HT device pci 1.0 on end # LPC device pci 1.1 off end # SM @@ -140,13 +140,13 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end - end # device pci 19.0 - + end # device pci 19.0 + device pci 19.0 on end device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end end end # PCI domain - + end #root_complex diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index 53162da97f..8309c8a10f 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -34,7 +34,7 @@ unsigned apicid_ck804b; unsigned sblk; -unsigned pci1234[] = +unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -48,7 +48,7 @@ unsigned pci1234[] = }; unsigned hc_possible_num; unsigned sbdn; -unsigned hcdn[] = +unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -77,10 +77,10 @@ void get_bus_conf(void) get_bus_conf_done = 1; - hc_possible_num = ARRAY_SIZE(pci1234); - + hc_possible_num = ARRAY_SIZE(pci1234); + get_sblk_pci1234(); - + sbdn = (hcdn[0] & 0xff); // first byte of first chain sbdn3 = (hcdn[1] & 0xff); @@ -262,8 +262,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(4); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_ck804 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c index 2bbbe7b110..324c87d995 100644 --- a/src/mainboard/sunw/ultra40/irq_tables.c +++ b/src/mainboard/sunw/ultra40/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -11,11 +11,11 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -76,15 +76,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_ck804_0; pirq->rtr_devfn = ((sbdn+9)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x005c; @@ -100,9 +100,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pcix bridge write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - if(pci1234[2] & 0xf) { - //second pci beidge + + if(pci1234[2] & 0xf) { + //second pci beidge write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); pirq_info++; slot_num++; } @@ -139,10 +139,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) //Slot2 pci write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); pirq_info++; slot_num++; -//nic +//nic write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//Slot3 PCIE x16 +//Slot3 PCIE x16 write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); pirq_info++; slot_num++; @@ -162,11 +162,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); pirq_info++; slot_num++; #endif - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index b019ffea13..be92616e2d 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1); @@ -212,7 +212,7 @@ static void *smp_write_config_table(void *v) //Channel A of 8131 -//Slot 6 PCIX 133/100/66 +//Slot 6 PCIX 133/100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 } diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c index 726373093f..eae21b4817 100644 --- a/src/mainboard/sunw/ultra40/resourcemap.c +++ b/src/mainboard/sunw/ultra40/resourcemap.c @@ -145,7 +145,7 @@ static void setup_ultra40_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -183,7 +183,7 @@ static void setup_ultra40_resource_map(void) * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -201,7 +201,7 @@ static void setup_ultra40_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -209,7 +209,7 @@ static void setup_ultra40_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index de16a4481f..76822ce45d 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -6,7 +6,7 @@ #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -55,7 +55,7 @@ static void sio_gpio_setup(void) unsigned value; /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); } @@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -111,21 +111,21 @@ static void sio_setup(void) unsigned value; uint32_t dword; uint8_t byte; - + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); - + byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); - + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; + value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); } @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index f44677118c..1948784761 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_SUPERMICRO - + source "src/mainboard/supermicro/h8dme/Kconfig" source "src/mainboard/supermicro/h8dmr/Kconfig" source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dme/cmos.layout +++ b/src/mainboard/supermicro/h8dme/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 5d6776a3f2..f6f75efb65 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -67,24 +67,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -116,15 +116,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -135,5 +135,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dme/resourcemap.c +++ b/src/mainboard/supermicro/h8dme/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dmr/cmos.layout b/src/mainboard/supermicro/h8dmr/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr/cmos.layout +++ b/src/mainboard/supermicro/h8dmr/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index d83f00637d..67920c4657 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,15 +136,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -155,5 +155,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dmr/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index fd0634ff62..3ef91c82bb 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,7 +37,7 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -98,7 +98,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -129,13 +129,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 8d8936c92f..c142dcb290 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdfam10/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdfam10/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,7 +136,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -147,10 +147,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -161,5 +161,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 673db742fb..a981fe1b9c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 51c2feb000..5759f40ccf 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -57,12 +57,12 @@ chip northbridge/amd/amdfam10/root_complex device pci 1.1 on end device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# +# chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -70,7 +70,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.1 off end # AZA - device pci 7.0 on + device pci 7.0 on device pci 1.0 on end end device pci 8.0 off end @@ -87,7 +87,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -110,10 +110,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -124,5 +124,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index efaf4cb754..9338d5e08c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0364; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h index 42969bb71e..5a17fa9442 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; unsigned char bus_8132_0; //7 unsigned char bus_8132_1; //8 diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 551ee977fa..c365ddbe2d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -100,33 +100,33 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ - for(j=7;j>=2; j--) { + for(j=7;j>=2; j--) { if(!m->bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index aa2081f7df..0d1657a170 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -93,12 +93,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #define MCP55_NUM 1 -#define MCP55_USE_NIC 0 +#define MCP55_USE_NIC 0 #define MCP55_USE_AZA 0 #define MCP55_PCI_E_X_0 4 @@ -128,13 +128,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x30); - + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb index 97176b9b78..038964e9ad 100644 --- a/src/mainboard/supermicro/x6dai_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb @@ -1,20 +1,20 @@ chip northbridge/intel/e7525 # mch device pci_domain 0 on - chip southbridge/intel/esb6300 # esb6300 + chip southbridge/intel/esb6300 # esb6300 register "pirq_a_d" = "0x0b0a0a05" register "pirq_e_h" = "0x0a0b0c80" - + device pci 1c.0 on end - + device pci 1d.0 on end device pci 1d.1 on end device pci 1d.4 on end device pci 1d.5 on end device pci 1d.7 on end - + device pci 1e.0 on end - - device pci 1f.0 on + + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end device pnp 2e.1 off end @@ -45,7 +45,7 @@ chip northbridge/intel/e7525 # mch device pci 1f.6 on end end device pci 00.0 on end - device pci 00.1 on end + device pci 00.1 on end device pci 00.2 on end device pci 02.0 on end device pci 03.0 on end diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index a3bb398fa2..a0c863cb45 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) bus_isa = 6; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index b718daf9ab..da5cadac00 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -116,7 +116,7 @@ static void main(unsigned long bist) // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -127,8 +127,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2531bc2969..1b1162c00d 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -18,17 +18,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb index d5625e4c7c..075acfc232 100644 --- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb @@ -10,8 +10,8 @@ chip northbridge/intel/e7520 # MCH register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 67bd2cfb56..2549cb1327 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -55,8 +55,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -118,7 +118,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -128,7 +128,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index e621594b93..bbc4e76778 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -6,12 +6,12 @@ chip northbridge/intel/e7520 # MCH device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801ex # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/nsc/pc87427 device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 68ad41de40..2b0cbc84d4 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -53,8 +53,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) //dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -138,8 +138,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 921c54fff5..b989e76e8a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> VGA device pci 1e.0 on end - + # -> IDE - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -39,18 +39,18 @@ chip northbridge/intel/e7520 # mch register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on end - device pci 03.0 on + device pci 01.0 on end + device pci 02.0 on end + device pci 03.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 2 device pci 0.0 on end device pci 0.1 on end - device pci 0.2 on + device pci 0.2 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 02.0 on end device pci 02.1 on end end @@ -58,7 +58,7 @@ chip northbridge/intel/e7520 # mch device pci 0.3 on end end end - device pci 04.0 on + device pci 04.0 on chip southbridge/intel/pxhd # pxhd2 # Bus bridges and ioapics usually bus 5 device pci 0.0 on end diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index b98ec52479..efc7abf22a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 7; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -159,7 +159,7 @@ static void *smp_write_config_table(void *v) } } - + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 77c9eba0fb..16f0ac7337 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index 318d492b9f..ed3fa65219 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -34,22 +34,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index 78a863c7a1..3e95e108d1 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index d2b845eac6..8f5ca7930e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/technexion/Kconfig b/src/mainboard/technexion/Kconfig index c0bf041034..da13c340eb 100644 --- a/src/mainboard/technexion/Kconfig +++ b/src/mainboard/technexion/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_TECHNEXION - + source "src/mainboard/technexion/tim8690/Kconfig" source "src/mainboard/technexion/tim5690/Kconfig" diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 11bb4248e7..924d09e55f 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -184,7 +184,7 @@ static void mb_gpio_init(u16 *iobase) it8712f_enter_conf(); outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); + outb(0x62, SIO_INDEX); outb((*iobase >> 8), SIO_DATA); outb(0x63, SIO_INDEX); outb((*iobase & 0xff), SIO_DATA); diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c index ae11b3eb63..b7f18647d3 100644 --- a/src/mainboard/technexion/tim5690/speaker.c +++ b/src/mainboard/technexion/tim5690/speaker.c @@ -54,7 +54,7 @@ void speaker_init(uint8_t time) { * CounterSelect, bit[7:6]=10b, Select counter 2. */ outb(0xb6, 0x43); - + /* SB600 RRG. * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 294c0f2590..664372d879 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -48,7 +48,7 @@ uint64_t uma_memory_base, uma_memory_size; /*************************************************** * This board, the TIM-8690 has two Marvel 88e5056 PCI-E -* 10/100/1000 chips on board. +* 10/100/1000 chips on board. * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. ****************************************************/ diff --git a/src/mainboard/technologic/Kconfig b/src/mainboard/technologic/Kconfig index 32967fd3e5..5756361863 100644 --- a/src/mainboard/technologic/Kconfig +++ b/src/mainboard/technologic/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_TECHNOLOGIC - + source "src/mainboard/technologic/ts5300/Kconfig" endchoice diff --git a/src/mainboard/technologic/ts5300/chip.h b/src/mainboard/technologic/ts5300/chip.h index 97f92dd915..ceb8af100a 100644 --- a/src/mainboard/technologic/ts5300/chip.h +++ b/src/mainboard/technologic/ts5300/chip.h @@ -1,5 +1,5 @@ extern struct chip_operations mainboard_ops; struct mainboard_config { - + }; diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb index 65809cb2f4..a0f05791af 100644 --- a/src/mainboard/technologic/ts5300/devicetree.cb +++ b/src/mainboard/technologic/ts5300/devicetree.cb @@ -1,7 +1,7 @@ chip cpu/amd/sc520 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end - + # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end diff --git a/src/mainboard/technologic/ts5300/irq_tables.c b/src/mainboard/technologic/ts5300/irq_tables.c index 9b49747ead..22d5820a62 100644 --- a/src/mainboard/technologic/ts5300/irq_tables.c +++ b/src/mainboard/technologic/ts5300/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 4b9ce16bf8..58333b8f88 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -17,10 +17,10 @@ static void irqdump(void) int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, - 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, + 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, - 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, - 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, + 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, + 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a, -1}; mmcr = (void *) 0xfffef000; @@ -44,7 +44,7 @@ static void enable_dev(struct device *dev) { /* from fuctory bios */ /* NOTE: the following interrupt settings made interrupts work - * for hard drive, and serial, but not for ethernet + * for hard drive, and serial, but not for ethernet */ printk(BIOS_ERR, "Setting up PIC\n"); @@ -63,7 +63,7 @@ static void enable_dev(struct device *dev) { mmcr->pic.rtcmap = 0x03; mmcr->pic.ferrmap = 0x00; mmcr->pic.intpinpol = 0x100; - + mmcr->pic.gp0imap = 0x00; mmcr->pic.gp1imap = 0x02; mmcr->pic.gp2imap = 0x07; @@ -83,7 +83,7 @@ static void enable_dev(struct device *dev) { mmcr->sysarb.ctl = 0x00; mmcr->sysarb.menb = 0x1f; mmcr->sysarb.prictl = 0x40000f0f; - + /* this is bios setting, depends on sysarb above */ mmcr->hostbridge.ctl = 0x0; mmcr->hostbridge.tgtirqctl = 0x0; @@ -125,7 +125,7 @@ static void enable_dev(struct device *dev) { mmcr->gpctl.gprdoff = 0x02; mmcr->gpctl.gpwrw = 0x07; mmcr->gpctl.gpwroff = 0x02; - + //mmcr->reset.sysinfo = 0xdf; //mmcr->reset.rescfg = 0x5; /* their IRQ table is wrong. Just hardwire it */ diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 4379c2457d..d0f0d4c61c 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -52,7 +52,7 @@ void setup_pars(void) static void identify_ts9500(void) { unsigned i, val; - + TS9500_LED_ON; print_err("TS-9500 add-on found:\n"); @@ -61,23 +61,23 @@ static void identify_ts9500(void) print_err(" DIP"); print_err_char(i+0x31); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); - + val=inb(0x19a); - + for (i=6; i<8; i++) { print_err(" JP"); print_err_char(i+0x30-5); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); @@ -103,33 +103,33 @@ static void identify_system(void) print_err(" SRAM option: "); if((val&1)==0) print_err("not "); print_err("installed\n"); - + print_err(" RS-485 option: "); if((val&2)==0) print_err("not "); print_err("installed\n"); val=inb(0x76); print_err(" Temp. range: "); - if((val&2)==0) print_err("commercial\n"); + if((val&2)==0) print_err("commercial\n"); else print_err("industrial\n"); - + print_err("\n"); - + val=inb(0x77); for (i=1; i<8; i++) { print_err(" JP"); print_err_char(i+0x30); print_err(": "); - if((val&(1<<i))!=0) - print_err("on\n"); + if((val&(1<<i))!=0) + print_err("on\n"); else - print_err("off\n"); + print_err("off\n"); } print_err("\n"); /* Detect TS-9500 */ val=inb(0x19d); - if(val==0x5f) + if(val==0x5f) identify_ts9500(); } @@ -144,18 +144,18 @@ static void main(unsigned long bist) { volatile int i; unsigned val; - + TS5300_LED_ON; - + // Let the hardware settle a bit. for(i = 0; i < 100; i++) ; - + setupsc520(); uart_init(); console_init(); - - + + print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n"); staticmem(); print_err("Memory initialized: 32MB\n"); @@ -170,7 +170,7 @@ static void main(unsigned long bist) ram_check(0x00000000, 0x000a0000); ram_check(0x000b0000, 0x02000000); #endif - + TS5300_LED_OFF; } diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig index 936ad3e71d..eb2caa09ff 100644 --- a/src/mainboard/thomson/Kconfig +++ b/src/mainboard/thomson/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_THOMSON - + source "src/mainboard/thomson/ip1000/Kconfig" endchoice diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index 6a69bb539d..1c5125a253 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -61,13 +61,13 @@ static void mb_gpio_init(void) outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP30 - FAN2_TACH */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); + outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP31 - FAN1_TACH */ outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP32 - FAN2_CTRL */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); + outl(0x04, PME_IO_BASE_ADDR + 0x35); /* GP33 - FAN1_CTRL */ outl(0x04, PME_IO_BASE_ADDR + 0x36); @@ -82,7 +82,7 @@ static void mb_gpio_init(void) outl(0x00, PME_IO_BASE_ADDR + 0x3a); /* GP42 - GPIO_PME_OUT */ - outl(0x00, PME_IO_BASE_ADDR + 0x3d); + outl(0x00, PME_IO_BASE_ADDR + 0x3d); /* GP50 - SER2_RI */ outl(0x05, PME_IO_BASE_ADDR + 0x3f); diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index c78a710321..f6eee68440 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -62,13 +62,13 @@ static void parport_gpios(void) printk(BIOS_DEBUG, "IP1000 GPIOs:\n"); printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios); - printk(BIOS_DEBUG, " green led: %s\n", + printk(BIOS_DEBUG, " green led: %s\n", (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on"); - printk(BIOS_DEBUG, " orange led: %s\n", + printk(BIOS_DEBUG, " orange led: %s\n", (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on"); - printk(BIOS_DEBUG, " red led: %s\n", + printk(BIOS_DEBUG, " red led: %s\n", (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on"); - printk(BIOS_DEBUG, " IR port: %s\n", + printk(BIOS_DEBUG, " IR port: %s\n", (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on"); } @@ -77,7 +77,7 @@ static void flash_gpios(void) u8 manufacturer_id = read8(0xffbc0000); u8 device_id = read8(0xffbc0001); - if ((manufacturer_id == 0x20) && + if ((manufacturer_id == 0x20) && ((device_id == 0x2c) || (device_id == 0x2d))) { printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", (device_id==0x2c)?'4':'8'); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index bf78a1d2d1..66b92d14bd 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -89,7 +89,7 @@ static void mb_early_setup(void) /* CPU Frequency Strap */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02); /* ACPI base address and enable Resource Indicator */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1)); /* Enable the SMBUS */ enable_smbus(); /* ACPI Enable */ diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig index 93b6d9d4c2..cd9646b38c 100644 --- a/src/mainboard/tyan/Kconfig +++ b/src/mainboard/tyan/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_TYAN - + source "src/mainboard/tyan/s1846/Kconfig" source "src/mainboard/tyan/s2735/Kconfig" source "src/mainboard/tyan/s2850/Kconfig" diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index a0f739c071..a387d1a4ba 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -26,12 +26,12 @@ config DCACHE_RAM_BASE hex default 0xcf000 depends on BOARD_TYAN_S2735 - + config DCACHE_RAM_SIZE hex default 0x1000 depends on BOARD_TYAN_S2735 - + config MAINBOARD_PART_NUMBER string default "S2735" diff --git a/src/mainboard/tyan/s2735/cmos.layout b/src/mainboard/tyan/s2735/cmos.layout index ccda70c808..608f02867c 100644 --- a/src/mainboard/tyan/s2735/cmos.layout +++ b/src/mainboard/tyan/s2735/cmos.layout @@ -30,8 +30,8 @@ entries 388 4 r 0 reboot_bits 392 3 e 5 baud_rate 395 1 e 2 hyper_threading -396 1 e 1 thermal_monitoring -397 1 e 1 remap_memory_high +396 1 e 1 thermal_monitoring +397 1 e 1 remap_memory_high 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index 8ad5e0ecac..1e8b12a790 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/e7501 device pci 2.0 on chip southbridge/intel/i82870 device pci 1c.0 on end - device pci 1d.0 on + device pci 1d.0 on device pci 1.0 on end # intel lan device pci 1.1 on end end @@ -20,7 +20,7 @@ chip northbridge/intel/e7501 device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - device pci 1e.0 on + device pci 1e.0 on device pci 1.0 on end # intel lan 10/100 device pci 2.0 on end # ati end @@ -56,7 +56,7 @@ chip northbridge/intel/e7501 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c index 4f6eb306dc..036b8d0cb0 100644 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ b/src/mainboard/tyan/s2735/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 6a73c6dc88..cde5c4e3b4 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -48,18 +48,18 @@ static void *smp_write_config_table(void *v) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x09, 0x20, res->base); - } + } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 0x0a, 0x20, res->base); - } + } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x8, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x8, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x8, 0x2); @@ -149,7 +149,7 @@ Compatibility Bus Address predefined range: 0x00000000-- Compatibility Bus Address bus ID: 0 address modifier: add - predefined range: 0x00000001 // There is no extension information... + predefined range: 0x00000001 // There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index f581de431e..de3124cb90 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -50,7 +50,7 @@ void main(unsigned long bist) .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, }, }; - + if (bist == 0) { enable_lapic(); } diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 264f8c7df6..98e6a28746 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # LDT0 @@ -51,7 +51,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -63,7 +63,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end @@ -82,14 +82,14 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c index 8c7e681ec2..d1179dcfae 100644 --- a/src/mainboard/tyan/s2850/irq_tables.c +++ b/src/mainboard/tyan/s2850/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 0d4d6f9bc1..51c060126f 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -90,8 +90,8 @@ static void *smp_write_config_table(void *v) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } + else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8111_1 = 2; @@ -110,12 +110,12 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); @@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13); - + //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 6fbafa90cb..4e75e36832 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index badb881777..edd4f6f784 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8151 # the on/off keyword is mandatory @@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -73,15 +73,15 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2875/irq_tables.c b/src/mainboard/tyan/s2875/irq_tables.c index db30d686c8..d08aa6ca09 100644 --- a/src/mainboard/tyan/s2875/irq_tables.c +++ b/src/mainboard/tyan/s2875/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 77afde6abf..c2a7012f13 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -104,15 +104,15 @@ static void *smp_write_config_table(void *v) if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); - + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); bus_8151_1 = 2; } - - + + } /*Bus: Bus ID Type*/ @@ -126,11 +126,11 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -156,7 +156,7 @@ static void *smp_write_config_table(void *v) // AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); -// Onboard Serial ATA +// Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x13); //Onboard Firewire smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 274f8dc7ca..ead3655fae 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index 122648e137..97dcae866a 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -66,7 +66,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -84,15 +84,15 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index 78c12016b4..19149df142 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr); + return copy_pirq_routing_table(addr); } diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index a8f3859d7b..94a150b031 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -89,14 +89,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -134,14 +134,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); @@ -165,7 +165,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -205,7 +205,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);// -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 7c0e4f2a2c..f75c541b9c 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index 3c1f5bc276..47b5d37775 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -8,11 +8,11 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on device pci 9.0 on end # Broadcom 5704 device pci 9.1 on end device pci a.0 on end # Adaptic @@ -65,7 +65,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -77,13 +77,13 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end @@ -120,12 +120,12 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end end diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 758e3d809d..562ba935d8 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -23,7 +23,7 @@ unsigned apicid_8111 ; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -35,7 +35,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -71,7 +71,7 @@ void get_bus_conf(void) } get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; @@ -119,8 +119,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/tyan/s2881/irq_tables.c b/src/mainboard/tyan/s2881/irq_tables.c index af66ba9730..b53a9923a7 100644 --- a/src/mainboard/tyan/s2881/irq_tables.c +++ b/src/mainboard/tyan/s2881/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -12,11 +12,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -62,22 +62,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge @@ -88,11 +88,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) // pirq_info++; slot_num++; pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c index 5866577ce4..773f2540a4 100644 --- a/src/mainboard/tyan/s2881/mainboard.c +++ b/src/mainboard/tyan/s2881/mainboard.c @@ -59,7 +59,7 @@ static void adt7463_init(device_t dev) result = smbus_write_byte(adt7463, 0x5e, 0xc2); /* Make sure that our fans never stop when temp. falls below Tmin, - * but rather keep going at minimum duty cycle (applies to automatic + * but rather keep going at minimum duty cycle (applies to automatic * fan control mode only). */ result = smbus_write_byte(adt7463, 0x62, 0xc0); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index ca75c51a93..a51384c641 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_num; int i; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); - + /*Bus: Bus ID Type*/ /* define bus and isa numbers */ @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); { @@ -82,7 +82,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + //8111 LPC ???? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13); diff --git a/src/mainboard/tyan/s2881/resourcemap.c b/src/mainboard/tyan/s2881/resourcemap.c index cecb790795..23ab936a5b 100644 --- a/src/mainboard/tyan/s2881/resourcemap.c +++ b/src/mainboard/tyan/s2881/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2881_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2881_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2881_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 1310c8e99b..0a63486ffb 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -3,7 +3,7 @@ #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index d563232b2d..b8cbce2858 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -67,7 +67,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -80,13 +80,13 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on end - device pci 1.3 on + device pci 1.3 on # chip drivers/generic/generic #dimm 0-0-0 # device i2c 50 on end # end # chip drivers/generic/generic #dimm 0-0-1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #dimm 0-1-0 # device i2c 52 on end # end @@ -111,11 +111,11 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index 3107ac8a87..4ddd63eecb 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -63,7 +63,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -76,11 +76,11 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -162,15 +162,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_chain_0; pirq->rtr_devfn = (4<<3)|3; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; @@ -186,7 +186,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); if (dev) { /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D + on the PCB routing of PINTA-D PINTA = IRQ5 PINTB = IRQ9 @@ -202,7 +202,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); @@ -279,16 +279,16 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; #endif -#if 0 +#if 0 //?? what's this? write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); pirq_info++; slot_num++; #endif - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index f1d7a27179..43ccef6276 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -30,7 +30,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -95,8 +95,8 @@ static void *smp_write_config_table(void *v) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } + else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; @@ -137,9 +137,9 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -163,7 +163,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -180,7 +180,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13); - + //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); @@ -209,7 +209,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index c49dff9f10..d8816d4cff 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index f8dc2215d9..7cdc728fbb 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -14,11 +14,11 @@ chip northbridge/amd/amdk8/root_complex end end device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end @@ -67,7 +67,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -82,36 +82,36 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end - end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # acpi device pci 1.5 on end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -119,9 +119,9 @@ chip northbridge/amd/amdk8/root_complex end #pci_domain -# chip drivers/generic/debug +# chip drivers/generic/debug # device pnp 0.0 off end -# device pnp 0.1 off end +# device pnp 0.1 off end # device pnp 0.2 off end # device pnp 0.3 off end # device pnp 0.4 off end diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index de4deb23d3..a511afa395 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -24,7 +24,7 @@ unsigned apicid_8111 ; unsigned apicid_8131_1; unsigned apicid_8131_2; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -36,7 +36,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -73,7 +73,7 @@ void get_bus_conf(void) } get_sblk_pci1234(); - + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; sbdn3 = sysconf.hcdn[0] & 0xff; sbdn5 = sysconf.hcdn[1] & 0xff; @@ -135,8 +135,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index f9a358e125..b272fda532 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -12,11 +12,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -65,22 +65,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge @@ -90,14 +90,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) // write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; //agp bridge - write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index d096b07905..87c812fb13 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) } } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); //??? What smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); -//Onboard AMD AC97 Audio +//Onboard AMD AC97 Audio smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); // Onboard AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) // AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); -//Onboard Serial ATA +//Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11); //Onboard Firewire smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) } -//Slot 4 PCIX 100/66 +//Slot 4 PCIX 100/66 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26 } diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c index 4a686020c8..af0ccabeb8 100644 --- a/src/mainboard/tyan/s2885/resourcemap.c +++ b/src/mainboard/tyan/s2885/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2885_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2885_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2885_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 7513c14e1b..f7ea579f6e 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -119,13 +119,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c index f7929b96c0..d76f1d6f47 100644 --- a/src/mainboard/tyan/s2891/resourcemap.c +++ b/src/mainboard/tyan/s2891/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s2891_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -182,7 +182,7 @@ static void setup_s2891_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s2891_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s2891_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -254,8 +254,8 @@ static void setup_s2891_resource_map(void) */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/tyan/s2892/dsdt.asl b/src/mainboard/tyan/s2892/dsdt.asl index 63a94bb932..d4242c3dc2 100644 --- a/src/mainboard/tyan/s2892/dsdt.asl +++ b/src/mainboard/tyan/s2892/dsdt.asl @@ -6,22 +6,22 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * + * the Free Software Foundation; version 2 of the License. + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* * ISA portions taken from QEMU acpi-dsdt.dsl. */ - + DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { #include "northbridge/amd/amdk8/amdk8_util.asl" diff --git a/src/mainboard/tyan/s2895/dsdt.asl b/src/mainboard/tyan/s2895/dsdt.asl index 268929fd9d..b3ac536d28 100644 --- a/src/mainboard/tyan/s2895/dsdt.asl +++ b/src/mainboard/tyan/s2895/dsdt.asl @@ -6,22 +6,22 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * + * the Free Software Foundation; version 2 of the License. + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* * ISA portions taken from QEMU acpi-dsdt.dsl. */ - + DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) { #include "northbridge/amd/amdk8/amdk8_util.asl" diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 18fa5e2bc3..c2a7ed00dd 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -15,7 +15,7 @@ config BOARD_TYAN_S2912 select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 - + config MAINBOARD_DIR string default tyan/s2912 @@ -25,7 +25,7 @@ config DCACHE_RAM_BASE hex default 0xc8000 depends on BOARD_TYAN_S2912 - + config DCACHE_RAM_SIZE hex default 0x08000 @@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE depends on BOARD_TYAN_S2912 config APIC_ID_OFFSET - hex + hex default 0x10 depends on BOARD_TYAN_S2912 @@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS depends on BOARD_TYAN_S2912 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_TYAN_S2912 @@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE depends on BOARD_TYAN_S2912 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_TYAN_S2912 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_TYAN_S2912 diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index a477b6891d..41a4a6ee8d 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index b21b1af4a7..9ff59d24ab 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -35,7 +35,7 @@ struct mb_sysconf_t mb_sysconf; unsigned pci1234x[] = -{ +{ // Here you only need to set value in pci1234 for HT-IO that could be // installed or not. // You may need to preset pci1234 for HTIO board, please refer to @@ -50,7 +50,7 @@ unsigned pci1234x[] = // 0x0000ff0 }; unsigned hcdnx[] = -{ +{ // HT Chain device num, actually it is unit id base of every ht device // in chain, assume every chain only have 4 ht device at most 0x20202020, diff --git a/src/mainboard/tyan/s2912/mb_sysconf.h b/src/mainboard/tyan/s2912/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/tyan/s2912/mb_sysconf.h +++ b/src/mainboard/tyan/s2912/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index bb14f3310b..a1de4c4f57 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/tyan/s2912_fam10/mb_sysconf.h +++ b/src/mainboard/tyan/s2912_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index 4a08e45d1b..4c2f2b59f4 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -68,7 +68,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -86,8 +86,8 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c index e95038dc37..352a7411e1 100644 --- a/src/mainboard/tyan/s4880/irq_tables.c +++ b/src/mainboard/tyan/s4880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 746d2a5d5e..a5094ba042 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - + { device_t dev; @@ -88,14 +88,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -133,14 +133,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -214,7 +214,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 3 PCIX 100/66 +//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s4880/resourcemap.c b/src/mainboard/tyan/s4880/resourcemap.c index cf45d55532..5fa85784ab 100644 --- a/src/mainboard/tyan/s4880/resourcemap.c +++ b/src/mainboard/tyan/s4880/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s4880_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s4880_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s4880_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 9933303278..753328c062 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -65,7 +65,7 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); @@ -85,7 +85,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_s4880_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index d2e5bbcf90..66f8c73e00 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -7,11 +7,11 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 1, link 1 == LDT 1 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on + device pci 0.0 on # chip drivers/lsi/53c1030 # device pci 4.0 on end # device pci 4.1 on end @@ -69,7 +69,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -81,12 +81,12 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on + device pci 1.3 on # chip drivers/i2c/i2cmux # pca9556 smbus mux # device i2c 18 on #0 pca9516 2, 1 # chip drivers/i2c/lm63 #cpu0 temp # device i2c 4c on end -# end +# end # end # device i2c 18 on #1 pca9516 1, 1 # chip drivers/generic/generic #dimm 1-0-0 @@ -163,7 +163,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... # device i2c 2e on end # end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid # device i2c 2a on end # end # chip drivers/generic/generic # Winbond HWM 0x92 @@ -181,16 +181,16 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end - + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end + end # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 off end # pci_regs_all diff --git a/src/mainboard/tyan/s4882/irq_tables.c b/src/mainboard/tyan/s4882/irq_tables.c index 4552b1f69c..92695abf7b 100644 --- a/src/mainboard/tyan/s4882/irq_tables.c +++ b/src/mainboard/tyan/s4882/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 4022dbdde1..81364262b7 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -79,24 +79,24 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - + { device_t dev; - + /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); if (bus_chain_0 == 0) { printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -134,14 +134,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -214,7 +214,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 3 PCIX 100/66 +//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s4882/resourcemap.c b/src/mainboard/tyan/s4882/resourcemap.c index 0e5be61a7c..2ee274960d 100644 --- a/src/mainboard/tyan/s4882/resourcemap.c +++ b/src/mainboard/tyan/s4882/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s4882_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s4882_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s4882_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index e1931fc2d4..9bec9de58b 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -1,4 +1,4 @@ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,7 +70,7 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); @@ -93,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -187,7 +187,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); - + enable_smbus(); memreset_setup(); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 74cd29a5f4..6d37e6bdf9 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { device_t dev; - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); diff --git a/src/mainboard/via/epia-m/acpi_tables.c b/src/mainboard/via/epia-m/acpi_tables.c index 69c526c1fe..9e42bc25a5 100644 --- a/src/mainboard/via/epia-m/acpi_tables.c +++ b/src/mainboard/via/epia-m/acpi_tables.c @@ -1,7 +1,7 @@ /* * coreboot ACPI Table support * written by Stefan Reinauer <stepan@openbios.org> - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * (C) Copyright 2004 Nick Barker * (C) Copyright 2005 Stefan Reinauer @@ -45,11 +45,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - + /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -60,10 +60,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb index e49090e789..ed543a21aa 100644 --- a/src/mainboard/via/epia-m/devicetree.cb +++ b/src/mainboard/via/epia-m/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/via/vt8623 device apic_cluster 0 on chip cpu/via/model_c3 - device apic 0 on end + device apic 0 on end end end @@ -44,7 +44,7 @@ chip northbridge/via/vt8623 end end - + device pci 11.1 on end # IDE # 2-4 non existant? device pci 11.5 on end # AC97 Audio @@ -55,7 +55,7 @@ chip northbridge/via/vt8623 chip southbridge/ricoh/rl5c476 register "enable_cf" = "1" device pci 0a.0 on end - device pci 0a.1 on end + device pci 0a.1 on end end end end diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl index b1b791d5f2..cbc8d24e41 100644 --- a/src/mainboard/via/epia-m/dsdt.asl +++ b/src/mainboard/via/epia-m/dsdt.asl @@ -2,12 +2,12 @@ * Minimalist ACPI DSDT table for EPIA-M / MII * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> * - * + * */ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { - /* + /* * Define the main processor */ Scope (\_PR) @@ -26,7 +26,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) /* Root of the bus hierarchy */ Scope (\_SB) { - /* Define how interrupt Link A is plumbed in */ + /* Define how interrupt Link A is plumbed in */ Device (LNKA) { Name (_HID, EisaId ("PNP0C0F")) @@ -36,7 +36,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -47,7 +47,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -59,16 +59,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKA - /* Define how interrupt Link B is plumbed in */ + } // End of LNKA + + /* Define how interrupt Link B is plumbed in */ Device (LNKB) { Name (_HID, EisaId ("PNP0C0F")) @@ -78,7 +78,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -89,7 +89,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -101,16 +101,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKB - /* Define how interrupt Link C is plumbed in */ + /* Define how interrupt Link C is plumbed in */ Device (LNKC) { Name (_HID, EisaId ("PNP0C0F")) @@ -120,7 +120,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -131,7 +131,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -143,16 +143,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKC - /* Define how interrupt Link D is plumbed in */ + /* Define how interrupt Link D is plumbed in */ Device (LNKD) { Name (_HID, EisaId ("PNP0C0F")) @@ -162,7 +162,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () @@ -173,7 +173,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -185,16 +185,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKD - + } // End of LNKD + + /* top PCI device */ Device (PCI0) { @@ -226,12 +226,12 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vt8623 Link C Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vt8623 Link D - Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A + Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D - Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA + Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD @@ -240,7 +240,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A - + Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C diff --git a/src/mainboard/via/epia-m/dsdt.c b/src/mainboard/via/epia-m/dsdt.c index fa878250f5..ca40651973 100644 --- a/src/mainboard/via/epia-m/dsdt.c +++ b/src/mainboard/via/epia-m/dsdt.c @@ -1,12 +1,12 @@ /* - * + * * Intel ACPI Component Architecture * ASL Optimizing Compiler version 20060127 [Apr 23 2006] * Copyright (C) 2000 - 2006 Intel Corporation * Supports ACPI Specification Revision 3.0a - * + * * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 - * + * * C source code output * */ diff --git a/src/mainboard/via/epia-m/irq_tables.c b/src/mainboard/via/epia-m/irq_tables.c index 551db214a8..f7776f6d20 100644 --- a/src/mainboard/via/epia-m/irq_tables.c +++ b/src/mainboard/via/epia-m/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 6a8446ac04..54feb26552 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -26,27 +26,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/via/vt8623/raminit.c" -static void enable_mainboard_devices(void) +static void enable_mainboard_devices(void) { device_t dev; - + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); - + if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } pci_write_config8(dev, 0x50, 0x80); pci_write_config8(dev, 0x51, 0x1f); #if 0 - // This early setup switches IDE into compatibility mode before PCI gets + // This early setup switches IDE into compatibility mode before PCI gets // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // // movb $0x09, %dl // movb $0x00, %dl // PCI_WRITE_CONFIG_BYTE #endif - /* we do this here as in V2, we can not yet do raw operations + /* we do this here as in V2, we can not yet do raw operations * to pci! */ dev += 0x100; /* ICKY */ @@ -58,7 +58,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x3d, 0); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { device_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; @@ -108,7 +108,7 @@ static void main(unsigned long bist) enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); - + /* Check all of memory */ #if 0 static const struct { @@ -129,7 +129,7 @@ static void main(unsigned long bist) } //dump_pci_devices(); - + print_spew("Leaving romstage.c:main()\n"); } diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 2e51c958d0..ac2e202d6a 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -547,7 +547,7 @@ void main(unsigned long bist) /* * For coreboot most time of S3 resume is the same as normal boot, * so some memory area under 1M become dirty, so before this happen, - * I need to backup the content of mem to top-mem. + * I need to backup the content of mem to top-mem. * * I will reserve the 1M top-men in LBIO table in coreboot_table.c * and recovery the content of 1M-mem in wakeup.c. @@ -628,7 +628,7 @@ void main(unsigned long bist) ); #endif - /* + /* * WAKE_MEM_INFO is inited in get_set_top_available_mem() * in tables.c these two memcpy() not not be enabled if set * the MTRR around this two lines. diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c index 1944b18de6..7cfa15114c 100644 --- a/src/mainboard/via/epia-n/acpi_tables.c +++ b/src/mainboard/via/epia-n/acpi_tables.c @@ -1,7 +1,7 @@ /* * coreboot ACPI Table support * written by Stefan Reinauer <stepan@openbios.org> - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9@btinternet.com>, and those portions * (C) Copyright 2004 Nick Barker * (C) Copyright 2005 Stefan Reinauer @@ -130,11 +130,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - + /* Align ACPI tables to 16byte */ start = ( start + 0x0f ) & -0x10; current = start; - + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -145,10 +145,10 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *)start, 0, current - start); - + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); - + /* * We explicitly add these tables later on: */ diff --git a/src/mainboard/via/epia-n/dsdt.asl b/src/mainboard/via/epia-n/dsdt.asl index 90731501ed..e50ee6b50c 100644 --- a/src/mainboard/via/epia-n/dsdt.asl +++ b/src/mainboard/via/epia-n/dsdt.asl @@ -3,7 +3,7 @@ * (C) Copyright 2009 Jon Harrison <jon.harrison@blueyonder.co.uk> * Heavily based on EPIA-M dstd.asl * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> - * + * */ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1) { diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 6ca72f293e..df9f82ea9b 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -41,8 +41,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) /* - * NOOB :: - * d0f0 - Device 0 Function 0 etc. + * NOOB :: + * d0f0 - Device 0 Function 0 etc. */ static const struct mem_controller ctrl = { .d0f0 = 0x0000, @@ -65,7 +65,7 @@ static void enable_mainboard_devices(void) { device_t dev; u8 reg; - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); @@ -95,10 +95,10 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x51, 0x9d); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { unsigned char shadowreg; - + shadowreg = pci_read_config8(ctrl.d0f3, 0x82); /* 0xf0000-0xfffff Read/Write*/ shadowreg |= 0x30; @@ -133,10 +133,10 @@ static void main(unsigned long bist) print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram(); - + /* setup cpu */ print_debug("Setup CPU Interface\n"); - c3_cpu_setup(ctrl.d0f2); + c3_cpu_setup(ctrl.d0f2); ddr_ram_setup(); @@ -144,7 +144,7 @@ static void main(unsigned long bist) print_debug("doing early_mtrr\n"); early_mtrr_init(); } - + //ram_check(0, 640 * 1024); print_spew("Leaving romstage.c:main()\n"); diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c index f3978d5e81..8b4352d25a 100644 --- a/src/mainboard/via/epia/irq_tables.c +++ b/src/mainboard/via/epia/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 202b117a42..66a8d203ed 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -27,13 +27,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" */ -static void enable_mainboard_devices(void) +static void enable_mainboard_devices(void) { device_t dev; /* dev 0 for southbridge */ - + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - + if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } @@ -41,7 +41,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); #if 0 - // This early setup switches IDE into compatibility mode before PCI gets + // This early setup switches IDE into compatibility mode before PCI gets // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // movb $0x09, %dl @@ -49,7 +49,7 @@ static void enable_mainboard_devices(void) // PCI_WRITE_CONFIG_BYTE // #endif - /* we do this here as in V2, we can not yet do raw operations + /* we do this here as in V2, we can not yet do raw operations * to pci! */ /* changed this to work correctly on later revisions of LB. @@ -64,7 +64,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x42, 0); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(void) { device_t dev = 0; unsigned char shadowreg; @@ -86,7 +86,7 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - + enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); @@ -98,7 +98,7 @@ static void main(unsigned long bist) sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); - + /* Check all of memory */ #if 0 ram_check(0x00000000, msr.lo); diff --git a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl index 4a294bcbaa..1505683563 100644 --- a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl +++ b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -22,67 +22,67 @@ Name (PICM, Package () { // _ADR PIN SRC IDX - Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0003FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0003FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0004FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0004FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0004FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0004FFFF, 0x03, LNKA, 0x00 }, - - Package () { 0x0005FFFF, 0x00, LNKC, 0x00 }, - Package () { 0x0005FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0005FFFF, 0x02, LNKA, 0x00 }, - Package () { 0x0005FFFF, 0x03, LNKB, 0x00 }, - - Package () { 0x0006FFFF, 0x00, LNKD, 0x00 }, - Package () { 0x0006FFFF, 0x01, LNKA, 0x00 }, - Package () { 0x0006FFFF, 0x02, LNKB, 0x00 }, - Package () { 0x0006FFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x0007FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0007FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0007FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0007FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0003FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0003FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0004FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKA, 0x00 }, + + Package () { 0x0005FFFF, 0x00, LNKC, 0x00 }, + Package () { 0x0005FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0005FFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0005FFFF, 0x03, LNKB, 0x00 }, + + Package () { 0x0006FFFF, 0x00, LNKD, 0x00 }, + Package () { 0x0006FFFF, 0x01, LNKA, 0x00 }, + Package () { 0x0006FFFF, 0x02, LNKB, 0x00 }, + Package () { 0x0006FFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x0007FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0007FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0007FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0007FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, }) Name (APIC, Package () { - Package () { 0x0003FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0003FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0003FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0003FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0003FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0003FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0003FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0003FFFF, 0x03, 0x00, 0x13 }, - Package () { 0x0004FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0004FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0004FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0004FFFF, 0x03, 0x00, 0x10 }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x10 }, - Package () { 0x0005FFFF, 0x00, 0x00, 0x12 }, - Package () { 0x0005FFFF, 0x01, 0x00, 0x13 }, - Package () { 0x0005FFFF, 0x02, 0x00, 0x10 }, - Package () { 0x0005FFFF, 0x03, 0x00, 0x11 }, + Package () { 0x0005FFFF, 0x00, 0x00, 0x12 }, + Package () { 0x0005FFFF, 0x01, 0x00, 0x13 }, + Package () { 0x0005FFFF, 0x02, 0x00, 0x10 }, + Package () { 0x0005FFFF, 0x03, 0x00, 0x11 }, - Package () { 0x0006FFFF, 0x00, 0x00, 0x13 }, - Package () { 0x0006FFFF, 0x01, 0x00, 0x10 }, - Package () { 0x0006FFFF, 0x02, 0x00, 0x11 }, - Package () { 0x0006FFFF, 0x03, 0x00, 0x12 }, + Package () { 0x0006FFFF, 0x00, 0x00, 0x13 }, + Package () { 0x0006FFFF, 0x01, 0x00, 0x10 }, + Package () { 0x0006FFFF, 0x02, 0x00, 0x11 }, + Package () { 0x0006FFFF, 0x03, 0x00, 0x12 }, - Package () { 0x0007FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0007FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0007FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0007FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0007FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0007FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0007FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0007FFFF, 0x03, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, }) diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index 63e64e61c0..a0bc380b78 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -22,122 +22,122 @@ Name (PICM, Package () { // _ADR PIN SRC IDX - Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0001FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0001FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, - - Package () { 0x0009FFFF, 0x00, LNKC, 0x00 }, - Package () { 0x0009FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0009FFFF, 0x02, LNKA, 0x00 }, - Package () { 0x0009FFFF, 0x03, LNKB, 0x00 }, - - Package () { 0x000AFFFF, 0x00, LNKD, 0x00 }, - Package () { 0x000AFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000AFFFF, 0x02, LNKB, 0x00 }, - Package () { 0x000AFFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x000BFFFF, 0x00, LNKD, 0x00 }, - Package () { 0x000BFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000BFFFF, 0x02, LNKB, 0x00 }, - Package () { 0x000BFFFF, 0x03, LNKC, 0x00 }, - - Package () { 0x000CFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000CFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000CFFFF, 0x02, LNKC, 0x00 }, - Package () { 0x000CFFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x000DFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000DFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000DFFFF, 0x02, LNKC, 0x00 }, - Package () { 0x000DFFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x01, LNKB, 0x00 }, - Package () { 0x000FFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0001FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0008FFFF, 0x00, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKA, 0x00 }, + + Package () { 0x0009FFFF, 0x00, LNKC, 0x00 }, + Package () { 0x0009FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0009FFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0009FFFF, 0x03, LNKB, 0x00 }, + + Package () { 0x000AFFFF, 0x00, LNKD, 0x00 }, + Package () { 0x000AFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000AFFFF, 0x02, LNKB, 0x00 }, + Package () { 0x000AFFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x000BFFFF, 0x00, LNKD, 0x00 }, + Package () { 0x000BFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000BFFFF, 0x02, LNKB, 0x00 }, + Package () { 0x000BFFFF, 0x03, LNKC, 0x00 }, + + Package () { 0x000CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x000CFFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x000DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x000DFFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x000FFFFF, 0x02, LNKC, 0x00 }, Package () { 0x000FFFFF, 0x03, LNKD, 0x00 }, - + /* USB controller */ - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0012FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0012FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0012FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0012FFFF, 0x03, LNKD, 0x00 } + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0012FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0012FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0012FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0012FFFF, 0x03, LNKD, 0x00 } }) Name (APIC, Package () { - Package () { 0x0001FFFF, 0x00, 0x00, 0x10 }, - Package () { 0x0001FFFF, 0x01, 0x00, 0x11 }, - Package () { 0x0001FFFF, 0x02, 0x00, 0x12 }, - Package () { 0x0001FFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, - - Package () { 0x0009FFFF, 0x00, 0x00, 0x12 }, - Package () { 0x0009FFFF, 0x01, 0x00, 0x13 }, - Package () { 0x0009FFFF, 0x02, 0x00, 0x10 }, - Package () { 0x0009FFFF, 0x03, 0x00, 0x11 }, - - Package () { 0x000AFFFF, 0x00, 0x00, 0x13 }, - Package () { 0x000AFFFF, 0x01, 0x00, 0x10 }, - Package () { 0x000AFFFF, 0x02, 0x00, 0x11 }, - Package () { 0x000AFFFF, 0x03, 0x00, 0x12 }, - - Package () { 0x000BFFFF, 0x00, 0x00, 0x13 }, - Package () { 0x000BFFFF, 0x01, 0x00, 0x10 }, - Package () { 0x000BFFFF, 0x02, 0x00, 0x11 }, - Package () { 0x000BFFFF, 0x03, 0x00, 0x12 }, - - Package () { 0x000CFFFF, 0x00, 0x00, 0x10 }, - Package () { 0x000CFFFF, 0x01, 0x00, 0x11 }, - Package () { 0x000CFFFF, 0x02, 0x00, 0x12 }, - Package () { 0x000CFFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x000DFFFF, 0x00, 0x00, 0x10 }, - Package () { 0x000DFFFF, 0x01, 0x00, 0x11 }, - Package () { 0x000DFFFF, 0x02, 0x00, 0x12 }, - Package () { 0x000DFFFF, 0x03, 0x00, 0x13 }, - - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x01, LNKA, 0x00 }, - Package () { 0x000FFFFF, 0x02, LNKA, 0x00 }, + Package () { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0001FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0001FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0001FFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x0008FFFF, 0x00, 0x00, 0x11 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x12 }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x13 }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x10 }, + + Package () { 0x0009FFFF, 0x00, 0x00, 0x12 }, + Package () { 0x0009FFFF, 0x01, 0x00, 0x13 }, + Package () { 0x0009FFFF, 0x02, 0x00, 0x10 }, + Package () { 0x0009FFFF, 0x03, 0x00, 0x11 }, + + Package () { 0x000AFFFF, 0x00, 0x00, 0x13 }, + Package () { 0x000AFFFF, 0x01, 0x00, 0x10 }, + Package () { 0x000AFFFF, 0x02, 0x00, 0x11 }, + Package () { 0x000AFFFF, 0x03, 0x00, 0x12 }, + + Package () { 0x000BFFFF, 0x00, 0x00, 0x13 }, + Package () { 0x000BFFFF, 0x01, 0x00, 0x10 }, + Package () { 0x000BFFFF, 0x02, 0x00, 0x11 }, + Package () { 0x000BFFFF, 0x03, 0x00, 0x12 }, + + Package () { 0x000CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x000CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x000CFFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x000DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x000DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x000DFFFF, 0x03, 0x00, 0x13 }, + + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x01, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x02, LNKA, 0x00 }, Package () { 0x000FFFFF, 0x03, LNKA, 0x00 }, /* USB controller. Hardwired in internal APIC mode, see PM pg. 137, "miscellaneous controls", footnote to "IDE interrupt select" */ - Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, - Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, - Package () { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package () { 0x0010FFFF, 0x03, 0x00, 0x17 }, - - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, - - Package () { 0x0012FFFF, 0x00, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x01, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x02, LNKD, 0x00 }, - Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x17 }, + + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0011FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0011FFFF, 0x03, LNKD, 0x00 }, + + Package () { 0x0012FFFF, 0x00, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x01, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x02, LNKD, 0x00 }, + Package () { 0x0012FFFF, 0x03, LNKD, 0x00 }, }) diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c index d31d8c55eb..737a5c8b12 100644 --- a/src/mainboard/via/vt8454c/acpi_tables.c +++ b/src/mainboard/via/vt8454c/acpi_tables.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index ada6c95690..d0ec7db2d0 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> * Copyright (C) 2007-2009 coresystems GmbH * @@ -22,7 +22,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { - /* + /* * Define the main processor */ Scope (\_PR) @@ -38,18 +38,18 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 }) Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 }) - Scope (\) { - Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode + Scope (\) { + Name (PICF , 0) // Global flag indicating whether to use PIC or APIC mode Method ( _PIC,1) // The OS is calling this { Store( Arg0 , PICF) } - } // end of \ scope + } // end of \ scope /* Root of the bus hierarchy */ Scope (\_SB) { - /* Define how interrupt Link A is plumbed in */ + /* Define how interrupt Link A is plumbed in */ Device (LNKA) { Name (_HID, EisaId ("PNP0C0F")) @@ -61,7 +61,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -79,7 +79,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -99,16 +99,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKA - /* Define how interrupt Link B is plumbed in */ + } // End of LNKA + + /* Define how interrupt Link B is plumbed in */ Device (LNKB) { Name (_HID, EisaId ("PNP0C0F")) @@ -120,7 +120,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -138,7 +138,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -159,16 +159,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKB - /* Define how interrupt Link C is plumbed in */ + /* Define how interrupt Link C is plumbed in */ Device (LNKC) { Name (_HID, EisaId ("PNP0C0F")) @@ -180,7 +180,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -198,7 +198,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -219,16 +219,16 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - + } // End of LNKC - /* Define how interrupt Link D is plumbed in */ + /* Define how interrupt Link D is plumbed in */ Device (LNKD) { Name (_HID, EisaId ("PNP0C0F")) @@ -240,7 +240,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (0x0B) } - /* Current Resources - return irq set up in BIOS */ + /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) { Name (CRSP, ResourceTemplate () { @@ -258,7 +258,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI - * happy + * happy */ Method (_PRS, 0, NotSerialized) { @@ -279,14 +279,14 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Set Resources - dummy function to keep Linux ACPI happy * Linux is more than happy not to tinker with irq - * assignments as long as the CRS and STA functions + * assignments as long as the CRS and STA functions * return good values */ Method (_SRS, 1, NotSerialized ) {} /* Disable - dummy function to keep Linux ACPI happy */ Method (_DIS, 0, NotSerialized ) {} - - } // End of LNKD + + } // End of LNKD /* PCI Root Bridge */ Device (PCI0) diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index dea85bc234..1a1efbf8f6 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -49,7 +49,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) { die("LPC bridge not found!!!\n"); } - // Disable GP3 + // Disable GP3 pci_write_config8(dev, 0x98, 0x00); // Disable mc97 diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index 7f5a53fc29..713849a098 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - + device pci d.0 on end # Ethernet 4 device pci a.0 on end # Ethernet 1 device pci b.0 on end # Ethernet 2 diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index 567790cede..c5506eaca5 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) return carry_over; } -#endif +#endif #endif // CONFIG_AMDMCT diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index 580f27831b..283e32e235 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -87,7 +87,7 @@ #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 #define DTL_TCL_MASK 7 -#define DTL_TCL_BASE 1 +#define DTL_TCL_BASE 1 #define DTL_TCL_MIN 3 #define DTL_TCL_MAX 6 #define DTL_TRCD_SHIFT 4 @@ -125,7 +125,7 @@ #define DTL_TRRD_BASE 2 #define DTL_TRRD_MIN 2 #define DTL_TRRD_MAX 5 -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ +#define DTL_MemClkDis_SHIFT 24 /* Channel A */ #define DTL_MemClkDis3 (1 << 26) #define DTL_MemClkDis2 (1 << 27) #define DTL_MemClkDis1 (1 << 28) @@ -135,16 +135,16 @@ #define DTL_MemClkDis0_S1g1 (0xa2 << 24) /* DTL_MemClkDis for m2 and s1g1 is different */ - + #define DRAM_TIMING_HIGH 0x8c #define DTH_TRWTTO_SHIFT 4 #define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 +#define DTH_TRWTTO_BASE 2 #define DTH_TRWTTO_MIN 2 #define DTH_TRWTTO_MAX 9 #define DTH_TWTR_SHIFT 8 #define DTH_TWTR_MASK 3 -#define DTH_TWTR_BASE 0 +#define DTH_TWTR_BASE 0 #define DTH_TWTR_MIN 1 #define DTH_TWTR_MAX 3 #define DTH_TWRRD_SHIFT 10 @@ -154,7 +154,7 @@ #define DTH_TWRRD_MAX 3 #define DTH_TWRWR_SHIFT 12 #define DTH_TWRWR_MASK 3 -#define DTH_TWRWR_BASE 1 +#define DTH_TWRWR_BASE 1 #define DTH_TWRWR_MIN 1 #define DTH_TWRWR_MAX 3 #define DTH_TRDRD_SHIFT 14 @@ -167,7 +167,7 @@ #define DTH_TREF_7_8_US 2 #define DTH_TREF_3_9_US 3 #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 +#define DTH_TRFC_MASK 7 #define DTH_TRFC_75_256M 0 #define DTH_TRFC_105_512M 1 #define DTH_TRFC_127_5_1G 2 @@ -185,12 +185,12 @@ #define DCL_DramTerm_No 0 #define DCL_DramTerm_75_OH 1 #define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 +#define DCL_DramTerm_50_OH 3 #define DCL_DrvWeak (1<<7) #define DCL_ParEn (1<<8) #define DCL_SelfRefRateEn (1<<9) #define DCL_BurstLength32 (1<<10) -#define DCL_Width128 (1<<11) +#define DCL_Width128 (1<<11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf #define DCL_UnBuffDimm (1<<16) @@ -312,7 +312,7 @@ #define DATC_CkeFineDelay_MASK 0x1f #define DATC_CkeFineDelay_BASE 0 #define DATC_CkeFineDelay_MIN 0 -#define DATC_CkeFineDelay_MAX 31 +#define DATC_CkeFineDelay_MAX 31 #define DATC_CkeSetup (1<<5) #define DATC_CsOdtFineDelay_SHIFT 8 #define DATC_CsOdtFineDelay_MASK 0x1f @@ -320,7 +320,7 @@ #define DATC_CsOdtFineDelay_MIN 0 #define DATC_CsOdtFineDelay_MAX 31 #define DATC_CsOdtSetup (1<<13) -#define DATC_AddrCmdFineDelay_SHIFT 16 +#define DATC_AddrCmdFineDelay_SHIFT 16 #define DATC_AddrCmdFineDelay_MASK 0x1f #define DATC_AddrCmdFineDelay_BASE 0 #define DATC_AddrCmdFineDelay_MIN 0 @@ -361,7 +361,7 @@ #define DRAM_DQS_RECV_ENABLE_TIME2 0x16 #define DRAM_DQS_RECV_ENABLE_TIME3 0x19 -/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 +/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 */ #define DRAM_CTRL_MISC 0xa0 @@ -417,7 +417,7 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, #define SCRUB_655_4us 15 #define SCRUB_1_31ms 16 #define SCRUB_2_62ms 17 -#define SCRUB_5_24ms 18 +#define SCRUB_5_24ms 18 #define SCRUB_10_49ms 19 #define SCRUB_20_97ms 20 #define SCRUB_42ms 21 @@ -530,7 +530,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if(sysinfo->nodes == 1) return; // in case only one cpu installed for(i=1; i<sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ @@ -563,7 +563,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) #ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else - printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); + printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif switch(sysinfo->mem_trained[i]) { case 0: //don't need train @@ -581,7 +581,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) print_debug("mem trained failed\n"); soft_reset(); #else - printk(BIOS_DEBUG, "mem trained failed\n"); + printk(BIOS_DEBUG, "mem trained failed\n"); hard_reset(); #endif } diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index e42158d92a..13c72fe846 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -56,7 +56,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk(BIOS_DEBUG, "before resume errata #%d\n", (is_post_rev_g) ? 270 : 125); - /* + /* 1. Restore memory controller registers as normal. 2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only) 3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register). diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 18b3109cf6..5d51f036cb 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -4,7 +4,7 @@ * devices which is done by the kernel * * written in 2003 by Eric Biederman - * + * * - Athlon64 workarounds by Stefan Reinauer * - "reset once" logic by Yinghai Lu */ @@ -24,7 +24,7 @@ /** * @brief Read resources for AGP aperture * - * @param + * @param * * There is only one AGP aperture resource needed. The resoruce is added to * the northbridge of BSP. @@ -64,7 +64,7 @@ static void mcf3_read_resources(device_t dev) static void set_agp_aperture(device_t dev) { struct resource *resource; - + resource = probe_resource(dev, 0x94); if (resource) { device_t pdev; @@ -78,7 +78,7 @@ static void set_agp_aperture(device_t dev) /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; - + /* Update the other northbriges */ pdev = 0; while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { @@ -90,7 +90,7 @@ static void set_agp_aperture(device_t dev) /* Don't set the GART Table base address */ pci_write_config32(pdev, 0x98, 0); - + /* Report the resource has been stored... */ report_resource_stored(pdev, resource, " <gart>"); } @@ -111,7 +111,7 @@ static void misc_control_init(struct device *dev) uint32_t cmd, cmd_ref; int needs_reset; struct device *f0_dev; - + printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); needs_reset = 0; @@ -125,7 +125,7 @@ static void misc_control_init(struct device *dev) if (is_cpu_pre_c0()) { /* Errata 58 - * Disable CPU low power states C2, C1 and throttling + * Disable CPU low power states C2, C1 and throttling */ cmd = pci_read_config32(dev, 0x80); cmd &= ~(1<<0); @@ -136,7 +136,7 @@ static void misc_control_init(struct device *dev) pci_write_config32(dev, 0x84, cmd ); /* Errata 66 - * Limit the number of downstream posted requests to 1 + * Limit the number of downstream posted requests to 1 */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { @@ -164,7 +164,7 @@ static void misc_control_init(struct device *dev) struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); - /* Errata 98 + /* Errata 98 * Set Clk Ramp Hystersis to 7 * Clock Power/Timing Low */ @@ -192,7 +192,7 @@ static void misc_control_init(struct device *dev) reg = 0x98 + (link * 0x20); link_type = pci_read_config32(f0_dev, reg); /* Only handle coherent link here please */ - if ((link_type & (LinkConnected|InitComplete|NonCoherent)) + if ((link_type & (LinkConnected|InitComplete|NonCoherent)) == (LinkConnected|InitComplete)) { cmd &= ~(0xff << (link *8)); diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index ad257d0ed6..7ad1b8004c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -567,7 +567,7 @@ static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. Socket 939 based Athlon64 * have dual channel capability, too, so we need a better test - * for Opterons. + * for Opterons. * However, all code uses is_opteron() to find out whether to * use dual channel, so if we really check for opteron here, we * need to fix up all code using this function, too. diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 6872883416..b89aa38d6a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -393,7 +393,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 110 = 8 bus clocks * 111 = 9 bus clocks * [ 7: 7] Reserved - * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, + * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, * minium write-to-read delay when both access the same chip select) * 00 = Reserved * 01 = 1 bus clocks @@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * registered DIMM is present * [19:19] Reserved * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) - * 0 = DRAM address and control signals are driven for one + * 0 = DRAM address and control signals are driven for one * MEMCLK cycle * 1 = One additional MEMCLK of setup time is provided on all * DRAM address and control signals except CS, CKE, and ODT; @@ -720,7 +720,7 @@ static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. M2 and S1G1 support dual * channel, too, but only support unbuffered DIMMs so we need a - * better test for Opterons. + * better test for Opterons. * However, all code uses is_opteron() to find out whether to * use dual channel, so if we really check for opteron here, we * need to fix up all code using this function, too. @@ -1221,7 +1221,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) csbase = value; canidate = index; } - + /* See if I have found a new canidate */ if (csbase == 0) { break; @@ -1640,7 +1640,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /*15*/ 200, 160, 120, 100, }; - + int index; msr_t msr; @@ -1659,7 +1659,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) unsigned fid_start; msr = rdmsr(0xc0010015); fid_start = (msr.lo & (0x3f << 24)); - + index = fid_start>>25; } @@ -1843,7 +1843,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * continue; } } - + } /* Make a second pass through the dimms and disable * any that cannot support the selected memclk and cas latency. @@ -2060,7 +2060,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me if (clocks < TT_MIN) { clocks = TT_MIN; } - + if (clocks > TT_MAX) { printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX); clocks = TT_MAX; @@ -3001,7 +3001,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #else int suspend = 0; #endif - + #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 unsigned cpu_f0_f1[8]; /* FIXME: How about 32 node machine later? */ diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 7b453bfc09..c56e51deb0 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -436,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i) unsigned fid_start; msr = rdmsr(0xc0010015); fid_start = (msr.lo & (0x3f << 24)); - + index = fid_start>>25; } @@ -600,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } for ( ; (channel < 2) && (!Errors); channel++) - { - print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); - - /* for each rank */ - /* there are four recriver pairs, loosely associated with CS */ - for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + { + print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); + + /* for each rank */ + /* there are four recriver pairs, loosely associated with CS */ + for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index 042bc9949b..82622cdc4c 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -231,7 +231,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) unsigned where; unsigned long reg; #if 0 - prink(BIOS_DEBUG, "%08x <- %08x\n", + prink(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]); #endif where = register_values[i]; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index fe4ae8c30c..3c4fa89e89 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3391,7 +3391,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, u8 max_dimms; // FIXME: skip for Ax - + dev = pDCTstat->dev_dct; /* Tri-state unused ODTs when motherboard termination is available */ diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 1b0214d9fd..1176744c87 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -40,10 +40,10 @@ static void enable_shadow(device_t dev) write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); - + optimize_xbus(dev); enable_shadow(dev); printk(BIOS_SPEW, "Calling enable_cache()\n"); @@ -63,7 +63,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver northbridge_driver __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_CYRIX, - .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, + .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; static void ram_resource(device_t dev, unsigned long index, @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) continue; ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); } - + tomk = ramreg << 10; /* Sort out the framebuffer size */ @@ -172,7 +172,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -211,5 +211,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_amd_gx1_ops = { CHIP_NAME("AMD GX1 Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c index f61a69b4f8..8525ce4d1f 100644 --- a/src/northbridge/amd/gx1/raminit.c +++ b/src/northbridge/amd/gx1/raminit.c @@ -12,7 +12,7 @@ U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express +Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse @@ -22,7 +22,7 @@ it with the version available from LANL. * rminnich@lanl.gov */ -/* SDRAM initialization for GX1 - translated from Christer Weinigel's +/* SDRAM initialization for GX1 - translated from Christer Weinigel's assembler version into C. Hamish Guthrie 10/4/2005 hamish@prodigi.ch @@ -53,7 +53,7 @@ unsigned int tval, i; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); outb(0x72, 0x80); } - + void enable_dimm(void) { @@ -93,12 +93,12 @@ unsigned int tval, i; tval &= ~PROGRAM_SDRAM; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - /* Refresh memory again */ + /* Refresh memory again */ tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); tval |= RFSHTST; for(i=0; i>NUM_REFRESH; i++) setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - + for(i=0; i<2000; i++) outb(0, 0xed); outb(0x74, 0x80); @@ -132,7 +132,7 @@ int failed_flag = 1; return (0x0070 << dimm_shift); else return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift)); - + } static unsigned int module_banks(int dimm_shift) @@ -229,7 +229,7 @@ unsigned int probe_config; #endif return(page_size_config << dimm_shift); } - + temp = ~(DIMM_PG_SZ << dimm_shift); probe_config = getGX1Mem(GX_BASE + MC_BANK_CFG); @@ -300,23 +300,23 @@ static int size_memory(int dimm_shift, unsigned int mem_config) mem_config &= (~(DIMM_MOD_BNK << dimm_shift)); mem_config |= (module_banks(dimm_shift)); - + print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); print_debug("\n"); mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift)); - + print_debug(" DIMM size: "); - print_debug_hex32(1 << + print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); print_debug("\n"); return (mem_config); } -static void sdram_init(void) +static void sdram_init(void) { unsigned int mem_config = 0x00700070; @@ -327,7 +327,7 @@ unsigned int mem_config = 0x00700070; setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */ setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */ setGX1Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */ - setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size + setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size 0x4000 -- 2 module banks 0x1000 -- 4 component banks 0x0700 -- DIMM size 512MB diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 620f56452d..f0b99e7e9d 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -61,7 +61,7 @@ static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { #ifdef UNUSED_CODE struct acpiinit { - unsigned short ioreg; + unsigned short ioreg; unsigned long regdata; unsigned short iolen; }; @@ -116,21 +116,21 @@ static void pmChipsetInit(void) port = (PMLogic_BASE + 0x034); val = 0x0A0 ; /* 5ms*/ outl(val, port); - + /* PM_WKD*/ port = (PMLogic_BASE + 0x030); outl(val, port); - + /* PM_SED*/ port = (PMLogic_BASE + 0x014); val = 0x04601 ; /* 5ms*/ outl(val, port); - + /* PM_SIDD*/ port = (PMLogic_BASE + 0x020); val = 0x08C02 ; /* 10ms*/ outl(val, port); - + /* GPIO24 OUT_AUX1 function is the external signal for 5535's * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem @@ -154,7 +154,7 @@ static void pmChipsetInit(void) * Programming of GPIO11 will be done by VSA PM code. During VSA * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks * should be On or Off. This is based on a Setup item. We do not want - * to leave GPIO11 enabled because of a Hawk board problem. With + * to leave GPIO11 enabled because of a Hawk board problem. With * GPIO11 enabled in S3, something is back-driving GPIO11 causing it * to float to 1.6-1.7V. */ @@ -188,7 +188,7 @@ static uint32_t FlashPort[] = { * ChipsetFlashSetup * * Flash LBARs need to be setup before VSA init so the PCI BARs have - * correct size info. Call this routine only if flash needs to be + * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). * **************************************************************************/ @@ -240,16 +240,16 @@ static void ChipsetFlashSetup(void) } - + /**************************************************************************** - * + * * ChipsetGeodeLinkInit * * Handle chipset specific GeodeLink settings here. * Called from GeodeLink init code. - * + * ****************************************************************************/ -static void +static void ChipsetGeodeLinkInit(void) { msr_t msr; @@ -269,7 +269,7 @@ ChipsetGeodeLinkInit(void) return; totalmem = sizeram() << 20 - 1; - totalmem >>= 12; + totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff; msr.lo = totalmem; @@ -292,7 +292,7 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); #ifdef UNUSED_CODE - /* we hope NEVER to be in coreboot when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; @@ -319,14 +319,14 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) msrnum = MSR_SB_USB2 + 8; wrmsr(msrnum, msr); } - + /* set hd IRQ */ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); /* Allow IO read and writes during a ATA DMA operation. */ /* This could be done in the HD rom but do it here for easier debugging. */ - + msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index a30ba78373..e59a838afe 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -4,7 +4,7 @@ #include <device/device.h> #include "chip.h" #include "northbridge.h" - + // FIXME handle UMA properly. #define VIDEO_MB 8 // MB of video memory diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e74a8e33f8..98acbc9f95 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -19,7 +19,7 @@ #define NORTHBRIDGE_FILE "northbridge.c" -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int @@ -128,7 +128,7 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); /* The IRQ steering values (in hex) are effectively dcba, where: - * <a> represents the IRQ for INTA, + * <a> represents the IRQ for INTA, * <b> represents the IRQ for INTB, * <c> represents the IRQ for INTC, and * <d> represents the IRQ for INTD. @@ -146,10 +146,10 @@ static void irq_init_steering(struct device *dev, u16 irq_map) { /* * setup_gx2_cache * - * Returns the amount of memory (in KB) available to the system. This is the + * Returns the amount of memory (in KB) available to the system. This is the * total amount of memory less the amount of memory reserved for SMM use. * - */ + */ static int setup_gx2_cache(void) { @@ -200,13 +200,13 @@ setup_gx2(void) membytes = size_kb * 1024; /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! - * so it is safe to use. You should NOT at this point call - * sizeram() directly. + * so it is safe to use. You should NOT at this point call + * sizeram() directly. */ /* we need to set 0x10000028 and 0x40000029 */ /* - * These two descriptors cover the range from 1 MB (0x100000) to + * These two descriptors cover the range from 1 MB (0x100000) to * SYSTOP (a.k.a. TOM, or Top of Memory) */ @@ -271,16 +271,16 @@ setup_gx2(void) static void enable_shadow(device_t dev) { - + } -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { unsigned long m; struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); - + enable_shadow(dev); irq_init_steering(dev, nb->irqmap); @@ -421,7 +421,7 @@ static void pci_domain_set_resources(device_t dev) continue; ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); } - + tomk = ramreg << 10; /* Sort out the framebuffer size */ @@ -455,7 +455,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -516,5 +516,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_amd_gx2_ops = { CHIP_NAME("AMD GX (previously GX2) Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 4ad5af23bc..7053f5e5d9 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -126,14 +126,14 @@ ShadowInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); if (msr.lo == 0) { - writeglmsr(gl); + writeglmsr(gl); } } -/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. +/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. * CLEAN ME UP */ -/* yes, this duplicates later code, but it seems that is how they want it done. +/* yes, this duplicates later code, but it seems that is how they want it done. */ static void SysmemInit(struct gliutable *gl) @@ -141,8 +141,8 @@ SysmemInit(struct gliutable *gl) msr_t msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* + * Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -165,7 +165,7 @@ SysmemInit(struct gliutable *gl) msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL0Init(struct gliutable *gl) { @@ -188,11 +188,11 @@ DMMGL0Init(struct gliutable *gl) { msr.hi |= (DMM_OFFSET >> 24); msr.lo = DMM_OFFSET << 8; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - + } static void DMMGL1Init(struct gliutable *gl) { @@ -211,7 +211,7 @@ DMMGL1Init(struct gliutable *gl) { /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */ printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -238,7 +238,7 @@ SMMGL0Init(struct gliutable *gl) { msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -254,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) { msr.hi |= (SMM_OFFSET >> 24); msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + wrmsr(gl->desc_name, msr); // MSR - See table above msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); @@ -265,31 +265,31 @@ GLIUInit(struct gliutable *gl){ while (gl->desc_type != GL_END){ switch(gl->desc_type){ - default: + default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); case SC_SHADOW: /* Check for a Shadow entry*/ ShadowInit(gl); break; - + case R_SYSMEM: /* check for a SYSMEM entry*/ SysmemInit(gl); break; - + case BMO_DMM: /* check for a DMM entry*/ DMMGL0Init(gl); break; - + case BM_DMM : /* check for a DMM entry*/ DMMGL1Init(gl); break; - + case BMO_SMM : /* check for a SMM entry*/ SMMGL0Init(gl); break; - + case BM_SMM : /* check for a SMM entry*/ - SMMGL1Init(gl); + SMMGL1Init(gl); break; } gl++; @@ -413,7 +413,7 @@ static void GLPCIInit(void){ /* */ /* 5535 NB Init*/ - /* */ + /* */ msrnum = GLPCI_ARB; msr = rdmsr(msrnum); msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; @@ -432,19 +432,19 @@ static void GLPCIInit(void){ msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; - + msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; - + msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; wrmsr(msrnum, msr); @@ -478,7 +478,7 @@ static void GLPCIInit(void){ /* * Modified:*/ /* **/ /* ***************************************************************************/ -static void +static void ClockGatingInit (void){ msr_t msr; struct msrinit *gating = ClockGatingDefault; @@ -489,7 +489,7 @@ ClockGatingInit (void){ NOSTACK bx, GetNVRAMValueBX cmp al, TVALUE_CG_OFF je gatingdone - + cmp al, TVALUE_CG_DEFAULT jb allon ja performance @@ -517,7 +517,7 @@ performance: } -static void +static void GeodeLinkPriority(void){ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; @@ -537,7 +537,7 @@ GeodeLinkPriority(void){ } - + /* * Get the GLIU0 shadow register settings * If the setShadow function is used then all shadow descriptors @@ -613,7 +613,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; - + // Set the Enable Register. msr = rdmsr(GLPCI_REN); @@ -667,7 +667,7 @@ static void setShadow(uint64_t shadowSettings) * Destroys: * **************************************************************************/ -static void +static void shadowRom(void) { uint64_t shadowSettings = getShadow(); @@ -688,7 +688,7 @@ shadowRom(void) * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 @@ -716,17 +716,17 @@ RCONFInit(void) while (1); } -// sysdescfound: +// sysdescfound: /* found the descriptor... get its contents */ msr = rdmsr(gl->desc_name); - /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the - * top 8 bits go into 0-7 of edx. + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - + // Set Default SYSMEM region properties msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8) @@ -739,7 +739,7 @@ RCONFInit(void) // Set ROMBASE cache properties. msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - + // now program RCONF_DEFAULT wrmsr(CPU_RCONF_DEFAULT, msr); @@ -776,15 +776,15 @@ northbridgeinit(void) GLIUInit(gliutables[i]); GeodeLinkPriority(); - + shadowRom(); - - // GeodeROM ensures that the BIOS waits the required 1 second before + + // GeodeROM ensures that the BIOS waits the required 1 second before // allowing anything to access PCI // PCIDelay(); - + RCONFInit(); - + // The cacheInit function in GeodeROM tests cache and, among other things, // makes sure all INVD instructions are treated as WBINVD. We do this // because we've found some programs which require this behavior. @@ -792,7 +792,7 @@ northbridgeinit(void) msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; wrmsr(CPU_DM_CONFIG0, msr); - + /* Now that the descriptor to memory is set up.*/ /* The memory controller needs one read to synch its lines before it can be used.*/ i = *(int *) 0; diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 898e31dcd4..c1b22a28a0 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -125,7 +125,7 @@ static unsigned int get_memory_speed(void) #define DEFAULT_MDIV 3 #define DEFAULT_VDIV 2 -#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 +#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200 static void pll_reset(void) { @@ -134,10 +134,10 @@ static void pll_reset(void) unsigned SyncBits; // store the sync bits in up ebx // clear the Bypass bit - + // If the straps say we are in bypass and the syspll is not AND there are no software // bits set then FS2 or something set up the PLL and we should not change it. - + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -145,15 +145,15 @@ static void pll_reset(void) // If the "we've already been here" flag is set, don't reconfigure the pll if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) ) { // we haven't configured the PLL; do it now - + // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the // correct Strap Table. post_code(POST_PLL_INIT); - + // configure for DDR msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // Use Manual settings // UseManual: post_code(POST_PLL_MANUAL); @@ -161,7 +161,7 @@ static void pll_reset(void) // DIV settings manually entered. // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // use gs and fs since we don't need them. - + // ProgramClocks: // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV // move everything into ebx @@ -174,7 +174,7 @@ static void pll_reset(void) // FbDIV MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT); - // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values + // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); @@ -192,15 +192,15 @@ static void pll_reset(void) // Check for Bypass mode. if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET) { - // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. + // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET; } else { - // CheckPCIsync: + // CheckPCIsync: // If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater // look up the real divider... if we get a 0 we have serious problems - if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % + if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) ) { SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET; @@ -234,13 +234,13 @@ static void pll_reset(void) msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET); msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); - + // You should never get here..... The chip has reset. post_code(POST_PLL_RESET_FAIL); while (1); } // we haven't configured the PLL; do it now - + } // End of Goodrich version of pll_reset /////////////////////////////////////////////////////////////////////////////// diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index b1cb1af6b3..3f99cab8ee 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -61,7 +61,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, - * it is documented in LX datasheet */ + * it is documented in LX datasheet */ /* load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); msr.lo |= ((0x01 << 27) | 0x01); @@ -85,10 +85,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* load RDSYNC */ msr = rdmsr(0x2000001f); msr.hi = 0x000ff310; - /* the above setting is supposed to be good for "slow" ram. We have found that for - * some dram, at some clock rates, e.g. hynix at 366/244, this will actually + /* the above setting is supposed to be good for "slow" ram. We have found that for + * some dram, at some clock rates, e.g. hynix at 366/244, this will actually * cause errors. The fix is to just set it to 0x310. Tested on 3 boards - * with 3 different type of dram -- Hynix, PSC, infineon. + * with 3 different type of dram -- Hynix, PSC, infineon. * I am leaving this comment here so that at some future time nobody is tempted * to mess with this setting -- RGM, 9/2006 */ diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index 57a485eedc..09eba0791a 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_LX bool select HAVE_HIGH_TABLES select GEODE_VSA - + config VIDEO_MB int default 8 diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index 85e6a45ba0..b245eea062 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -35,7 +35,7 @@ struct msrinit { }; static const struct msrinit geodelx_vga_msr[] = { - /* Enable the GLIU Memory routing to the hardware + /* Enable the GLIU Memory routing to the hardware * PDID1 : Port 4, GLIU0 * PBASE : 0x000A0 * PMASK : 0xFFFE0 @@ -71,9 +71,9 @@ void graphics_init(void) /* SoftVG initialization */ printk(BIOS_DEBUG, "Graphics init...\n"); - + geodelx_vga_msr_init(); - + /* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ @@ -94,7 +94,7 @@ void graphics_init(void) * so we can add the real value in megabytes */ - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); vrWrite(wClassIndex, wData); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4dd29d134f..6eba99d9df 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -262,7 +262,7 @@ void print_conf(void) #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int sizeram(void) diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 75d77f0305..9014fb1de3 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,9 +22,9 @@ #include <spd.h> #include "southbridge/amd/cs5536/cs5536.h" -static const unsigned char NumColAddr[] = { - 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +static const unsigned char NumColAddr[] = { + 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; static void banner(const char *s) @@ -35,8 +35,8 @@ static void banner(const char *s) static void hcf(void) { print_emerg("DIE\n"); - /* this guarantees we flush the UART fifos (if any) and also - * ensures that things, in general, keep going so no debug output + /* this guarantees we flush the UART fifos (if any) and also + * ensures that things, in general, keep going so no debug output * is lost */ while (1) @@ -231,7 +231,7 @@ static void set_refresh_rate(void) } msr = rdmsr(MC_CF07_DATA); - msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) + msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) << CF07_LOWER_REF_INT_SHIFT; wrmsr(MC_CF07_DATA, msr); } @@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == + if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_emerg("No memory in the system\n"); post_code(ERROR_NO_DIMMS); diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 500ea3e138..c116cb6296 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -16,8 +16,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -35,7 +35,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - + for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -61,8 +61,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -104,8 +104,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); #endif @@ -141,8 +141,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); #endif @@ -188,7 +188,7 @@ static inline void dump_smbus_registers(void) print_debug_hex8(device); #endif for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; status = smbus_read_byte(device, j); if (status < 0) { @@ -212,10 +212,10 @@ static inline void dump_smbus_registers(void) #endif } print_debug("\n"); - } + } } -static inline void dump_io_resources(unsigned port) +static inline void dump_io_resources(unsigned port) { int i; @@ -257,13 +257,13 @@ static inline void dump_mem(unsigned start, unsigned end) if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "\n%08x:", i); -#else +#else print_debug("\n"); print_debug_hex32(i); print_debug(":"); #endif } -#if CONFIG_USE_PRINTK_IN_CAR +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index c3b373c926..a2e4b245ee 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -112,11 +112,11 @@ static void pci_domain_set_resources(device_t dev) remapbase_r = pci_read_config16(mc_dev, 0xc6); remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); pci_write_config16(mc_dev, 0xc6, remapbase_r); - + remaplimit_r = pci_read_config16(mc_dev, 0xc8); remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); pci_write_config16(mc_dev, 0xc8, remaplimit_r); - + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .init = 0, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index 9f757e0f79..ac3bd41866 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -1,9 +1,9 @@ /* This was originally for the e7500, modified for e7501 - * The primary differences are that 7501 apparently can + * The primary differences are that 7501 apparently can * support single channel RAM (i haven't tested), * CAS1.5 is no longer supported, The ECC scrubber * now supports a mode to zero RAM and init ECC in one step - * and the undocumented registers at 0x80 require new + * and the undocumented registers at 0x80 require new * (undocumented) values determined by guesswork and * comparison w/ OEM BIOS values. * Steven James 02/06/2003 @@ -17,7 +17,7 @@ #include <stdlib.h> #include "e7501.h" -// Uncomment this to enable run-time checking of DIMM parameters +// Uncomment this to enable run-time checking of DIMM parameters // for dual-channel operation // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY @@ -52,10 +52,10 @@ struct dimm_size { /**********************************************************************************/ static const uint32_t refresh_frequency[] = { - /* Relative frequency (array value) of each E7501 Refresh Mode Select + /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) - * [0] disabled -> 0 + * [0] disabled -> 0 * [1] 15.6 usec -> 2 * [2] 7.8 usec -> 3 * [3] 64 usec -> 1 @@ -68,10 +68,10 @@ static const uint32_t refresh_frequency[] = { }; static const uint32_t refresh_rate_map[] = { - /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode + /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 - * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and + * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and * 64 clock (481 ns) (7) refresh. * [0] == 15.625 us -> 15.6 us * [1] == 3.9 us -> 481 ns @@ -110,7 +110,7 @@ static const long constant_register_values[] = { */ // Not everyone wants to be Super Micro Computer, Inc. // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), + // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), /* Undocumented * (DRAM Read Timing Control, if similar to 855PM?) @@ -125,11 +125,11 @@ static const long constant_register_values[] = { * CAS 2.0 values taken from Intel BIOS settings, others are a guess * and may be terribly wrong. Old values preserved as comments until I * figure this out for sure. - * e7501 docs claim that CAS1.5 is unsupported, so it may or may not + * e7501 docs claim that CAS1.5 is unsupported, so it may or may not * work at all. * Steven James 02/06/2003 */ - /* NOTE: values now configured in configure_e7501_cas_latency() based + /* NOTE: values now configured in configure_e7501_cas_latency() based * on SPD info and total number of DIMMs (per Intel) */ @@ -168,8 +168,8 @@ static const long constant_register_values[] = { /* DRB - DRAM Row Boundary Registers * 0x60 - 0x6F * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. + * memory address assigned to each pair of DIMMS, in 64MB + * granularity. */ // Conservatively say each row has 64MB of ram, we will fix this up later // NOTE: These defaults allow us to prime all of the DIMMs on the board @@ -178,7 +178,7 @@ static const long constant_register_values[] = { 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - /* DRA - DRAM Row Attribute Register + /* DRA - DRAM Row Attribute Register * 0x70 Row 0,1 * 0x71 Row 2,3 * 0x72 Row 4,5 @@ -312,7 +312,7 @@ static const long constant_register_values[] = { // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - // Default to dual-channel mode, ECC, 1-clock address/cmd hold + // Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), @@ -425,7 +425,7 @@ static const long constant_register_values[] = { 0xf4, 0x3f8ffffd, 0x40300002, #ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. + // SJM: Undocumented. // This will access D2:F0:0x50, is this correct?? 0x1050, 0xffffffcf, 0x00000030, #endif @@ -606,11 +606,11 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate // Return Value: dimm_size - log2(number of bits) for each side of the DIMM // Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + +// log2(# bits) = (# columns) + log2(data width) + // (# rows) + log2(banks per SDRAM) // -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size +// Note that it might be easier to use SPD byte 31 here, it has the +// DIMM size as a multiple of 4MB. The way we do it now we can size // both sides of an asymmetric dimm. // static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) @@ -653,7 +653,7 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) #ifdef VALIDATE_DIMM_COMPATIBILITY //---------------------------------------------------------------------------------- // Function: are_spd_values_equal -// Parameters: spd_byte_number - +// Parameters: spd_byte_number - // dimmN_address - SMBus addresses of DIMM sockets to interrogate // Return Value: 1 if both DIMM sockets report the same value for the specified // SPD parameter; 0 if the values differed or an error occurred. @@ -834,7 +834,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) //---------------------------------------------------------------------------------- // Function: do_ram_command -// Parameters: +// Parameters: // command - specifies the command to be sent to the DIMMs: // RAM_COMMAND_NOP - No Operation // RAM_COMMAND_PRECHARGE - Precharge all banks @@ -860,7 +860,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dram_controller_mode |= command; pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - // RAM_COMMAND_NORMAL is an exception. + // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. if (command != RAM_COMMAND_NORMAL) { @@ -897,7 +897,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // NOTE: 0x40 * 64 MB == 4 GB ASSERT(dimm_start_64M_multiple < 0x40); - // NOTE: 2^26 == 64 MB + // NOTE: 2^26 == 64 MB uint32_t dimm_start_address = dimm_start_64M_multiple << 26; @@ -921,7 +921,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // Parameters: jedec_mode_bits - for mode register set & extended mode register set // commands, bits 0-12 contain the register value in JEDEC format. // Return Value: None -// Description: Set the mode register of all DIMMs. The proper CAS# latency +// Description: Set the mode register of all DIMMs. The proper CAS# latency // setting is added to the mode bits specified by the caller. // static void set_ram_mode(uint16_t jedec_mode_bits) @@ -954,11 +954,11 @@ static void set_ram_mode(uint16_t jedec_mode_bits) //---------------------------------------------------------------------------------- // Function: configure_dimm_row_boundaries -// Parameters: +// Parameters: // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM -// total_dram_64M_multiple - total DRAM in the system (as a +// total_dram_64M_multiple - total DRAM in the system (as a // multiple of 64 MB) for DIMMs < dimm_index -// dimm_index - which DIMM pair is being processed +// dimm_index - which DIMM pair is being processed // (0..MAX_DIMM_SOCKETS_PER_CHANNEL) // Return Value: New multiple of 64 MB total DRAM in the system // Description: Configure the E7501's DRAM Row Boundary registers for the memory @@ -975,7 +975,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28)); - // In dual-channel mode, we are called only once for each pair of DIMMs. + // In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. // Convert single DIMM capacity to paired DIMM capacity @@ -994,7 +994,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), total_dram_64M_multiple); - // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair + // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair // (as a multiple of 64 MB) to the total capacity of the system if (dimm_log2_num_bits.side2 >= 29) total_dram_64M_multiple += @@ -1021,12 +1021,12 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits // Function: configure_e7501_ram_addresses // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the E7501's DRAM row boundary addresses and its Top Of -// Low Memory (TOLM). If necessary, set up a remap window so we -// don't waste DRAM that ordinarily would lie behind addresses +// Description: Program the E7501's DRAM row boundary addresses and its Top Of +// Low Memory (TOLM). If necessary, set up a remap window so we +// don't waste DRAM that ordinarily would lie behind addresses // reserved for memory-mapped I/O. // static void configure_e7501_ram_addresses(const struct mem_controller @@ -1181,11 +1181,11 @@ static void initialize_ecc(void) // Function: configure_e7501_dram_timing // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the DRAM Timing register of the E7501 (except for CAS# -// latency, which is assumed to have been programmed already), based +// Description: Program the DRAM Timing register of the E7501 (except for CAS# +// latency, which is assumed to have been programmed already), based // on the parameters of the various installed DIMMs. // static void configure_e7501_dram_timing(const struct mem_controller *ctrl, @@ -1255,7 +1255,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_row_precharge > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks else if (slowest_row_precharge > (15 << 2)) - dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks + dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks else dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks @@ -1267,7 +1267,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks else if (slowest_ras_cas_delay > (15 << 2)) - dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks + dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks else dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks @@ -1280,7 +1280,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_active_to_precharge_delay > 52) die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0 << 9); // 46-52 ns: 7 clocks + dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else @@ -1318,7 +1318,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // Function: configure_e7501_cas_latency // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Determine the shortest CAS# latency that the E7501 and all DIMMs @@ -1475,7 +1475,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, // Function: configure_e7501_dram_controller_mode // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the refresh interval so that we refresh no more often @@ -1583,7 +1583,7 @@ static void configure_e7501_dram_controller_mode(const struct // Function: configure_e7501_row_attributes // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the E7501's DRAM Row Attributes (DRA) registers @@ -1636,7 +1636,7 @@ static void configure_e7501_row_attributes(const struct mem_controller //---------------------------------------------------------------------------------- // Function: enable_e7501_clocks -// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see +// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Enable clock signals for populated DIMM sockets and disable them @@ -1690,8 +1690,8 @@ static void RAM_RESET_DDR_PTR(void) // Description: Set E7501 registers that are either independent of DIMM specifics, // or establish default settings that will be overridden when we // learn the specifics. -// This sets PCI configuration registers to known good values based -// on the table 'constant_register_values', which are a triple of +// This sets PCI configuration registers to known good values based +// on the table 'constant_register_values', which are a triple of // configuration register offset, mask, and bits to set. // static void ram_set_d0f0_regs(void) @@ -1748,8 +1748,8 @@ static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr) // Parameters: None // Return Value: None // Description: Set the E7501's (undocumented) RCOMP registers. -// Per the 855PM datasheet and IXP2800 HW Initialization Reference -// Manual, RCOMP registers appear to affect drive strength, +// Per the 855PM datasheet and IXP2800 HW Initialization Reference +// Manual, RCOMP registers appear to affect drive strength, // pullup/pulldown offset, and slew rate of various signal groups. // Comments below are conjecture based on apparent similarity // between the E7501 and these two chips. @@ -1980,9 +1980,9 @@ static void sdram_enable(int controllers, // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Configure SDRAM controller parameters that depend on -// characteristics of the DIMMs installed in the system. These -// characteristics are read from the DIMMs via the standard Serial +// Description: Configure SDRAM controller parameters that depend on +// characteristics of the DIMMs installed in the system. These +// characteristics are read from the DIMMs via the standard Serial // Presence Detect (SPD) interface. // static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -2011,7 +2011,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) } /* NOTE: configure_e7501_ram_addresses() is NOT called here. - * We want to keep the default 64 MB/row mapping until sdram_enable() is called, + * We want to keep the default 64 MB/row mapping until sdram_enable() is called, * even though the default mapping is almost certainly incorrect. * The default mapping makes it easy to initialize all of the DIMMs * even if the total system memory is > 4 GB. @@ -2028,7 +2028,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Do basic ram setup that does NOT depend on serial presence detect +// Description: Do basic ram setup that does NOT depend on serial presence detect // information (i.e. independent of DIMM specifics). // static void sdram_set_registers(const struct mem_controller *ctrl) diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 0d09414904..df0e9291a3 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -6,12 +6,12 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller // SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away // 0 == not present - uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; + uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c index 79a5cdaee1..1c0dad5ed9 100644 --- a/src/northbridge/intel/e7501/reset_test.c +++ b/src/northbridge/intel/e7501/reset_test.c @@ -7,12 +7,12 @@ */ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c index 133d1c4f88..d7a8048567 100644 --- a/src/northbridge/intel/e7520/memory_initialized.c +++ b/src/northbridge/intel/e7520/memory_initialized.c @@ -10,4 +10,4 @@ static inline int memory_initialized(void) //print_debug("\n"); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index efb7f0263b..93604b6cf7 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c index 07440e368e..ab73a713c2 100644 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ b/src/northbridge/intel/e7520/pciexp_porta.c @@ -7,16 +7,16 @@ #include <arch/io.h> #include "chip.h" #include <reset.h> - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -58,5 +58,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_porta1.c b/src/northbridge/intel/e7520/pciexp_porta1.c index 26605df8ab..c79535fbb0 100644 --- a/src/northbridge/intel/e7520/pciexp_porta1.c +++ b/src/northbridge/intel/e7520/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portb.c b/src/northbridge/intel/e7520/pciexp_portb.c index 668c665988..b20abdee6f 100644 --- a/src/northbridge/intel/e7520/pciexp_portb.c +++ b/src/northbridge/intel/e7520/pciexp_portb.c @@ -7,16 +7,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -38,5 +38,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portc.c b/src/northbridge/intel/e7520/pciexp_portc.c index fe55e661ec..d2706d1364 100644 --- a/src/northbridge/intel/e7520/pciexp_portc.c +++ b/src/northbridge/intel/e7520/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 836e6f8c7c..7f1b9d500a 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); + drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} static void pll_setup(uint32_t drc) { @@ -710,7 +710,7 @@ static void pll_setup(uint32_t drc) } mainboard_set_e7520_pll(pins); return; -} +} #define TIMEOUT_LOOPS 300000 @@ -724,7 +724,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180); @@ -741,10 +741,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -757,7 +757,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -784,14 +784,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -799,7 +799,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -817,7 +817,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -825,7 +825,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -914,7 +914,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1063,15 +1063,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1101,24 +1101,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1127,7 +1127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1137,12 +1137,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1150,7 +1150,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1160,10 +1160,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1188,7 +1188,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1200,7 +1200,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1210,17 +1210,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1228,33 +1228,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1279,7 +1279,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1292,9 +1292,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1303,7 +1303,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1311,7 +1311,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1331,22 +1331,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* Set the ecc mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/e7525/memory_initialized.c b/src/northbridge/intel/e7525/memory_initialized.c index 6eb31a8ca3..69bfdf32dd 100644 --- a/src/northbridge/intel/e7525/memory_initialized.c +++ b/src/northbridge/intel/e7525/memory_initialized.c @@ -6,4 +6,4 @@ static inline int memory_initialized(void) uint32_t drc; drc = pci_read_config32(NB_DEV, DRC); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 02bf119b96..559dc15b8b 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7525/pciexp_porta.c b/src/northbridge/intel/e7525/pciexp_porta.c index 3efc378ce0..4bae287df4 100644 --- a/src/northbridge/intel/e7525/pciexp_porta.c +++ b/src/northbridge/intel/e7525/pciexp_porta.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_porta1.c b/src/northbridge/intel/e7525/pciexp_porta1.c index 4f4204b7ad..b54ee8add6 100644 --- a/src/northbridge/intel/e7525/pciexp_porta1.c +++ b/src/northbridge/intel/e7525/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portb.c b/src/northbridge/intel/e7525/pciexp_portb.c index faf34dcfae..7b78b42e07 100644 --- a/src/northbridge/intel/e7525/pciexp_portb.c +++ b/src/northbridge/intel/e7525/pciexp_portb.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portc.c b/src/northbridge/intel/e7525/pciexp_portc.c index d7d75a2f9c..da6eaf70de 100644 --- a/src/northbridge/intel/e7525/pciexp_portc.c +++ b/src/northbridge/intel/e7525/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 0d18022020..be44434bf5 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); + pci_write_config32(ctrl->f0, DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(ctrl->f0, DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); + drc = pci_read_config32(ctrl->f0, DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} #define TIMEOUT_LOOPS 300000 @@ -695,7 +695,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, 0x88, 0xf0000180); @@ -712,10 +712,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -728,7 +728,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -755,14 +755,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -770,7 +770,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -788,7 +788,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -796,7 +796,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -883,7 +883,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1034,15 +1034,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1071,24 +1071,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(ctrl->f0, DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(ctrl->f0, DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(ctrl->f0, DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1097,7 +1097,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1107,12 +1107,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1120,7 +1120,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1130,10 +1130,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1158,7 +1158,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1170,7 +1170,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1180,17 +1180,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1198,33 +1198,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1249,7 +1249,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1259,9 +1259,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1270,7 +1270,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1278,7 +1278,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1298,22 +1298,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(ctrl->f0, MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); + pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index d6400d5859..42f624aaf7 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -59,7 +59,7 @@ static void pcie_bus_enable_resources(struct device *dev) if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); - + dev->command |= PCI_COMMAND_IO; dev->command |= PCI_COMMAND_MEMORY; } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5a4a328e44..7aeef29c84 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -34,7 +34,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, - PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, + PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; int max; @@ -89,7 +89,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -143,7 +143,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) { int i; int cum; - + for (i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -212,7 +212,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -258,7 +258,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* set device width (x8) */ dra |= (1 << 4); dra |= (1 << 10); - + /* set device type (registered) */ dra |= (1 << 14); @@ -278,7 +278,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, } -static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, +static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, u8 dimm_mask, u32 drc) { int i; @@ -409,7 +409,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, return val; } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -486,7 +486,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; int i; @@ -506,7 +506,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) u32 dimm,i; u32 data32; u32 t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, SDRC, 0xa0002c30); @@ -581,17 +581,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = data32 | (3 << 5); /* temp turn off ODT */ /* Set DRAM controller mode */ pci_write_config32(ctrl->f0, DRC, data32); - + /* Turn the clocks on */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* Program row size */ spd_set_ram_size(ctrl, mask); - + /* Program row attributes */ spd_set_row_attributes(ctrl, mask); - /* Program timing values */ + /* Program timing values */ mode_reg = spd_set_drt_attributes(ctrl, mask, drc); dump_dcal_regs(); @@ -608,14 +608,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ udelay(16); for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); print_debug("\n"); - write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); + write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -623,7 +623,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -633,10 +633,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS: Enable DLLs, set OCD calibration mode to default */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -648,7 +648,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* MRS: Reset DLLs */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -661,7 +661,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(48); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -671,11 +671,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ for (i = 0; i < 2; i++) { udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Refresh CS"); print_debug_hex8(cs); print_debug("\n"); @@ -688,7 +688,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* MRS: Set DLLs to normal */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -734,7 +734,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + dump_dcal_regs(); /* Adjust RCOMP */ @@ -746,11 +746,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dump_dcal_regs(); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { if (!(mask & (1<<cs))) continue; print_debug("clear memory CS"); @@ -779,10 +779,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) drc |= (1 << 29); drc |= (3 << 30); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ECC mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 4de84d3472..99f043f778 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -30,7 +30,7 @@ config SDRAMPWR_4DIMM This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong. - + If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option. diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index b437755213..34f4fd4fed 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 97311c5fdf..2edbe8ba3f 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -72,10 +72,10 @@ #define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */ #define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */ - + #define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ #define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ -#define BSPAD0 0xd0 /* These are free for our use. */ +#define BSPAD0 0xd0 /* These are free for our use. */ #define BSPAD1 0xd1 #define BSPAD2 0xd2 #define BSPAD3 0xd3 diff --git a/src/northbridge/intel/i440lx/Makefile.inc b/src/northbridge/intel/i440lx/Makefile.inc index f4ef7d49c2..c6b480940f 100644 --- a/src/northbridge/intel/i440lx/Makefile.inc +++ b/src/northbridge/intel/i440lx/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.o +driver-y += northbridge.o diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index ebe38afd51..7ebc002c72 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -33,7 +33,7 @@ #include "northbridge.h" #include "i440lx.h" -/* This code is mostly same as 440BX created by Uwe Hermann, +/* This code is mostly same as 440BX created by Uwe Hermann, * i done only very minor changes like renamed functions to 440lx etc * Maciej */ diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 61ddde98ca..d8cebb2808 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -61,14 +61,14 @@ static const long register_values[] = { // 0x04 == bit 10 // BASE is 0x8A but we dont want bit 9 or 10 have ENABLED so 0x8C PACCFG + 1, 0x38, 0x8c, - + DBC, 0x00, 0xC3, DRT, 0x00, 0xFF, DRT+1, 0x00, 0xFF, DRAMC, 0x00, 0x00, /* disable refresh for now. */ - DRAMT, 0x00, 0x00, + DRAMT, 0x00, 0x00, PAM0, 0x00, 0x30, // everything is a mem PAM1, 0x00, 0x33, @@ -109,7 +109,7 @@ static void do_ram_command(u32 command) u32 addr, addr_offset; /* Configure the RAM command. */ - reg16 = pci_read_config16(NB, DRAMXC); + reg16 = pci_read_config16(NB, DRAMXC); reg16 &= 0xff1f; /* Clear bits 7-5. */ reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, DRAMXC, reg16); @@ -127,7 +127,7 @@ static void do_ram_command(u32 command) addr_offset = 0; caslatency = 3; /* TODO: Dynamically get CAS latency later. */ - /* before translation it is + /* before translation it is * * M[02:00] Burst Length * M[03:03] Burst Type @@ -153,7 +153,7 @@ static void do_ram_command(u32 command) * must be left shifted by 3 * so possible formula is (caslatency <<4)|(burst_type << 1)|(burst length) * then << 3 shift to compensate shift in Memory Controller - */ + */ if (command == RAM_COMMAND_MRS) { if (caslatency == 3) addr_offset = 0x1d0; @@ -194,7 +194,7 @@ static void spd_enable_refresh(void) /* this chipset offer only two choices regarding refresh * refresh disabled, or refresh normal */ - + pci_write_config8(NB, DRAMC, reg | 0x01); reg = pci_read_config8(NB, DRAMC); @@ -216,10 +216,10 @@ static void northbridge_init(void) pci_write_config32(NB, APBASE, reg32); #ifdef DEBUG_RAM_SETUP - /* - * apbase dont get set still, no idea what i have doing wrong yet, + /* + * apbase dont get set still, no idea what i have doing wrong yet, * i am almost sure that somehow i set it by mistake once, but can't - * repeat that. + * repeat that. */ reg32 = pci_read_config32(NB, APBASE); PRINT_DEBUG("APBASE "); @@ -238,11 +238,11 @@ static void sdram_set_registers(void) int i, max; /* nice banner with FSB shown? do we have - * any standart policy about such things? + * any standart policy about such things? */ #if 0 uint16_t reg16; - reg16 = pci_read_config16(NB, PACCFG); + reg16 = pci_read_config16(NB, PACCFG); printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6'); #endif @@ -261,8 +261,8 @@ static void sdram_set_registers(void) reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); - /* - * i am not sure if that is needed, but was usefull + /* + * i am not sure if that is needed, but was usefull * for me to confirm what got written */ #ifdef DEBUG_RAM_SETUP @@ -282,7 +282,7 @@ static void sdram_set_registers(void) #endif } - PRINT_DEBUG("Northbridge atexit sdram set registers\n"); + PRINT_DEBUG("Northbridge atexit sdram set registers\n"); DUMPNORTH(); } @@ -293,9 +293,9 @@ static void sdram_set_spd_registers(void) u16 memsize = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t ds = 0; // dimm size + uint16_t ds = 0; // dimm size int j; - /* this code skips second bank on each socket (no idea how to fix it now) + /* this code skips second bank on each socket (no idea how to fix it now) */ PRINT_DEBUG("DIMM"); @@ -321,8 +321,8 @@ static void sdram_set_spd_registers(void) /* This is more or less crude hack - * allowing to run this target under qemu (even if that is not really - * same hardware emulated), + * allowing to run this target under qemu (even if that is not really + * same hardware emulated), * probably some kconfig expert option should be added to enable/disable * this nicelly */ @@ -333,10 +333,10 @@ static void sdram_set_spd_registers(void) // todo: support for bank with not equal sizes as per jedec standart? - + /* * because density is reported in units of 4Mbyte - * and rows in device are just value, + * and rows in device are just value, * and for setting registers we need value in 8Mbyte units */ @@ -348,7 +348,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRB + (2*i), memsize); pci_write_config8(NB, DRB + (2*i) + 1, memsize); if (ds > 0) { - /* i have no idea why pci_read_config16 not work for + /* i have no idea why pci_read_config16 not work for * me correctly here */ ds = pci_read_config8(NB, DRT+1); @@ -364,9 +364,9 @@ static void sdram_set_spd_registers(void) PRINT_DEBUG_HEX16(ds); PRINT_DEBUG("\n"); - /* + /* * modify DRT register if current row isn't empty - * code assume its SDRAM plugged (should check if its sdram or EDO, + * code assume its SDRAM plugged (should check if its sdram or EDO, * edo would have 0x00 as constand instead 0x10 for SDRAM * also this code is buggy because ignores second row of each dimm socket */ @@ -400,7 +400,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRAMC, 0x00); /* Cas latency 3, and other shouldbe properly from spd too */ - pci_write_config8(NB, DRAMT, 0xAC); + pci_write_config8(NB, DRAMT, 0xAC); /* TODO? */ pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40); diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 87b039f5f5..5bddbb60a3 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index fbb64f6088..81148e313d 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -312,7 +312,7 @@ static void set_dram_buffer_strength(void) SPD_NUM_DIMM_BANKS) > 1; d1.ss = !d1.ds; } - + buff_sc = 0; /* Tame the beast... */ @@ -350,7 +350,7 @@ static void set_dram_buffer_strength(void) buff_sc |= 1 << 14; if (!d0.size && d1.size) buff_sc |= 1 << 15; - + print_debug("BUFF_SC calculated to 0x"); print_debug_hex16(buff_sc); print_debug("\n"); @@ -371,7 +371,7 @@ static void sdram_set_registers(void) /* Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff); - + /* Set size for onboard-VGA framebuffer. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); reg8 &= 0x3f; /* Disable graphics (for now). */ diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h index 5a06dd171d..8c558a5699 100644 --- a/src/northbridge/intel/i82810/raminit.h +++ b/src/northbridge/intel/i82810/raminit.h @@ -27,7 +27,7 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50 -/* The following table has been bumped over to this header to avoid clutter in +/* The following table has been bumped over to this header to avoid clutter in * raminit.c. It's used to translate the value read from SPD Byte 31 to a value * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most * northbridges have some sort of simple calculation that can be done for this, @@ -38,7 +38,7 @@ /* TODO: Find a better way of doing this. */ static const uint8_t translate_spd_to_i82810[] = { - /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB + /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB * side can't be either, at least for now. */ /* TODO: For above case, only use the other side if > 4MB, and get some diff --git a/src/northbridge/intel/i82830/i82830_smihandler.c b/src/northbridge/intel/i82830/i82830_smihandler.c index 515be54acc..c9c7bcb27f 100644 --- a/src/northbridge/intel/i82830/i82830_smihandler.c +++ b/src/northbridge/intel/i82830/i82830_smihandler.c @@ -194,10 +194,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (obj_header->objnum == count) { #ifdef DEBUG_SMI_I82830 if (mbi_header->name_len == 0xff) { @@ -224,7 +224,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) + if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum); break; } @@ -251,10 +251,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (getobj->objnum == count) { printk(BIOS_DEBUG, "| |- len = %x\n", len); memcpy((void *)(getobj->buffer + OBJ_OFFSET), @@ -270,7 +270,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (getobj->banner.retsts == MSH_IF_NOT_FOUND) + if (getobj->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum); break; } diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 66b591b548..21c677960e 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -68,7 +68,7 @@ static void vga_init(device_t dev) #define PIPE_A_TV (1 << 3) #define PIPE_B_CRT (1 << 8) #define PIPE_B_TV (1 << 10) - printk(BIOS_DEBUG, "Enabling TV-Out\n"); + printk(BIOS_DEBUG, "Enabling TV-Out\n"); void runInt10(void); M.x86.R_AX = 0x5f64; M.x86.R_BX = 0x0001; // Set Display Device, force execution diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index c353776c12..2f7d5342a1 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -31,8 +31,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -51,7 +51,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -70,8 +70,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -93,8 +93,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -130,7 +130,7 @@ static inline void dump_smbus_registers(void) print_debug("smbus: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; if ((j & 0xf) == 0) { print_debug("\n"); @@ -147,5 +147,5 @@ static inline void dump_smbus_registers(void) print_debug_char(' '); } print_debug("\n"); - } + } } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 03bf3a93b6..3495fb6cfb 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -79,15 +79,15 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; uint32_t pci_tolm; - + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); - + if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -117,7 +117,7 @@ static void pci_domain_set_resources(device_t dev) /* Write the ram configuration registers, * preserving the reserved bits. */ - + /* Report the memory regions */ printk(BIOS_DEBUG, "tomk = %ld\n", tomk); printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); @@ -143,7 +143,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 5d71a27ca1..386eda10bb 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include <sdram_mode.h> #include <delay.h> @@ -28,7 +28,7 @@ * Set only what I need until it works, then make it figure things out on boot * assumes only one dimm is populated */ - + static void sdram_set_registers(const struct mem_controller *ctrl) { /* @@ -40,7 +40,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) static void spd_set_row_attributes(const struct mem_controller *ctrl) { uint16_t dra_reg; - + dra_reg = 0x7733; pci_write_config16(ctrl->d0, 0x50, dra_reg); } @@ -48,7 +48,7 @@ static void spd_set_row_attributes(const struct mem_controller *ctrl) static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) { uint32_t drc_reg; - + /* drc_reg = 0x00009101; */ drc_reg = 0x00009901; pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -57,7 +57,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) static void spd_set_dram_timing(const struct mem_controller *ctrl) { uint32_t drt_reg; - + drt_reg = 0x2a004405; pci_write_config32(ctrl->d0, 0x60, drt_reg); } @@ -73,7 +73,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl) static void spd_set_dram_pwr_management(const struct mem_controller *ctrl) { uint32_t pwrmg_reg; - + pwrmg_reg = 0x10f10430; pci_write_config32(ctrl->d0, 0x68, pwrmg_reg); } @@ -97,31 +97,31 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 0), 0x2c, 0x35808086); pci_write_config32(PCI_DEV(0, 0, 0), 0x48, 0xfec10000); pci_write_config32(PCI_DEV(0, 0, 0), 0x50, 0x00440100); - + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x11111000); - + pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0002); */ pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0044); /* pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0000); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); pci_write_config32(PCI_DEV(0, 0, 0), 0x5c, 0x33333333); /* pci_write_config32(PCI_DEV(0, 0, 0), 0x60, 0x0000390a); pci_write_config32(PCI_DEV(0, 0, 0), 0x74, 0x02006056); pci_write_config32(PCI_DEV(0, 0, 0), 0x78, 0x00800001); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); - + pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); + pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, 0x00001020); /* pci_write_config32(PCI_DEV(0, 0, 0), 0xfc, 0x00000109); */ /* 0:0.1 */ - pci_write_config32(ctrl->d0, 0x74, 0x00000001); + pci_write_config32(ctrl->d0, 0x74, 0x00000001); pci_write_config32(ctrl->d0, 0x78, 0x001fe974); pci_write_config32(ctrl->d0, 0x80, 0x00af0039); pci_write_config32(ctrl->d0, 0x84, 0x0000033c); @@ -133,7 +133,7 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(ctrl->d0, 0xb8, 0x000055d4); pci_write_config32(ctrl->d0, 0xbc, 0x024acd38); pci_write_config32(ctrl->d0, 0xc0, 0x00000003); - + /* 0:0.3 */ /* pci_write_config32(PCI_DEV(0, 0, 3), 0x2c, 0x35858086); @@ -147,12 +147,12 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 3), 0x7c, 0x0284007f); pci_write_config32(PCI_DEV(0, 0, 3), 0x84, 0x000000ef); */ - + /* pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0200); pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0400); */ - + /* pci_write_config32(PCI_DEV(0, 0, 3), 0xc4, 0x00000000); pci_write_config32(PCI_DEV(0, 0, 3), 0xd8, 0xff00c308); @@ -180,7 +180,7 @@ static void ram_command(const struct mem_controller *ctrl, uint32_t addr) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); @@ -195,12 +195,12 @@ static void ram_command_mrs(const struct mem_controller *ctrl, { uint32_t drc_reg; uint32_t adjusted_mode; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); pci_write_config8(ctrl->d0, 0x70, drc_reg); - /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ + /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9)); print_debug("Setting mode: "); print_debug_hex32(adjusted_mode + addr); @@ -211,7 +211,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl, static void set_initialize_complete(const struct mem_controller *ctrl) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg |= (1 << 29); pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -224,7 +224,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("Ram enable 1\n"); delay(); delay(); - + print_debug("Ram enable 2\n"); ram_command(ctrl, 1, 0); ram_command(ctrl, 1, rank1); @@ -242,17 +242,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1); delay(); delay(); - + print_debug("Ram enable 5\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1); - + print_debug("Ram enable 6\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - + print_debug("Ram enable 7\n"); for(i = 0; i < 8; i++) { ram_command(ctrl, 6, 0); @@ -270,19 +270,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command(ctrl, 7, rank1); delay(); delay(); - + print_debug("Ram enable 9\n"); set_initialize_complete(ctrl); - + delay(); delay(); delay(); - + print_debug("After configuration:\n"); /* dump_pci_devices(); */ - + /* - print_debug("\n\n***** RAM TEST *****\n"); + print_debug("\n\n***** RAM TEST *****\n"); ram_check(0, 0xa0000); ram_check(0x100000, 0x40000000); */ diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c index b48b4a3764..40f2f89973 100644 --- a/src/northbridge/intel/i855/reset_test.c +++ b/src/northbridge/intel/i855/reset_test.c @@ -28,12 +28,12 @@ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 6002a76876..dd095ca7b3 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -26,8 +26,8 @@ static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -64,8 +64,8 @@ static inline void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -86,7 +86,7 @@ static inline void dump_spd_registers(void) int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - + for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); @@ -94,7 +94,7 @@ static inline void dump_spd_registers(void) status = smbus_read_byte(device, i); if (status < 0) { printk(BIOS_DEBUG, "bad device: %02x\n", -status); - break; + break; } printk(BIOS_DEBUG, "%02x ", status); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index db24c93a0d..3c54b98855 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -199,7 +199,7 @@ static int sdram_capabilities_two_dimms_per_channel(void) return (reg8 != 0); } -// TODO check if we ever need this function +// TODO check if we ever need this function #if 0 static int sdram_capabilities_MEM4G_disable(void) { diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 80dcc8d1a9..3fbc358de5 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -45,7 +45,7 @@ static void memctrl_init(device_t dev) /* vlink mirror */ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN400_VLINK, 0); - + /* Setup Low Memory Top */ /* 0x47 == HA(32:25) */ /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */ @@ -104,7 +104,7 @@ static void memctrl_init(device_t dev) pci_write_config8(vlink_dev, 0x63, shadowreg); /* Activate VGA Frame Buffer */ - + reg8 = pci_read_config8(dev, 0xA0); reg8 |= 0x01; pci_write_config8(dev, 0xA0, reg8); @@ -268,7 +268,7 @@ static void cn400_domain_set_resources(device_t dev) (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } assign_resources(&dev->link[0]); - + printk(BIOS_SPEW, "Leaving %s.\n", __func__); } diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index a0b3aab1c5..7081c78744 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* +/* Automatically detect and set up ddr dram on the CN400 chipset. Assumes DDR400 memory as no attempt is made to clock the chipset down if slower memory is installed. @@ -33,9 +33,9 @@ #include <cpu/x86/mtrr.h> #include "cn400.h" -static void dimm_read(unsigned long bank,unsigned long x) +static void dimm_read(unsigned long bank,unsigned long x) { - //unsigned long eax; + //unsigned long eax; volatile unsigned long y; //eax = x; y = * (volatile unsigned long *) (x+ bank) ; @@ -50,7 +50,7 @@ static void print_val(char *str, int val) } /** - * Configure the bus between the CPU and the northbridge. This might be able to + * Configure the bus between the CPU and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers * should not be messed around with. These are too complex to explain short of * copying the datasheets into the comments, but most of these values are from @@ -66,27 +66,27 @@ static void c3_cpu_setup(device_t dev) /* Host bus interface registers (D0F2 0x50-0x67) */ /* Taken from CN700 and updated from running CN400 */ uint8_t reg8; - + /* Host Bus I/O Circuit (see datasheet) */ /* Host Address Pullup/down Driving */ pci_write_config8(dev, 0x70, 0x33); pci_write_config8(dev, 0x71, 0x44); pci_write_config8(dev, 0x72, 0x33); pci_write_config8(dev, 0x73, 0x44); - + /* Output Delay Stagger Control */ pci_write_config8(dev, 0x74, 0x70); - + /* AGTL+ I/O Circuit */ pci_write_config8(dev, 0x75, 0x08); - + /* AGTL+ Compensation Status */ pci_write_config8(dev, 0x76, 0x74); - + /* AGTL+ Auto Compensation Offest */ pci_write_config8(dev, 0x77, 0x00); pci_write_config8(dev, 0x78, 0x94); - + /* Request phase control */ pci_write_config8(dev, 0x50, 0xA8); @@ -94,71 +94,71 @@ static void c3_cpu_setup(device_t dev) pci_write_config8(dev, 0x60, 0x00); pci_write_config8(dev, 0x61, 0x00); pci_write_config8(dev, 0x62, 0x00); - + /* QW DRDY# Timing Control */ pci_write_config8(dev, 0x63, 0x00); pci_write_config8(dev, 0x64, 0x00); pci_write_config8(dev, 0x65, 0x00); - + /* Read Line Burst DRDY# Timing Control */ pci_write_config8(dev, 0x66, 0x00); pci_write_config8(dev, 0x67, 0x00); - + /* CPU Interface Control */ pci_write_config8(dev, 0x51, 0xFE); pci_write_config8(dev, 0x52, 0xEF); - + /* Arbitration */ pci_write_config8(dev, 0x53, 0x88); - + /* Write Policy & Reorder Latecy */ pci_write_config8(dev, 0x56, 0x00); - + /* Delivery-Trigger Control */ pci_write_config8(dev, 0x58, 0x00); - + /* IPI Control */ pci_write_config8(dev, 0x59, 0x30); - + /* CPU Misc Control */ pci_write_config8(dev, 0x5C, 0x00); - + /* Write Policy */ pci_write_config8(dev, 0x5d, 0xb2); - + /* Bandwidth Timer */ pci_write_config8(dev, 0x5e, 0x88); - + /* CPU Miscellaneous Control */ pci_write_config8(dev, 0x5f, 0xc7); - + /* CPU Miscellaneous Control */ pci_write_config8(dev, 0x55, 0x28); pci_write_config8(dev, 0x57, 0x69); - + /* CPU Host Bus Final Setup */ reg8 = pci_read_config8(dev, 0x54); reg8 |= 0x08; pci_write_config8(dev, 0x54, reg8); } - -static void ddr_ram_setup(void) + +static void ddr_ram_setup(void) { uint8_t b, c, bank, ma; uint16_t i; unsigned long bank_address; - - - print_debug("CN400 RAM init starting\n"); + + + print_debug("CN400 RAM init starting\n"); pci_write_config8(ctrl.d0f7, 0x75, 0x08); - - + + /* No Interleaving or Multi Page */ pci_write_config8(ctrl.d0f3, 0x69, 0x00); - pci_write_config8(ctrl.d0f3, 0x6b, 0x10); - + pci_write_config8(ctrl.d0f3, 0x6b, 0x10); + /* DRAM MA Map Type Device 0 Fn3 Offset 50-51 @@ -186,14 +186,14 @@ static void ddr_ram_setup(void) bank = 0x40; b = smbus_read_byte(0x50, SPD_NUM_ROWS); //print_val("\nNumber of Rows ", b); - + if( b >= 0x0d ){ // 256/512Mb - + if (b == 0x0e) bank = 0x48; else bank = 0x44; - + /* Read SPD byte 13, Primary DRAM width. */ @@ -205,7 +205,7 @@ static void ddr_ram_setup(void) /* Read SPD byte 4, Number of column addresses. - */ + */ b = smbus_read_byte(0x50, SPD_NUM_COLUMNS); //print_val("\nNo Columns ",b); if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr @@ -240,11 +240,11 @@ static void ddr_ram_setup(void) //c = 0; b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if( b & 0x02 ) - { + { c = 0x40; // 2GB bank |= 0x02; } - else if( b & 0x01) + else if( b & 0x01) { c = 0x20; // 1GB if (bank == 0x48) bank |= 0x01; @@ -255,12 +255,12 @@ static void ddr_ram_setup(void) c = 0x10; // 512MB if (bank == 0x44) bank |= 0x02; } - else if( b & 0x40) - { + else if( b & 0x40) + { c = 0x08; // 256MB if (bank == 0x44) bank |= 0x01; else bank |= 0x03; - } + } else if( b & 0x20) { c = 0x04; // 128MB @@ -276,7 +276,7 @@ static void ddr_ram_setup(void) // set bank zero size pci_write_config8(ctrl.d0f3, 0x40, c); - + // SPD byte 5 # of physical banks b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS); @@ -288,7 +288,7 @@ static void ddr_ram_setup(void) } /* else { - die("Only a single DIMM is supported by EPIA-N(L)\n"); + die("Only a single DIMM is supported by EPIA-N(L)\n"); } */ // set banks 1,2,3... @@ -299,13 +299,13 @@ static void ddr_ram_setup(void) pci_write_config8(ctrl.d0f3, 0x45,c); pci_write_config8(ctrl.d0f3, 0x46,c); pci_write_config8(ctrl.d0f3, 0x47,c); - + /* Top Rank Address Mirrored to the South Bridge */ /* over the VLink */ pci_write_config8(ctrl.d0f7, 0x57, (c << 1)); ma = bank; - + /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES); /* print_debug("\nCAS Supported "); @@ -322,7 +322,7 @@ static void ddr_ram_setup(void) print_val("\nCycle time at CL X-0.5 (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD); print_val("\nCycle time at CL X-1 (nS)", c); -*/ +*/ /* Scaling of Cycle Time SPD data */ /* 7 4 3 0 */ /* ns x0.1ns */ @@ -353,7 +353,7 @@ static void ddr_ram_setup(void) c = 0x10; } } - } + } /* Scale DRAM Cycle Time to tRP/tRCD */ /* 7 2 1 0 */ @@ -384,7 +384,7 @@ static void ddr_ram_setup(void) */ b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME); - + //print_val("\ntRP ",b); if ( b >= (5 * bank)) { c |= 0x03; // set tRP = 5T @@ -425,16 +425,16 @@ static void ddr_ram_setup(void) if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T - + /* Write DRAM Timing All Banks I */ pci_write_config8(ctrl.d0f3, 0x56, c); - + /* TWrite DRAM Timing All Banks II */ pci_write_config8(ctrl.d0f3, 0x57, 0x1a); - + /* DRAM arbitration timer */ pci_write_config8(ctrl.d0f3, 0x65, 0x99); - + /* DRAM Clock Device 0 Fn 3 Offset 68 */ @@ -453,7 +453,7 @@ static void ddr_ram_setup(void) /* 133MHz FSB / DDR333. See also c3_cpu_setup */ pci_write_config8(ctrl.d0f3, 0x68, 0x81); } - else + else { /* DRAM DDR Control Alert! Alert! This hardwires to */ /* 133MHz FSB / DDR266. See also c3_cpu_setup */ @@ -475,7 +475,7 @@ static void ddr_ram_setup(void) /* 4-Way Interleave With Multi-Paging (From Running System)*/ pci_write_config8(ctrl.d0f3, 0x69, c); - + /*DRAM Controller Internal Options */ pci_write_config8(ctrl.d0f3, 0x54, 0x01); @@ -484,7 +484,7 @@ static void ddr_ram_setup(void) /* DRAM Control */ pci_write_config8(ctrl.d0f3, 0x6e, 0x80); - + /* Disable refresh for now */ pci_write_config8(ctrl.d0f3, 0x6a, 0x00); @@ -497,7 +497,7 @@ static void ddr_ram_setup(void) /* DRAM Bus Turn-Around Setting */ pci_write_config8(ctrl.d0f3, 0x60, 0x01); - + /* Disable DRAM refresh */ pci_write_config8(ctrl.d0f3,0x6a,0x0); @@ -524,7 +524,7 @@ static void ddr_ram_setup(void) c = b | 0x40; pci_write_config8(ctrl.d0f3, 0xb0, c); - + /* Set RAM Decode method */ pci_write_config8(ctrl.d0f3, 0x55, 0x0a); @@ -542,14 +542,14 @@ static void ddr_ram_setup(void) CPU FSB Operating Frequency (bits 7:5) 000 : 100MHz 001 : 133MHz - 010 : 200MHz + 010 : 200MHz 011->111 : Reserved - + SDRAM BL8 (4) - + Don't change Frequency from power up defaults This seems to lockup the RAM interface - */ + */ c = pci_read_config8(ctrl.d0f2, 0x54); c |= 0x10; pci_write_config8(ctrl.d0f2, 0x54, c); @@ -566,7 +566,7 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_NOP; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); /* read a double word from any address of the dimm */ dimm_read(bank_address,0x1f000); @@ -576,7 +576,7 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); dimm_read(bank_address,0x1f000); @@ -584,8 +584,8 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - /* TODO: Bank Addressing for Different Numbers of Row Addresses */ + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + /* TODO: Bank Addressing for Different Numbers of Row Addresses */ dimm_read(bank_address,0x2000); udelay(1); dimm_read(bank_address,0x800); @@ -595,14 +595,14 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_PRECHARGE; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); dimm_read(bank_address,0x1f200); /* CBR Cycle Enable */ c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_CBR; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); /* Read 8 times */ for (c=0;c<8;c++) { @@ -614,10 +614,10 @@ static void ddr_ram_setup(void) c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL); c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_MSR_LOW; - pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); + pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); -/* +/* Mode Register Definition with adjustement so that address calculation is correct - 64 bit technology, therefore a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented @@ -626,9 +626,9 @@ static void ddr_ram_setup(void) MR[9-7] CAS Latency MR[6] Burst Type 0 = sequential, 1 = interleaved MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved - MR[0-2] dont care + MR[0-2] dont care - CAS Latency + CAS Latency 000 reserved 001 reserved 010 2 @@ -657,24 +657,24 @@ static void ddr_ram_setup(void) c &= 0xf8; /* Clear bits 2-0. */ c |= RAM_COMMAND_NORMAL; pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c); - + bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000; } // end of for each bank - + /* Set DRAM DQS Output Control */ pci_write_config8(ctrl.d0f3, 0x79, 0x11); - + /* Set DQS A/B Input delay to defaults */ pci_write_config8(ctrl.d0f3, 0x7A, 0xA1); - pci_write_config8(ctrl.d0f3, 0x7B, 0x62); + pci_write_config8(ctrl.d0f3, 0x7B, 0x62); /* DQS Duty Cycle Control */ pci_write_config8(ctrl.d0f3, 0xED, 0x11); /* SPD byte 5 # of physical banks */ b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1; - + /* determine low bond */ if( b == 2) bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000; @@ -720,10 +720,10 @@ static void ddr_ram_setup(void) // if everything verified then found low bond break; - + } - print_val("\nLow Bond ",i); - if( i < 0xff ){ + print_val("\nLow Bond ",i); + if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ pci_write_config8(ctrl.d0f3,0x70, i); @@ -774,24 +774,24 @@ static void ddr_ram_setup(void) /* Set DQS ChA Data Output Delay to the default */ pci_write_config8(ctrl.d0f3, 0x71, 0x65); - + /* Set Ch B DQS Output Delays */ pci_write_config8(ctrl.d0f3, 0x72, 0x2a); pci_write_config8(ctrl.d0f3, 0x73, 0x29); - + pci_write_config8(ctrl.d0f3, 0x78, 0x03); /* Mystery Value */ pci_write_config8(ctrl.d0f3, 0x67, 0x50); - + /* Enable Toggle Limiting */ pci_write_config8(ctrl.d0f4, 0xA3, 0x80); - + /* DRAM refresh rate Device 0 F3 Offset 6a - TODO :: Fix for different DRAM technologies - other than 512Mb and DRAM Freq - Units of 16 DRAM clock cycles - 1. + TODO :: Fix for different DRAM technologies + other than 512Mb and DRAM Freq + Units of 16 DRAM clock cycles - 1. */ //c = pci_read_config8(ctrl.d0f3, 0x68); //c &= 0x07; @@ -799,13 +799,13 @@ static void ddr_ram_setup(void) //print_val("SPD_REFRESH = ", b); pci_write_config8(ctrl.d0f3,0x6a,0x65); - + /* SMM and APIC decoding, we do not use SMM */ b = 0x29; pci_write_config8(ctrl.d0f3, 0x86, b); /* SMM and APIC decoding mirror */ pci_write_config8(ctrl.d0f7, 0xe6, b); - + /* Open Up the Rest of the Shadow RAM */ pci_write_config8(ctrl.d0f3,0x80,0xff); pci_write_config8(ctrl.d0f3,0x81,0xff); @@ -816,10 +816,10 @@ static void ddr_ram_setup(void) pci_write_config8(ctrl.d0f7,0x76,0x50); pci_write_config8(ctrl.d0f7,0x71,0xc8); - + /* VGA device. */ pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15)); pci_write_config16(ctrl.d0f3, 0xa4, 0x0010); print_debug("CN400 raminit.c done\n"); -} +} diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index cf9c54be23..511079b03a 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -62,7 +62,7 @@ static int via_cn400_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -70,7 +70,7 @@ static int via_cn400_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 63dab5b3e0..20b0afeb6e 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -51,7 +51,7 @@ static void do_ram_command(device_t dev, u8 command) } /** - * Configure the bus between the CPU and the northbridge. This might be able to + * Configure the bus between the CPU and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers * should not be messed around with. These are too complex to explain short of * copying the datasheets into the comments, but most of these values are from @@ -244,7 +244,7 @@ static void sdram_set_size(const struct mem_controller *ctrl) } /** - * Set up various RAM and other control registers statically. Some of these may + * Set up various RAM and other control registers statically. Some of these may * not be needed, other should be done with SPD info, but that's a project for * the future. */ @@ -422,7 +422,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* - * (E)MRS values are from the BPG. No direct explanation is given, but + * (E)MRS values are from the BPG. No direct explanation is given, but * they should somehow conform to the JEDEC DDR2 SDRAM Specification * (JESD79-2C). */ diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 69f188b01e..33d1fe0071 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -62,7 +62,7 @@ static int via_cn700_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -70,7 +70,7 @@ static int via_cn700_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } diff --git a/src/northbridge/via/cx700/cx700_early_serial.c b/src/northbridge/via/cx700/cx700_early_serial.c index a0d7301e20..3f5020f670 100644 --- a/src/northbridge/via/cx700/cx700_early_serial.c +++ b/src/northbridge/via/cx700/cx700_early_serial.c @@ -61,7 +61,7 @@ static void enable_cx700_serial(void) // turn on pnp cx700_writepnpaddr(0x87); cx700_writepnpaddr(0x87); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address cx700_writepnpaddr(0x7); cx700_writepnpdata(0x2); diff --git a/src/northbridge/via/cx700/cx700_vga.c b/src/northbridge/via/cx700/cx700_vga.c index e36062d9d2..2999907616 100644 --- a/src/northbridge/via/cx700/cx700_vga.c +++ b/src/northbridge/via/cx700/cx700_vga.c @@ -120,7 +120,7 @@ static int via_cx700_int15_handler(struct eregs *regs) break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } @@ -170,7 +170,7 @@ static void vga_init(device_t dev) // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); // this is how it looks: vga_enable_console(); - + /* It's not clear if these need to be programmed before or after * the VGA bios runs. Try both, clean up later */ /* Set memory rate to 200MHz */ diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 6693724ad4..5694ea31aa 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -452,7 +452,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) /* To store DDRII frequence */ pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ, val); - /* Manual reset and adjust DLL when DRAM change frequency + /* Manual reset and adjust DLL when DRAM change frequency * This is a necessary sequence. */ udelay(2000); @@ -1623,7 +1623,7 @@ static void sdram_enable(const struct mem_controller *ctrl) u8 mask; u8 val; } b0d1f0[] = { - { 0x40, 0x00, 0x8b}, + { 0x40, 0x00, 0x8b}, { 0x41, 0x80, 0x43}, { 0x42, 0x00, 0x62}, { 0x43, 0x00, 0x44}, diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 5af7836a93..8fca0eae2c 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -18,7 +18,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -108,16 +108,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); @@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { @@ -182,5 +182,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_via_vt8601_ops = { CHIP_NAME("VIA VT8601 Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c index cb13ad4e98..2365b8d8fb 100644 --- a/src/northbridge/via/vt8601/raminit.c +++ b/src/northbridge/via/vt8601/raminit.c @@ -13,7 +13,7 @@ U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express +Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse @@ -107,14 +107,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(north, 0x78, 0x01); print_debug_hex8(pci_read_config8(north, 0x78)); - // dram control, see the book. + // dram control, see the book. #if DIMM_PC133 pci_write_config8(north, 0x68, 0x52); #else pci_write_config8(north, 0x68, 0x42); #endif - // dram control, see the book. + // dram control, see the book. pci_write_config8(north, 0x6B, 0x0c); // Initial setting, 256MB in each bank, will be rewritten later. @@ -125,7 +125,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) pci_write_config8(north, 0x5D, 0x80); pci_write_config8(north, 0x5E, 0xA0); pci_write_config8(north, 0x5F, 0xC0); - // It seems we have to take care of these 2 registers as if + // It seems we have to take care of these 2 registers as if // they are bank 6 and 7. pci_write_config8(north, 0x56, 0xC0); pci_write_config8(north, 0x57, 0xC0); @@ -149,7 +149,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) #endif // dram frequency select. - // enable 4K pages for 64M dram. + // enable 4K pages for 64M dram. #if DIMM_PC133 pci_write_config8(north, 0x69, 0x3c); #else @@ -181,8 +181,8 @@ static unsigned long spd_module_size(unsigned char slot) /* unsigned int module = ((0x50 + slot) << 1) + 1; */ unsigned int module = 0x50 + slot; - /* is the module there? if byte 2 is not 4, then we'll assume it - * is useless. + /* is the module there? if byte 2 is not 4, then we'll assume it + * is useless. */ print_info("Slot "); print_info_hex8(slot); @@ -292,7 +292,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config8(north, 0x6C, 0x01); print_debug("NOP\n"); /* wait 200us */ - // You need to do the memory reference. That causes the nop cycle. + // You need to do the memory reference. That causes the nop cycle. dimms_read(0); udelay(400); print_debug("PRECHARGE\n"); @@ -340,7 +340,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dimms_read(0); udelay(200); print_debug("set ref. rate\n"); - // Set the refresh rate. + // Set the refresh rate. #if DIMM_PC133 pci_write_config8(north, 0x6A, 0x86); #else @@ -370,7 +370,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set the MA map type. * - * 0xa should be another option, but when + * 0xa should be another option, but when * it would be used is unknown. */ diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 4920ec3973..7ba9cd6316 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -21,7 +21,7 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { device_t fb_dev; unsigned long fb; @@ -40,7 +40,7 @@ static void northbridge_init(device_t dev) pci_write_config8(dev, 0x84, 0x80); pci_write_config16(dev, 0x80, 0x610f); pci_write_config32(dev, 0x88, 0x00000002); - + fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0); if (fb_dev) { /* Fixup GART and framebuffer addresses properly. @@ -168,16 +168,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024); @@ -210,7 +210,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c index f57127b3da..295011b785 100644 --- a/src/northbridge/via/vt8623/raminit.c +++ b/src/northbridge/via/vt8623/raminit.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* +/* Automatically detect and set up ddr dram on the CLE266 chipset. Assumes DDR memory, though chipset also supports SDRAM Assumes at least 266Mhz memory as no attempt is made to clock @@ -35,9 +35,9 @@ -void dimm_read(unsigned long bank,unsigned long x) +void dimm_read(unsigned long bank,unsigned long x) { - //unsigned long eax; + //unsigned long eax; volatile unsigned long y; //eax = x; y = * (volatile unsigned long *) (x+ bank) ; @@ -46,7 +46,7 @@ void dimm_read(unsigned long bank,unsigned long x) void -dumpnorth(device_t north) +dumpnorth(device_t north) { uint16_t r, c; for(r = 0; r < 256; r += 16) { @@ -65,7 +65,7 @@ void print_val(char *str, int val) print_debug_hex8(val); } -static void ddr_ram_setup(const struct mem_controller *ctrl) +static void ddr_ram_setup(const struct mem_controller *ctrl) { device_t north = (device_t) 0; uint8_t b, c, bank; @@ -75,7 +75,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_debug("vt8623 init starting\n"); north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0); north = 0; - + pci_write_config8(north,0x75,0x08); @@ -105,7 +105,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_val("Detecting Memory\nNumber of Banks ",b); if( b != 2 ){ // not 16 Mb type - + /* Read SPD byte 3, Number of row addresses. */ @@ -126,7 +126,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) 64/128Mb chip Read SPD byte 4, Number of column addresses. -*/ +*/ b = smbus_read_byte(0xa0,4); print_val("\nNo Columns ",b); if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr @@ -153,7 +153,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) if( b & 0x02 ) c = 0x80; // 2GB else if( b & 0x01) c = 0x40; // 1GB else if( b & 0x80) c = 0x20; // 512Mb - else if( b & 0x40) c = 0x10; // 256Mb + else if( b & 0x40) c = 0x10; // 256Mb else if( b & 0x20) c = 0x08; // 128Mb else if( b & 0x10) c = 0x04; // 64Mb else if( b & 0x08) c = 0x02; // 32Mb @@ -191,7 +191,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); - + if( b & 0x10 ){ // DDR offering optional CAS 3 print_debug("\nStarting at CAS 3"); @@ -405,7 +405,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* MSR Enable */ pci_write_config8(north,0x6b,0x13); -/* +/* Mode Register Definition with adjustement so that address calculation is correct - 64 bit technology, therefore a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented @@ -414,9 +414,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) MR[9-7] CAS Latency MR[6] Burst Type 0 = sequential, 1 = interleaved MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved - MR[0-2] dont care + MR[0-2] dont care - CAS Latency + CAS Latency 000 reserved 001 reserved 010 2 @@ -498,10 +498,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) // if everything verified then found low bond break; - + } - print_val("\nLow Bond ",i); - if( i < 0xff ){ + print_val("\nLow Bond ",i); + if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ pci_write_config8(north,0x68,i ^ (i>>1) ); @@ -588,7 +588,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) pci_write_config8(north,0x71,0xc8); - + /* graphics aperture base */ diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 7dbb7831b1..78ffe0aa94 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -57,7 +57,7 @@ static int via_vt8623_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -65,7 +65,7 @@ static int via_vt8623_int15_handler(struct eregs *regs) regs->eax=0x860f; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); break; } @@ -122,11 +122,11 @@ static void vga_init(device_t dev) // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); // this is how it looks: vga_enable_console(); - + #ifdef MEASURE_VGA_INIT_TIME clocks2 = rdmsr(0x10); instructions = rdmsr(0xc2); - + printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo); printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo); printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo); diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index c3097cf2cb..172a8de148 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -30,8 +30,8 @@ CB_STATUS VerifyChc(void); /*=================================================================== Function : DRAMRegInitValue() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -68,7 +68,7 @@ static const u8 DramRegTbl[][3] = { // {0x79, 0x00, 0x8F }, {0x85, 0x00, 0x00}, // {0x90, 0x87, 0x78 }, - // {0x91, 0x00, 0x46 }, + // {0x91, 0x00, 0x46 }, {0x40, 0x00, 0x00}, {0, 0, 0} @@ -155,8 +155,8 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : DRAMInitializeProc() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -176,7 +176,7 @@ static BOOLEAN ChkForExistLowBank(void) Address = (u32 *) 4; *Address = EXIST_TEST_PATTERN; - // _asm {WBINVD} + // _asm {WBINVD} WaitMicroSec(100); Address = (u32 *) 8; data32 = *Address; @@ -223,7 +223,7 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */ if (idx < 4) /* CHA init */ InitDDR2CHA(DramAttr); // temp wjb 2007/1 only for compiling - // in the function InitDDR2,the parameter is no need + // in the function InitDDR2,the parameter is no need Status = ChkForExistLowBank(); if (Status == TRUE) { PRINT_DEBUG_MEM(" S\r"); @@ -247,8 +247,8 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : DRAMSetVRNUM() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard PhyRank: Physical Rank number @@ -285,14 +285,14 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, /*=================================================================== Function : SetEndingAddr() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard VirRank: Virtual Rank number - Value: (value) add or subtract value to this and after banks + Value: (value) add or subtract value to this and after banks Output : Void -Purpose : Set ending address of virtual rank specified by VirRank +Purpose : Set ending address of virtual rank specified by VirRank ===================================================================*/ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address @@ -312,8 +312,8 @@ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address /*=================================================================== Function : InitDDR2() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -522,13 +522,13 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : InitDDR2_CHB() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Initialize DDR2 of CHB by standard sequence -Reference : +Reference : ===================================================================*/ /*// DLL: Enable Reset static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) @@ -569,7 +569,7 @@ void InitDDR2CHB( Data = 0x80; pci_write_config8(MEMCTRL, 0x54, Data); - + // step3. //disable bank paging and multi page Data=pci_read_config8(MEMCTRL, 0x69); @@ -579,18 +579,18 @@ void InitDDR2CHB( Data=pci_read_config8(MEMCTRL, 0xd3); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 4. Initialize CHB begin Data=pci_read_config8(MEMCTRL, 0xd3); Data |= 0x40; pci_write_config8(MEMCTRL, 0xd3, Data); - + //Step 5. NOP command enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd7, Data); - + //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; @@ -604,7 +604,7 @@ void InitDDR2CHB( // Loop 200us for (Idx = 0; Idx < 0x10; Idx++) WaitMicroSec(10); - + // Step 8. // all banks precharge command enable Data=pci_read_config8(MEMCTRL, 0xd7); @@ -618,7 +618,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step10. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -661,7 +661,7 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //step 14. MSR DLL Reset + //step 14. MSR DLL Reset AccessAddr = CHB_MRS_DLL_150[1] >> 3; Data =(u8) (AccessAddr & 0xff); pci_write_config8(MEMCTRL, 0xd9, Data); @@ -691,7 +691,7 @@ void InitDDR2CHB( Data |= 0x10; pci_write_config8(MEMCTRL, 0xd7, Data); - + // step17. issue precharge all cycle Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; @@ -718,7 +718,7 @@ void InitDDR2CHB( WaitMicroSec(200); } - + //step22. MSR enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -730,7 +730,7 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - + //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- //Burst Length : really offset Rx6c[1] @@ -773,7 +773,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 25. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -784,7 +784,7 @@ void InitDDR2CHB( Data &= 0xC7; Data |= 0x08; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 26. OCD default AccessAddr = (CHB_OCD_Default_150ohm) >> 3; @@ -805,7 +805,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0xd3, Data); Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 25. EMRS enable Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -859,12 +859,12 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //step 31. exit the initialization mode + //step 31. exit the initialization mode Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0xBF; pci_write_config8(MEMCTRL, 0xd3, Data); - + //step 32. Enable bank paging and multi page Data=pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; @@ -874,13 +874,13 @@ void InitDDR2CHB( /*=================================================================== Function : InitDDR2CHC() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Initialize DDR2 of CHC by standard sequence -Reference : +Reference : ===================================================================*/ // DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM @@ -1102,7 +1102,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) Status = VerifyChc(); if (Status != CB_SUCCESS) PRINT_DEBUG_MEM("Error!!!!CHC init error!\r"); - //step 31. exit the initialization mode + //step 31. exit the initialization mode Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0x9F; pci_write_config8(MEMCTRL, 0xdb, Data); diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c index 785d775baf..c4971d1b17 100644 --- a/src/northbridge/via/vx800/dqs_search.c +++ b/src/northbridge/via/vx800/dqs_search.c @@ -22,8 +22,8 @@ void SetDQSOutputCHB(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMDQSOutputSearchCHA() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void @@ -40,12 +40,12 @@ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : SetDQSOutputCHA() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void -Purpose : according the frequence set CHA DQS output +Purpose : according the frequence set CHA DQS output ===================================================================*/ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) { @@ -80,8 +80,8 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMDQSInputSearch() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index 342a6e0454..7688ab34a8 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -30,11 +30,11 @@ void WaitMicroSec(UINTN MicroSeconds) /*=================================================================== Function : via_write_phys() -Precondition : +Precondition : Input : addr value Output : void -Purpose : +Purpose : Reference : None ===================================================================*/ @@ -47,10 +47,10 @@ void via_write_phys(volatile u32 addr, volatile u32 value) /*=================================================================== Function : via_read_phys() -Precondition : +Precondition : Input : addr -Output : u32 -Purpose : +Output : u32 +Purpose : Reference : None ===================================================================*/ @@ -63,10 +63,10 @@ u32 via_read_phys(volatile u32 addr) /*=================================================================== Function : DimmRead() -Precondition : +Precondition : Input : x -Output : u32 -Purpose : +Output : u32 +Purpose : Reference : None ===================================================================*/ @@ -80,13 +80,13 @@ u32 DimmRead(volatile u32 x) /*=================================================================== Function : DramBaseTest() -Precondition : this function used to verify memory -Input : +Precondition : this function used to verify memory +Input : BaseAdd, length, mode Output : u32 -Purpose :write into and read out to verify if dram is correct +Purpose :write into and read out to verify if dram is correct Reference : None ===================================================================*/ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, @@ -170,8 +170,8 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, /*=================================================================== Function : DumpRegisters() -Precondition : -Input : +Precondition : +Input : pPCIPPI, DevNum, FuncNum @@ -209,8 +209,8 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) /*=================================================================== Function : dumpnorth() -Precondition : -Input : +Precondition : +Input : pPCIPPI, Func Output : Void diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index c6a7edda05..bdba494d85 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -58,7 +58,7 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr) /* ODT Control for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB which include driving enable/range and strong/weak selection - + Processing: According to DRAM frequency to ODT control bits. Because function enable bit must be the last one to be set. So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be @@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { }; #define ODT_Table_Width_DDR2 4 -// RxD6 RxD3 +// RxD6 RxD3 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 }; void DrivingODT(DRAM_SYS_ATTR * DramAttr) diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c index a93c9a03c4..5e8e214d1f 100644 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c @@ -20,7 +20,7 @@ #include "northbridge/via/vx800/driving_clk_phase_data.h" -// DQS Driving +// DQS Driving //Reg0xE0, 0xE1 // According to #Bank to set DRAM DQS Driving // #Bank 1 2 3 4 5 6 7 8 @@ -161,7 +161,7 @@ static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } }; -/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = +/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { // (And NOT) DDR800 DDR667 DDR533 DDR400 //Reg Mask Value Value Value Value diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 8db60237b7..63755c3181 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -362,7 +362,7 @@ g) Rx73h = 32h /* decide if this is a s3 wakeup or a normal boot */ boot_mode = acpi_is_wakeup_early_via_vx800(); /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, + When this boot is not a S3 resume, and PCI registers had been written, then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ if ((boot_mode != 3) && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { @@ -371,7 +371,7 @@ g) Rx73h = 32h /*x86 cold boot I/O cmd */ enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this + //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this if (bist == 0) { // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); @@ -441,7 +441,7 @@ g) Rx73h = 32h /* For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. + so before this happen, I need to backup the content of mem to top-mem. I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c */ #if PAYLOAD_IS_SEABIOS==1 // @@ -449,7 +449,7 @@ g) Rx73h = 32h /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, + /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. @@ -462,7 +462,7 @@ g) Rx73h = 32h u32 memtop4 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; - /* __asm__ volatile ( + /* __asm__ volatile ( "movl $0x204, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -478,7 +478,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop2) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x206, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -494,7 +494,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop1) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x208, %ecx\n\t" "xorl %edx, %edx\n\t" "movl $0,%eax\n\t" @@ -512,21 +512,21 @@ g) Rx73h = 32h */ // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( + /*__asm__ volatile ( "movl $0, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0xa0000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) + "rep movsd\n\t" + ::"g"(memtop3) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0xe0000, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0x20000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) + "rep movsd\n\t" + ::"g"(memtop4) );*/ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - @@ -537,22 +537,22 @@ g) Rx73h = 32h (unsigned char *) 0xe0000, 0x20000); /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" +/* __asm__ volatile ( + "wbinvd\n\t" "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "movl $0x204, %ecx\n\t" "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" + "movl $0x205, %ecx\n\t" + "wrmsr\n\t" "movl $0x206, %ecx\n\t" "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" + "movl $0x207, %ecx\n\t" + "wrmsr\n\t" + "movl $0x208, %ecx\n\t" + "wrmsr\n\t" + "movl $0x209, %ecx\n\t" + "wrmsr\n\t" );*/ } #endif diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c index 97cc21820a..9ec31b58da 100644 --- a/src/northbridge/via/vx800/final_setting.c +++ b/src/northbridge/via/vx800/final_setting.c @@ -64,8 +64,8 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMRegFinalValue() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information in MotherBoard Output : Void diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 47a99c3cc1..03daeec342 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -230,7 +230,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) DramAttr->DramFreq = DIMMFREQ_200; DramAttr->DramCyc = 1000; } - //if set the frequence mannul + //if set the frequence mannul PRINT_DEBUG_MEM("Dram Frequency:"); PRINT_DEBUG_MEM_HEX16(DramAttr->DramFreq); PRINT_DEBUG_MEM(" \r"); diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 4dfe843bae..37e559c026 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -118,7 +118,7 @@ static u32 find_pci_tolm(struct bus *bus) static void pci_domain_set_resources(device_t dev) { - /* + /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index 6c88c68953..3eada63329 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -32,8 +32,8 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMBankInterleave() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : STEP 13 Set Bank Interleave VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank 11:8 Bank @@ -85,11 +85,11 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingMATypeM() -Precondition : +Precondition : Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void - Purpose : STEP 14 1 DRAM Sizing 2 Fill MA type 3 Prank to vrankMapping + Purpose : STEP 14 1 DRAM Sizing 2 Fill MA type 3 Prank to vrankMapping ===================================================================*/ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) { @@ -103,8 +103,8 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMClearEndingAddress() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : clear Ending and Start adress from 0x40-4f to zero @@ -120,8 +120,8 @@ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingEachRank() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit @@ -189,8 +189,8 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetRankMAType() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit @@ -258,11 +258,11 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetEndingAddress() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void -Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size +Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size ===================================================================*/ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) { @@ -311,8 +311,8 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMPRToVRMapping() -Precondition : -Input : +Precondition : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard Output : Void Purpose : set the Vrank-prank map with the same order diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index a1d8e74812..7668b22e0b 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -72,7 +72,7 @@ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr) /* Set DRAM Timing: CAS Latency for DDR1 -D0F3RX62 bit[0:2] for CAS Latency; +D0F3RX62 bit[0:2] for CAS Latency; */ void SetCL(DRAM_SYS_ATTR * DramAttr) { diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 72420981ff..6fe8194922 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -139,7 +139,7 @@ void SetUMARam(void) // vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. + //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); @@ -256,7 +256,7 @@ void SetUMARam(void) } outb(ByteVal, 0x03d5); - // Set frame buffer size + // Set frame buffer size outb(0x39, 0x03c4); outb(1 << SLD0F3Val, 0x03c5); @@ -295,7 +295,7 @@ void SetUMARam(void) SLBase = (RamSize << 26) - (UmaSize << 20); outb(0x6D, 0x03c4); - //SL Base[28:21] + //SL Base[28:21] outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5); outb(0x6e, 0x03c4); diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 3897e010b5..7bdc3418f1 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -62,19 +62,19 @@ static int via_vx800_int15_handler(struct eregs *regs) case 0x5f18: { /* - * BL Bit[7:4] - * Memory Data Rate - * 0000: 66MHz - * 0001: 100MHz - * 0010: 133MHz - * 0011: 200MHz ( DDR200 ) - * 0100: 266MHz ( DDR266 ) - * 0101: 333MHz ( DDR333 ) - * 0110: 400MHz ( DDR400 ) - * 0111: 533MHz ( DDR I/II 533 + * BL Bit[7:4] + * Memory Data Rate + * 0000: 66MHz + * 0001: 100MHz + * 0010: 133MHz + * 0011: 200MHz ( DDR200 ) + * 0100: 266MHz ( DDR266 ) + * 0101: 333MHz ( DDR333 ) + * 0110: 400MHz ( DDR400 ) + * 0111: 533MHz ( DDR I/II 533 * 1000: 667MHz ( DDR I/II 667) - * Bit[3:0] - * N: Frame Buffer Size 2^N MB + * Bit[3:0] + * N: Frame Buffer Size 2^N MB */ u8 i; device_t dev; @@ -109,7 +109,7 @@ static int via_vx800_int15_handler(struct eregs *regs) case 0x5f02: regs->eax=0x5f; regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default res=0; break; @@ -118,7 +118,7 @@ static int via_vx800_int15_handler(struct eregs *regs) res = 0; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); regs->eax = 0; break; diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c index 6462a2d295..8bac43ff12 100644 --- a/src/northbridge/via/vx800/vx800_early_serial.c +++ b/src/northbridge/via/vx800/vx800_early_serial.c @@ -70,7 +70,7 @@ static void enable_vx800_serial(void) // turn on pnp vx800_writepnpaddr(0x87); vx800_writepnpaddr(0x87); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address vx800_writepnpaddr(0x7); vx800_writepnpdata(0x2); diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c index 7ba9b41acb..e40d54d721 100644 --- a/src/northbridge/via/vx800/vx800_early_smbus.c +++ b/src/northbridge/via/vx800/vx800_early_smbus.c @@ -171,10 +171,10 @@ static void enable_smbus(void) } /** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for * known-good data from a slot/address. Exits on either good data or a timeout. * * TODO: This should probably go into some global file, but one would need to diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c index 874f32fbbd..ce2d822946 100644 --- a/src/northbridge/via/vx800/vx800_lpc.c +++ b/src/northbridge/via/vx800/vx800_lpc.c @@ -42,9 +42,9 @@ static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only I static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA -static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 +static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 -static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA +static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA static unsigned char *pin_to_irq(const unsigned char *pin) { @@ -218,7 +218,7 @@ static void S3_ps2_kb_ms_wakeup(struct device *dev) pci_write_config8(dev, 0x51, enables); outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger - outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME } @@ -354,17 +354,17 @@ static void southbridge_init(struct device *dev) fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) - #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. + #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 3 CLKRUN# is always asserted PMIORx26<3> =0 - 4 Disable PCISTP# When CLKRUN# is asserted - 1: PCISTP# will not assert When CLKRUN# is asserted + 4 Disable PCISTP# When CLKRUN# is asserted + 1: PCISTP# will not assert When CLKRUN# is asserted PMIORx26<4> =1 - 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. - VRDSLP will be active in either this bit set in C3 or LVL4 register read + 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state. + VRDSLP will be active in either this bit set in C3 or LVL4 register read PMIORx26<0> =0 - 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 + 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15 */ outb(0x17, VX800_ACPI_IO_BASE + 0x26); diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 43190fd071..358c221856 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -1,6 +1,6 @@ obj-y += mc146818rtc.o obj-y += isa-dma.o -obj-y += i8259.o +obj-y += i8259.o obj-$(CONFIG_UDELAY_IO) += udelay_io.o obj-y += keyboard.o diff --git a/src/pc80/i8259.c b/src/pc80/i8259.c index 330b7c6428..66988753cf 100644 --- a/src/pc80/i8259.c +++ b/src/pc80/i8259.c @@ -75,7 +75,7 @@ void setup_i8259(void) outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2); outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2); - /* Now the interrupt controller expects us to write to ICW3. + /* Now the interrupt controller expects us to write to ICW3. * * The normal scenario is to set up cascading on IRQ2 on the master * i8259 and assign the slave ID 2 to the slave i8259. @@ -89,9 +89,9 @@ void setup_i8259(void) * operating as part of an x86 architecture based chipset */ outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2); - outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); + outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); - /* Now clear the interrupts through OCW1. + /* Now clear the interrupts through OCW1. * First we mask off all interrupts on the slave interrupt controller * then we mask off all interrupts but interrupt 2 on the master * controller. This way the cascading stays alife. diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c index 4bee1cdffe..078bde273c 100644 --- a/src/pc80/mc146818rtc.c +++ b/src/pc80/mc146818rtc.c @@ -156,7 +156,7 @@ void rtc_init(int invalid) if (invalid || cmos_invalid || checksum_invalid) { printk(BIOS_WARNING, "RTC:%s%s%s zeroing cmos\n", - invalid?" Clear requested":"", + invalid?" Clear requested":"", cmos_invalid?" Power Problem":"", checksum_invalid?" Checksum invalid":""); #if 0 @@ -166,7 +166,7 @@ void rtc_init(int invalid) for(i = 10; i < 48; i++) { cmos_write(0, i); } - + if (cmos_invalid) { /* Now setup a default date of Sat 1 January 2000 */ cmos_write(0, 0x00); /* seconds */ @@ -218,7 +218,7 @@ static int get_cmos_value(unsigned long bit, unsigned long length, void *vret) unsigned long i; unsigned char uchar; - /* The table is checked when it is built to ensure all + /* The table is checked when it is built to ensure all values are valid. */ ret = vret; byte=bit/8; /* find the byte where the data starts */ @@ -248,7 +248,7 @@ int get_option(void *dest, const char *name) /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - + /* find the requested entry record */ ct=&option_table; ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); @@ -263,7 +263,7 @@ int get_option(void *dest, const char *name) printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); return(-2); } - + if(get_cmos_value(ce->bit, ce->length, dest)) return(-3); if(!rtc_checksum_valid(LB_CKS_RANGE_START, diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c index 87fc3f0a61..fa1f388804 100644 --- a/src/pc80/mc146818rtc_early.c +++ b/src/pc80/mc146818rtc_early.c @@ -88,7 +88,7 @@ static inline int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - + /* Are we in normal mode? */ if (byte & 1) { byte &= 0x0f; /* yes, clear the boot count */ diff --git a/src/pc80/serial.c b/src/pc80/serial.c index 837d112338..b4d0542824 100644 --- a/src/pc80/serial.c +++ b/src/pc80/serial.c @@ -53,14 +53,14 @@ static int uart_can_tx_byte(void) static void uart_wait_to_tx_byte(void) { - while(!uart_can_tx_byte()) + while(!uart_can_tx_byte()) ; } static void uart_wait_until_sent(void) { while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; + ; } static void uart_tx_byte(unsigned char data) @@ -109,6 +109,6 @@ void uart_init(void) uart8250_init(CONFIG_TTYS0_BASE, ttys0_div, UART_LCS); #else uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, UART_LCS); -#endif +#endif } #endif diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index 1390065c09..2707ca6b43 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -13,8 +13,8 @@ void amd8111_enable(device_t dev) /* See if we are on the bus behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) + if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { unsigned devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); @@ -33,7 +33,7 @@ void amd8111_enable(device_t dev) return; } if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); @@ -66,7 +66,7 @@ void amd8111_enable(device_t dev) struct chip_operations southbridge_amd_amd8111_ops = { CHIP_NAME("AMD-8111 Southbridge") - /* This only called when this device is listed in the + /* This only called when this device is listed in the * static device tree. */ .enable_dev = amd8111_enable, diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/amd8111_ac97.c index 697915e002..f49c9bfd5f 100644 --- a/src/southbridge/amd/amd8111/amd8111_ac97.c +++ b/src/southbridge/amd/amd8111/amd8111_ac97.c @@ -10,7 +10,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x2c, + pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 32e3808a98..2ad54b78f6 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -28,7 +28,7 @@ static int lsmbus_recv_byte(device_t dev) device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - + return do_smbus_recv_byte(res->base, device); } @@ -51,7 +51,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - + return do_smbus_read_byte(res->base, device, address); } @@ -62,7 +62,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, 0x58); - + return do_smbus_write_byte(res->base, device, address, val); } @@ -109,7 +109,7 @@ static void acpi_init(struct device *dev) */ byte = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); - + /* power on after power fail */ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); @@ -126,7 +126,7 @@ static void acpi_init(struct device *dev) */ byte = pci_read_config8(dev, 0x4a); pci_write_config8(dev, 0x4a, byte | (1<<6)); - + /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); @@ -177,12 +177,12 @@ static void acpi_enable_resources(device_t dev) /* Set the class code */ pci_write_config32(dev, 0x60, 0x06800000); - + } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x7c, + pci_write_config32(dev, 0x7c, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -204,7 +204,7 @@ static struct device_operations acpi_ops = { .init = acpi_init, .scan_bus = scan_static_bus, /* We don't need amd8111_enable, chip ops takes care of it. - * It could be useful if these devices were not + * It could be useful if these devices were not * enabled by default. */ // .enable = amd8111_enable, diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c index 3b6f5a0a65..3299875187 100644 --- a/src/southbridge/amd/amd8111/amd8111_ide.c +++ b/src/southbridge/amd/amd8111/amd8111_ide.c @@ -42,7 +42,7 @@ static void ide_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x70, + pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index 85e217bb65..8fe4982721 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -19,11 +19,11 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - + pci_write_config32(dev,0xa0, 0xfed00001); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); - + } static void lpc_init(struct device *dev) @@ -40,7 +40,7 @@ static void lpc_init(struct device *dev) /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + pci_write_config8(dev, 0x46, byte | (1<<0)); /* Enable 5Mib Rom window */ byte = pci_read_config8(dev, 0x43); @@ -65,11 +65,11 @@ static void lpc_init(struct device *dev) pci_write_config8(dev, 0x40, byte); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte |= (1 << 7); /* set NMI */ pci_write_config8(dev, 0x40, byte); } - + /* Initialize the real time clock */ rtc_init(0); @@ -114,7 +114,7 @@ static void amd8111_lpc_enable_resources(device_t dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x70, + pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index 8818b51b40..4ab7212eda 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -25,20 +25,20 @@ typedef enum { ASF_INIT_DONE_ALIAS = (1 << 29), /* VAL2 */ JUMBO = (1 << 21), - VSIZE = (1 << 20), + VSIZE = (1 << 20), VLONLY = (1 << 19), - VL_TAG_DEL = (1 << 18), + VL_TAG_DEL = (1 << 18), /* VAL1 */ - EN_PMGR = (1 << 14), + EN_PMGR = (1 << 14), INTLEVEL = (1 << 13), - FORCE_FULL_DUPLEX = (1 << 12), - FORCE_LINK_STATUS = (1 << 11), - APEP = (1 << 10), - MPPLBA = (1 << 9), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), /* VAL0 */ - RESET_PHY_PULSE = (1 << 2), - RESET_PHY = (1 << 1), - PHY_RST_POL = (1 << 0), + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), }CMD3_BITS; static void nic_init(struct device *dev) @@ -72,7 +72,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; - + static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c index 9b26bcb90d..c96e898aea 100644 --- a/src/southbridge/amd/amd8111/amd8111_reset.c +++ b/src/southbridge/amd/amd8111/amd8111_reset.c @@ -67,7 +67,7 @@ void hard_reset(void) */ bus = node_link_to_bus(node, link); dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), bus); /* Reset */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/amd8111_smbus.c index 2554fd0c5e..0a0c58dce3 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_smbus.c @@ -13,7 +13,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x44, + pci_write_config32(dev, 0x44, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index b5799666e9..fe9b3bff8c 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -27,7 +27,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) break; } if(loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBGSTATUS), + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); } } while(--loops); @@ -41,7 +41,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) do { unsigned short val; smbus_delay(); - + val = inw(smbus_io_base + SMBGSTATUS); if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) { break; @@ -58,7 +58,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); @@ -103,7 +103,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); @@ -146,7 +146,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/amd8111_usb.c index f1c331dbaf..13dccf435b 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb.c +++ b/src/southbridge/amd/amd8111/amd8111_usb.c @@ -12,7 +12,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x70, + pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c index 3aa5211dd0..89115c3bbe 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb2.c +++ b/src/southbridge/amd/amd8111/amd8111_usb2.c @@ -11,7 +11,7 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x70, + pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -23,7 +23,7 @@ static struct pci_operations lops_pci = { static void amd8111_usb2_enable(device_t dev) { - // Due to buggy USB2 we force it to disable. + // Due to buggy USB2 we force it to disable. dev->enabled = 0; amd8111_enable(dev); printk(BIOS_DEBUG, "USB2 disabled.\n"); diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h index 6c97ef2232..601038c441 100644 --- a/src/southbridge/amd/amd8111/chip.h +++ b/src/southbridge/amd/amd8111/chip.h @@ -1,7 +1,7 @@ #ifndef AMD8111_CHIP_H #define AMD8111_CHIP_H -struct southbridge_amd_amd8111_config +struct southbridge_amd_amd8111_config { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; diff --git a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c index bcb89fa22a..e90f497d95 100644 --- a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131-disable/amd8131_bridge.c @@ -112,5 +112,5 @@ static const struct pci_driver ioapic_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7451, - + }; diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index 04930517e6..ae2c4cffcb 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -121,7 +121,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) } } /* Errata #56 additional limits when the bus runs at 133Mhz */ - if (info->errata_56 && + if (info->errata_56 && (PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)) { unsigned limit_read; @@ -131,7 +131,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) if (sib_funcs == 0) { /* 2k reads */ limit_read = 2; - } + } else if (sib_funcs <= 1) { /* 1k reads */ limit_read = 1; @@ -226,8 +226,8 @@ static unsigned int amd8131_scan_bus(struct bus *bus, * we are running at 133Mhz and have a 4 function device. * see errata #56 */ - if (!bus->children || - (info.errata_56 && + if (!bus->children || + (info.errata_56 && (info.max_func >= 3) && (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))) { @@ -242,7 +242,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus, pcix_misc = pci_read_config32(bus->dev, 0x40); pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - + return max; } @@ -284,7 +284,7 @@ static void amd8131_pcix_init(device_t dev) byte = pci_read_config8(dev, 0x04); byte |= 0x10; pci_write_config8(dev, 0x04, byte); - + /* Set drive strength */ word = pci_read_config16(dev, 0xe0); word = 0x0404; @@ -292,7 +292,7 @@ static void amd8131_pcix_init(device_t dev) word = pci_read_config16(dev, 0xe4); word = 0x0404; pci_write_config16(dev, 0xe4, word); - + /* Set impedance */ word = pci_read_config16(dev, 0xe8); word = 0x0404; @@ -303,7 +303,7 @@ static void amd8131_pcix_init(device_t dev) word = pci_read_config16(dev, 0x4c); word |= 1; pci_write_config16(dev, 0x4c, word); - + /* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); pci_write_config16(dev, 0xaa, word); @@ -315,12 +315,12 @@ static void amd8131_pcix_init(device_t dev) dword = pci_read_config32(dev, 0x04); dword |= (1<<8); pci_write_config32(dev, 0x04, dword); - + /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); dword |= (3<<16); pci_write_config32(dev, 0x3c, dword); - + /* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); @@ -329,7 +329,7 @@ static void amd8131_pcix_init(device_t dev) dword |= (1<<0); pci_write_config32(dev, 0x44, dword); } - + /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); if(dword) { /* do device A only */ @@ -349,7 +349,7 @@ static void bridge_read_resources(struct device *dev) { struct resource *res; pci_bus_read_resources(dev); - res = find_resource(dev, PCI_MEMORY_BASE); + res = find_resource(dev, PCI_MEMORY_BASE); if (res) { res->limit = 0xffffffffffULL; } @@ -428,5 +428,5 @@ static const struct pci_driver ioapic_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7451, - + }; diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c index 2c18c5ebcb..e8283baa50 100644 --- a/src/southbridge/amd/amd8132/amd8132_bridge.c +++ b/src/southbridge/amd/amd8132/amd8132_bridge.c @@ -114,7 +114,7 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) max_read = (status & PCI_X_STATUS_MAX_READ) >> 21; max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23; - if (info->rev == 0x01) { // only a1 need it + if (info->rev == 0x01) { // only a1 need it /* Errata #53 Limit the number of split transactions to avoid starvation */ if (sibs >= 2) { /* At most 2 outstanding split transactions when we have @@ -186,7 +186,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus, amd8132_walk_children(bus, amd8132_count_dev, &info); #if 0 - /* Disable the bus if there are no devices on it + /* Disable the bus if there are no devices on it */ if (!bus->children) { @@ -201,7 +201,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus, pcix_misc = pci_read_config32(bus->dev, 0x40); pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - + return max; } #endif @@ -229,7 +229,7 @@ static void amd8132_pcix_init(device_t dev) uint32_t dword; uint8_t byte; unsigned chip_rev; - + /* Find the revision of the 8132 */ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); @@ -259,7 +259,7 @@ static void amd8132_pcix_init(device_t dev) dword = pci_read_config32(dev, 0x04); dword |= (1<<8); pci_write_config32(dev, 0x04, dword); - + /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); dword |= (3<<16); @@ -267,7 +267,7 @@ static void amd8132_pcix_init(device_t dev) dword = pci_read_config32(dev, 0x40); // dword &= ~(1<<31); /* WriteChainEnable */ - dword |= (1<<31); + dword |= (1<<31); dword |= (1<<7);// must set to 1 dword |= (3<<21); //PCIErrorSerrDisable pci_write_config32(dev, 0x40, dword); @@ -335,7 +335,7 @@ static void bridge_read_resources(struct device *dev) { struct resource *res; pci_bus_read_resources(dev); - res = find_resource(dev, PCI_MEMORY_BASE); + res = find_resource(dev, PCI_MEMORY_BASE); if (res) { res->limit = 0xffffffffffULL; } @@ -450,5 +450,5 @@ static const struct pci_driver ioapic_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7459, - + }; diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c index 93c7992810..5d673f6ae8 100644 --- a/src/southbridge/amd/amd8151/amd8151_agp3.c +++ b/src/southbridge/amd/amd8151/amd8151_agp3.c @@ -38,7 +38,7 @@ static const struct pci_driver agp3bridge_driver __pci_driver = { static void agp3dev_enable(device_t dev) { uint32_t value; - + /* AGP enable */ value = pci_read_config32(dev, 0xa8); value |= (3<<8)|2; //AGP 8x @@ -71,5 +71,5 @@ static struct device_operations agp3dev_ops = { static const struct pci_driver agp3dev_driver __pci_driver = { .ops = &agp3dev_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7454, //AGP Device + .device = 0x7454, //AGP Device }; diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 6f203558e3..50b62df0c3 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -21,7 +21,7 @@ static void nvram_on(struct device *dev) /* Set positive decode on ROM */ /* Also, there is no apparent reason to turn off the devoce on the */ /* IDE devices */ - + reg = pci_read_config8(dev, 0x5b); reg |= 1 << 5; /* ROM Decode */ reg |= 1 << 3; /* Primary IDE decode */ @@ -43,7 +43,7 @@ static void nvram_on(struct device *dev) #endif } - + static void southbridge_init(struct device *dev) { printk(BIOS_SPEW, "cs5535: %s\n", __func__); diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c index fbb3647578..91dc852012 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_setup.c +++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c @@ -8,13 +8,13 @@ * */ -#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */ +#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */ #define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */ /** * @brief Setup PCI IDSEL for CS5535 * - * + * */ static void cs5535_setup_extmsr(void) diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c index 6ff46338f6..ec801f02a8 100644 --- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c +++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c @@ -18,7 +18,7 @@ static int cs5535_enable_smbus(void) /* Setup SMBus host controller address to 0xEF */ val = inb(SMBUS_IO_BASE + SMB_ADD); val |= (0xEF | SMB_ADD_SAEN); - outb(val, SMBUS_IO_BASE + SMB_ADD); + outb(val, SMBUS_IO_BASE + SMB_ADD); } static int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/cs5535_smbus.h index 9cf55ba29c..799e226f5e 100644 --- a/src/southbridge/amd/cs5535/cs5535_smbus.h +++ b/src/southbridge/amd/cs5535/cs5535_smbus.h @@ -105,7 +105,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device unsigned char val; unsigned long loops; loops = SMBUS_TIMEOUT; - + /* send the slave address */ outb(device, smbus_io_base + SMB_SDA); @@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device break; } } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; + return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } static int smbus_send_command(unsigned smbus_io_base, unsigned char command) @@ -149,7 +149,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command) break; } } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; + return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig index b6884b7fa9..e7caf5e27a 100644 --- a/src/southbridge/amd/cs5536/Kconfig +++ b/src/southbridge/amd/cs5536/Kconfig @@ -26,5 +26,5 @@ config UDELAY_TSC default y depends on SOUTHBRIDGE_AMD_CS5536 - + diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 43f3b1290e..11679278f8 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -247,7 +247,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb) isa_dma_init(); } - + /** * Depending on settings in the config struct, enable COM1 or COM2 or both. @@ -263,8 +263,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) u16 addr = 0; u32 gpio_addr; device_t dev; - - dev = dev_find_device(PCI_VENDOR_ID_AMD, + + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); gpio_addr &= ~1; /* Clear I/O bit */ @@ -431,7 +431,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) msr_t msr; device_t dev; - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); if (dev) { @@ -452,7 +452,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) write32(bar + HCCPARAMS, 0x00005012); } - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -480,7 +480,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) * - set PADEN (former OTGPADEN) bit in uoc register * - set APU bit in uoc register */ if (sb->enable_USBP4_device) { - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -499,13 +499,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) } /* Disable virtual PCI UDC and OTG headers */ - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { pci_write_config32(dev, 0x7C, 0xDEADBEEF); } - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { pci_write_config32(dev, 0x7C, 0xDEADBEEF); @@ -513,14 +513,14 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) } /**************************************************************************** - * - * ChipsetInit + * + * ChipsetInit * * Called from northbridge init (Pre-VSA). * * NOTE! This function is NOT called if the CS5536 is combined with * an AMD Geode GX2. It's ONLY used on Geode LX based systems. - * + * ****************************************************************************/ void chipsetinit(void) { @@ -530,7 +530,7 @@ void chipsetinit(void) struct southbridge_amd_cs5536_config *sb; struct msrinit *csi; - dev = dev_find_device(PCI_VENDOR_ID_AMD, + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); if (!dev) { diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 073bb3ea59..797ac92764 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -465,7 +465,7 @@ #define FLASH_IO_256B 0x0000FF00 #if !defined(ASSEMBLY) && !defined(__ROMCC__) -#if defined(__PRE_RAM__) +#if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); #else diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h index 3613b3d37b..dea08a437c 100644 --- a/src/southbridge/amd/cs5536/cs5536_smbus2.h +++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h @@ -309,7 +309,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, (unsigned char *)&data, 1); } -static inline int do_smbus_write_word(unsigned smbus_io_base, +static inline int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, unsigned char address, unsigned short data) { return _dowrite(smbus_io_base, device, address, (unsigned char *)&data, diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c b/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c index f83e54b682..ece7e794eb 100644 --- a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c +++ b/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c @@ -10,8 +10,8 @@ #include <device/pci_ops.h> static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, +{ + pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 3ac28e59ca..3f92be7dec 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -16,7 +16,7 @@ void bcm5785_enable(device_t dev) /* See if we are on the behind the pcix bridge */ bus_dev = dev->bus->dev; - if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && + if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && (bus_dev->device == 0x0036 )) // device under PCI-X Bridge { unsigned devfn; @@ -34,7 +34,7 @@ void bcm5785_enable(device_t dev) else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; - if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { + if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { if(dev->device == 0x0036) //PCI-X Bridge { devfn += (1<<3); } else if(dev->device == 0x0223) // USB diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index fd2f3ed114..d448bf67c3 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -85,7 +85,7 @@ static unsigned get_sbdn(unsigned bus) static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - //ACPI Decode Enable + //ACPI Decode Enable outb(0x0e, 0xcd6); outb((1<<3), 0xcd7); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c index 2638e97d5c..a55ddd82e8 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c @@ -15,11 +15,11 @@ static void enable_smbus(void) if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); } - + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config8(dev, 0xd2, 0x03); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index e76dd3a45a..29c08ab74e 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -52,25 +52,25 @@ static void bcm5785_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -/** +/** * @brief Enable resources for children devices - * + * * @param dev the device whos children's resources are to be enabled - * + * * This function is call by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. - * + * * Indirect mutual recursion: * enable_childrens_resources() -> enable_resources() * enable_resources() -> device_operation::enable_resources() * device_operation::enable_resources() -> enable_children_resources() - */ + */ static void bcm5785_lpc_enable_childrens_resources(device_t dev) -{ - unsigned link; +{ + unsigned link; uint32_t reg; int i; - + reg = pci_read_config8(dev, 0x44); for (link = 0; link < dev->links; link++) { @@ -93,10 +93,10 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) case 0x3f8: // COM1 reg |= (1<<6); break; case 0x2f8: // COM2 - reg |= (1<<7); break; + reg |= (1<<7); break; case 0x378: // Parallal 1 reg |= (1<<0); break; - case 0x3f0: // FD0 + case 0x3f0: // FD0 reg |= (1<<26); break; case 0x220: // Aduio 0 reg |= (1<<14); break; @@ -108,7 +108,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } } pci_write_config32(dev, 0x44, reg); - + } diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index ec92ecf7e9..58d5ff5bb7 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -44,7 +44,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "init PHY...\n"); for(i=0; i<4; i++) { - mmio = res->base + 0x100 * i; + mmio = res->base + 0x100 * i; byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c index a13e9f3fd0..4f518b6a54 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c @@ -30,7 +30,7 @@ static void sb_init(device_t dev) byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW @@ -47,16 +47,16 @@ static void bcm5785_sb_read_resources(device_t dev) struct resource *res; /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - /* Get Resource for SMBUS */ - pci_get_resource(dev, 0x90); + pci_dev_read_resources(dev); + /* Get Resource for SMBUS */ + pci_get_resource(dev, 0x90); - compact_resources(dev); + compact_resources(dev); /* Add an extra subtractive resource for both memory and I/O */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; @@ -75,7 +75,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } - + static int lsmbus_send_byte(device_t dev, uint8_t val) { unsigned device; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h b/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h index 5f2f7717a0..e71bb5cbee 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h @@ -19,7 +19,7 @@ #define SMBSLVDAT 0xc -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000*10) @@ -36,7 +36,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) do { unsigned char val; val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; + val &= 0x1f; if (val == 0) { // ready now return 0; } @@ -51,7 +51,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) loops = SMBUS_TIMEOUT; do { unsigned char val; - + val = inb(smbus_io_base + SMBHSTSTAT); val &= 0x1f; // mask off reserved bits if ( val & 0x1c) { @@ -68,7 +68,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { uint8_t byte; - + if (smbus_wait_until_ready(smbus_io_base) < 0) { return -2; // not ready } @@ -128,7 +128,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return -2; // not ready } - + /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c b/src/southbridge/broadcom/bcm5785/bcm5785_usb.c index c2e7366272..15295d8329 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_usb.c @@ -23,8 +23,8 @@ static void usb_init(struct device *dev) } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, +{ + pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h index 4aa2ce3217..3106f60c24 100644 --- a/src/southbridge/broadcom/bcm5785/chip.h +++ b/src/southbridge/broadcom/bcm5785/chip.h @@ -1,7 +1,7 @@ #ifndef BCM5785_CHIP_H #define BCM5785_CHIP_H -struct southbridge_broadcom_bcm5785_config +struct southbridge_broadcom_bcm5785_config { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h index ff74e615fd..4082769cce 100644 --- a/src/southbridge/intel/esb6300/chip.h +++ b/src/southbridge/intel/esb6300/chip.h @@ -1,4 +1,4 @@ -struct southbridge_intel_esb6300_config +struct southbridge_intel_esb6300_config { #define ESB6300_GPIO_USE_MASK 0x03 #define ESB6300_GPIO_USE_DEFAULT 0x00 diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c index 786daea23b..5d8f5e412d 100644 --- a/src/southbridge/intel/esb6300/esb6300.c +++ b/src/southbridge/intel/esb6300/esb6300.c @@ -25,7 +25,7 @@ void esb6300_enable(device_t dev) (lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | + if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) { return; } @@ -39,7 +39,7 @@ void esb6300_enable(device_t dev) if (reg != reg_old) { pci_write_config16(lpc_dev, 0xf2, reg); } - + } struct chip_operations southbridge_intel_esb6300_ops = { diff --git a/src/southbridge/intel/esb6300/esb6300_ac97.c b/src/southbridge/intel/esb6300/esb6300_ac97.c index 231f8129ad..7b7795f5df 100644 --- a/src/southbridge/intel/esb6300/esb6300_ac97.c +++ b/src/southbridge/intel/esb6300/esb6300_ac97.c @@ -8,7 +8,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c index ae7cfcd227..d804fde038 100644 --- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c +++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c @@ -12,7 +12,7 @@ static void enable_smbus(void) pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ pci_write_config8(dev, 0x11, 4); - + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); } @@ -30,7 +30,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va return; } -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { unsigned char global_control_register; @@ -41,11 +41,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* chear the PM timeout flags, SECOND_TO_STS */ outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return -2; } - + /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -56,39 +56,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - + /* set the command address */ outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - + /* set the block length */ outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - + /* try sending out the first byte of data here */ byte=(data1>>(0))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); for(i=0;i<length;i++) { - + /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { return -3; } - + /* load the next byte */ if(i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - + /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/esb6300_ehci.c index 8c20c0325f..c103c4bd2f 100644 --- a/src/southbridge/intel/esb6300/esb6300_ehci.c +++ b/src/southbridge/intel/esb6300/esb6300_ehci.c @@ -11,7 +11,7 @@ static void ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); @@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/esb6300_ide.c index 543468dabb..abe86a811d 100644 --- a/src/southbridge/intel/esb6300/esb6300_ide.c +++ b/src/southbridge/intel/esb6300/esb6300_ide.c @@ -16,7 +16,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x48, 0x05); pci_write_config16(dev, 0x4a, 0x0101); pci_write_config16(dev, 0x54, 0x5055); - + #if 0 uint16_t word; word = pci_read_config16(dev, 0x40); @@ -32,7 +32,7 @@ static void ide_init(struct device *dev) static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index fe035bb2c4..66ac62bb3f 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -96,7 +96,7 @@ static void set_esb6300_gpio_direction( switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) { case ESB6300_GPIO_SEL_OUTPUT: val = 0; break; case ESB6300_GPIO_SEL_INPUT: val = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -133,7 +133,7 @@ static void set_esb6300_gpio_level( case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break; case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break; case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -166,7 +166,7 @@ static void set_esb6300_gpio_inv( switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) { case ESB6300_GPIO_INV_OFF: val = 0; break; case ESB6300_GPIO_INV_ON: val = 1; break; - default: + default: continue; } gpio_inv &= ~( 1 << i); @@ -210,7 +210,7 @@ static void esb6300_gpio_init(device_t dev) /* Find the GPIO bar */ res = find_resource(dev, GPIO_BAR); if (!res) { - return; + return; } /* Set the use selects */ @@ -274,7 +274,7 @@ static void lpc_init(struct device *dev) pci_write_config8(dev, 0xa0, 0x20); pci_write_config8(dev, 0xad, 0x03); pci_write_config8(dev, 0xbb, 0x09); - + esb6300_enable_serial_irqs(dev); esb6300_pci_dma_cfg(dev); @@ -292,7 +292,7 @@ static void lpc_init(struct device *dev) /* Set up the PIRQ */ esb6300_pirq_init(dev); - + /* Set the state of the gpio lines */ esb6300_gpio_init(dev); @@ -346,7 +346,7 @@ static void esb6300_lpc_enable_resources(device_t dev) acpi_cntl = pci_read_config8(dev, 0x44); acpi_cntl |= (1 << 4); pci_write_config8(dev, 0x44, acpi_cntl); - + /* Enable the GPIO bar */ gpio_cntl = pci_read_config8(dev, 0x5c); gpio_cntl |= (1 << 4); diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c index 9d02536cd4..5bbf317411 100644 --- a/src/southbridge/intel/esb6300/esb6300_pic.c +++ b/src/southbridge/intel/esb6300/esb6300_pic.c @@ -40,7 +40,7 @@ static void pic_read_resources(device_t dev) res->limit = res->base + res->size -1; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; } diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/esb6300_sata.c index 5818df1819..6dce2d2f3a 100644 --- a/src/southbridge/intel/esb6300/esb6300_sata.c +++ b/src/southbridge/intel/esb6300/esb6300_sata.c @@ -15,37 +15,37 @@ static void sata_init(struct device *dev) /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); - + /* Set timmings */ pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); - + /* Sync DMA */ pci_write_config16(dev, 0x48, 0x000f); pci_write_config16(dev, 0x4a, 0x1111); - + /* 66 mhz */ pci_write_config16(dev, 0x54, 0xf00f); - + /* Combine ide - sata configuration */ pci_write_config8(dev, 0x90, 0x0); - + /* port 0 & 1 enable */ pci_write_config8(dev, 0x92, 0x33); - + /* initialize SATA */ pci_write_config16(dev, 0xa0, 0x0018); pci_write_config32(dev, 0xa4, 0x00000264); pci_write_config16(dev, 0xa0, 0x0040); pci_write_config32(dev, 0xa4, 0x00220043); - + printk(BIOS_DEBUG, "SATA Enabled\n"); } static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -66,7 +66,7 @@ static const struct pci_driver sata_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA, }; - + static const struct pci_driver sata_driver_nr __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.h b/src/southbridge/intel/esb6300/esb6300_smbus.h index 0b793c37f9..e7a0d5c711 100644 --- a/src/southbridge/intel/esb6300/esb6300_smbus.h +++ b/src/southbridge/intel/esb6300/esb6300_smbus.h @@ -10,7 +10,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/esb6300_uhci.c index 10b1dfa1cc..a8bcd888f1 100644 --- a/src/southbridge/intel/esb6300/esb6300_uhci.c +++ b/src/southbridge/intel/esb6300/esb6300_uhci.c @@ -12,7 +12,7 @@ static void uhci_init(struct device *dev) #if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index d629e2f144..eaa81e40c7 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -230,9 +230,9 @@ static void i3100_power_options(device_t dev) { /* avoid #S4 assertions */ reg8 |= (3 << 4); /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); + reg8 &= ~(1 << 3); pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -245,14 +245,14 @@ static void i3100_power_options(device_t dev) { /* PCI SERR# Disable for now */ reg8 |= (1 << 2); outb(reg8, 0x61); - + reg8 = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { /* Set NMI. */ printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); + reg8 &= ~(1 << 7); } else { /* Can't mask NMI from PCI-E and NMI_NOW */ printk(BIOS_INFO, "NMI sources disabled.\n"); @@ -267,7 +267,7 @@ static void i3100_power_options(device_t dev) { /* CLKRUN_EN */ // reg16 |= (1 << 2); pci_write_config16(dev, GEN_PMCON_1, reg16); - + // Set the board's GPI routing. // i82801gx_gpi_routing(dev); } @@ -321,7 +321,7 @@ static void lpc_init(struct device *dev) // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode // (register 0x10/0x11) while the old code used int 1 (register 0x12) - // ... Why? + // ... Why? setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c index cafb68fe0d..14c13da290 100644 --- a/src/southbridge/intel/i3100/i3100_sata.c +++ b/src/southbridge/intel/i3100/i3100_sata.c @@ -73,29 +73,29 @@ static void sata_init(struct device *dev) /* IDE I/O configuration */ pci_write_config32(dev, SATA_IIOC, 0); - + } else { /* SATA configuration */ pci_write_config8(dev, SATA_CMD, 0x07); pci_write_config8(dev, SATA_PI, 0x8f); - + /* Set timings */ pci_write_config16(dev, SATA_PTIM, 0x0a307); pci_write_config16(dev, SATA_STIM, 0x0a307); - + /* Sync DMA */ pci_write_config8(dev, SATA_SYNCC, 0x0f); pci_write_config16(dev, SATA_SYNCTIM, 0x1111); - + /* Fast ATA */ pci_write_config16(dev, SATA_IIOC, 0x1000); - + /* Select IDE mode */ pci_write_config8(dev, SATA_MAP, 0x00); - + /* Enable ports 0-3 */ pci_write_config8(dev, SATA_PCS + 1, 0x0f); - + } printk(BIOS_DEBUG, "SATA Enabled\n"); } diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h index a1ede98eb6..1c6f26a47d 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h @@ -31,9 +31,9 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) if ((val & 0x1) == 0) { break; } -#if 0 +#if 0 if(loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBHST_STATUS), + outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); } #endif @@ -48,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) do { unsigned short val; smbus_delay(); - + val = inb(smbus_io_base + SMBHST_STATUS); // Make sure the command is done - if ((val & 0x1) != 0) { + if ((val & 0x1) != 0) { continue; } // Don't break out until one of the interrupt @@ -71,7 +71,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); @@ -117,7 +117,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); @@ -160,7 +160,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* clear any lingering errors, so the transaction will run */ diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c index 2daa986bd4..da3e404d26 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_ide.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c @@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801ax_config config_t; static void ide_init(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = dev->chip_info; /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index 8fccdf0983..50be866be3 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801ax_config config_t; #define PIRQG 0x0A #define PIRQH 0x0B -/* - * Use 0x0ef8 for a bitmap to cover all these IRQ's. +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c index ffbaf80dbd..9d287b2b9b 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_ide.c +++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c @@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801bx_config config_t; static void ide_init(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = dev->chip_info; /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index c63de08c2a..96dbd54e37 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801bx_config config_t; #define PIRQG 0x0A #define PIRQH 0x0B -/* - * Use 0x0ef8 for a bitmap to cover all these IRQ's. +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index e4ec70bc5f..6287b631af 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -110,7 +110,7 @@ static int do_smbus_read_byte(unsigned device, unsigned address) return byte; } -/* This function is neither used nor tested by me (Corey Osgood), the author +/* This function is neither used nor tested by me (Corey Osgood), the author (Yinghai) probably tested/used it on i82801er */ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h index 99b069e82d..88415e0556 100644 --- a/src/southbridge/intel/i82801cx/chip.h +++ b/src/southbridge/intel/i82801cx/chip.h @@ -1,7 +1,7 @@ #ifndef I82801CX_CHIP_H #define I82801CX_CHIP_H -struct southbridge_intel_i82801cx_config +struct southbridge_intel_i82801cx_config { }; extern struct chip_operations southbridge_intel_i82801cx_ops; diff --git a/src/southbridge/intel/i82801cx/i82801cx.c b/src/southbridge/intel/i82801cx/i82801cx.c index ddbbc7da37..685c931fc8 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.c +++ b/src/southbridge/intel/i82801cx/i82801cx.c @@ -19,7 +19,7 @@ void i82801cx_enable(device_t dev) // Calculate disable bit position for specified device:function // NOTE: For ICH-3, only the following devices can be disabled: - // D31:F1, D31:F3, D31:F5, D31:F6, + // D31:F1, D31:F3, D31:F5, D31:F6, // D29:F0, D29:F1, D29:F2 if (PCI_SLOT(dev->path.pci.devfn) == 31) { diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index ea7d858d14..e0d377a9cd 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -70,9 +70,9 @@ void i82801cx_hard_reset(void); #define SMBTRNSADD 9 #define SMBSLVDATA 10 #define SMLINK_PIN_CTL 14 -#define SMBUS_PIN_CTL 15 +#define SMBUS_PIN_CTL 15 -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000) diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index 02420ef75b..b62db80f9c 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -10,9 +10,9 @@ static void enable_smbus(void) pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ pci_write_config8(dev, HOSTC, HST_EN); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation */ + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -55,7 +55,7 @@ static int smbus_wait_until_ready(void) } if(loops == (SMBUS_TIMEOUT / 2)) { // Clear status flags - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } } while(--loops); @@ -69,7 +69,7 @@ static int smbus_wait_until_done(void) do { unsigned char val; smbus_delay(); - + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); // !HOST_BUSY? if ( (val & 1) == 0) { @@ -92,7 +92,7 @@ static int smbus_read_byte(unsigned device, unsigned address) if (smbus_wait_until_ready() < 0) { return -2; } - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index 7523b03f80..97b2994abf 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -36,12 +36,12 @@ static void i82801cx_enable_ioapic( struct device *dev) dword |= (1 << 2); /* DMA collection buf enable */ pci_write_config32(dev, GEN_CNTL, dword); printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - + // Must program the APIC's ID before using it *ioapic_index = 0; // Select APIC ID register *ioapic_data = (2<<24); - + // Hang if the ID didn't take (chip not present?) *ioapic_index = 0; dword = *ioapic_data; @@ -65,11 +65,11 @@ static void i82801cx_enable_serial_irqs( struct device *dev) // Parameters: dev // mask - identifies whether each channel should be used for PCI DMA // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. -// Channel 4 is not used (reserved). +// Channel 4 is not used (reserved). // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -105,13 +105,13 @@ static void i82801cx_rtc_init(struct device *dev) pmcon3 |= SLEEP_AFTER_POWER_FAIL; } pci_write_config8(dev, GEN_PMCON_3, pmcon3); - printk(BIOS_INFO, "set power %s after power fail\n", + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); // See if the Safe Mode jumper is set dword = pci_read_config32(dev, GEN_STS); rtc_failed |= dword & (1 << 2); - + rtc_init(rtc_failed); } @@ -120,28 +120,28 @@ static void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); - + // Set ACPI base address to 0x1100 (I/O space) pci_write_config32(dev, PMBASE, 0x00001101); - + // Enable ACPI I/O and power management pci_write_config8(dev, ACPI_CNTL, 0x10); - + // Set GPIO base address to 0x1180 (I/O space) pci_write_config32(dev, GPIO_BASE, 0x00001181); - + // Enable GPIO pci_write_config8(dev, GPIO_CNTL, 0x10); - + // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - + // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted. pci_write_config8(dev, PIRQE_ROUT, 0x07); - + // Enable access to the upper 128 byte bank of CMOS RAM pci_write_config8(dev, RTC_CONF, 0x04); - + // Decode 0x3F8-0x3FF (COM1) for COMA port, // 0x2F8-0x2FF (COM2) for COMB pci_write_config8(dev, COM_DEC, 0x10); @@ -149,7 +149,7 @@ static void i82801cx_1f0_misc(struct device *dev) // LPT decode defaults to 0x378-0x37F and 0x778-0x77F // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 - // Enable COMA, COMB, LPT, floppy; + // Enable COMA, COMB, LPT, floppy; // disable microcontroller, Super I/O, sound, gameport pci_write_config16(dev, LPC_EN, 0x000F); } @@ -164,7 +164,7 @@ static void lpc_init(struct device *dev) i82801cx_enable_ioapic(dev); i82801cx_enable_serial_irqs(dev); - + /* power after power fail */ /* FIXME this doesn't work! */ /* Which state do we want to goto after g3 (power restored)? @@ -187,11 +187,11 @@ static void lpc_init(struct device *dev) byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); } - + /* Initialize the real time clock */ i82801cx_rtc_init(dev); diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c index b69bbc1d9d..324f82f286 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c @@ -9,7 +9,7 @@ void smbus_enable(void) { /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, + pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); @@ -31,13 +31,13 @@ static void smbus_wait_until_ready(void) static void smbus_wait_until_done(void) { unsigned char byte; - + // Loop while HOST_BUSY do { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } while((byte &1) == 1); - + // Wait for SUCCESS or error or BYTE_DONE while( (byte & ~1) == 0) { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c index 00b668d023..28cb3572e5 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_usb.c +++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c @@ -12,8 +12,8 @@ static void usb_init(struct device *dev) uint32_t cmd; printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 282ccfd247..ac904efa29 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -38,7 +38,7 @@ void i82801dx_enable(device_t dev) // Calculate disable bit position for specified device:function // NOTE: For ICH-4, only the following devices can be disabled: - // D31: F0, F1, F3, F5, F6, + // D31: F0, F1, F3, F5, F6, // D29: F0, F1, F2, F7 if (PCI_SLOT(dev->path.pci.devfn) == 31) { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 885f9de0f1..1b995b1204 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -20,11 +20,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. +/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. + * fb1 code is what we want, fb2 structure is needed however. + * so we need to get fb1 code for 82801dbm into fb2 structure. */ -/* What I did: took the 80801er stuff from fb2, verify it against the +/* What I did: took the 80801er stuff from fb2, verify it against the * db stuff in fb1, and made sure it was right. */ @@ -132,9 +132,9 @@ extern void i82801dx_enable(device_t dev); #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000) diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c index 16c6e11e72..f58cd86342 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c @@ -32,7 +32,7 @@ #define SMLINK_PIN_CTL 0xe #define SMBUS_PIN_CTL 0xf -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ //#define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index 34a0a97ffd..f04fc3fd29 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -1,7 +1,7 @@ #ifndef I82801EX_CHIP_H #define I82801EX_CHIP_H -struct southbridge_intel_i82801ex_config +struct southbridge_intel_i82801ex_config { #define ICH5R_GPIO_USE_MASK 0x03 diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index bc5f04bf44..fc4164523a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -25,7 +25,7 @@ void i82801ex_enable(device_t dev) (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | + if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { return; } @@ -39,7 +39,7 @@ void i82801ex_enable(device_t dev) if (reg != reg_old) { pci_write_config16(lpc_dev, 0xf2, reg); } - + } struct chip_operations southbridge_intel_i82801ex_ops = { diff --git a/src/southbridge/intel/i82801ex/i82801ex_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c index 65502dd8cc..08efe1534d 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ac97.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c @@ -8,7 +8,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index 27bd3f2324..b07c77a94f 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return; } - + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 @@ -60,11 +60,11 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va /* poll for transaction completion */ smbus_wait_until_done(SMBUS_IO_BASE); -#endif +#endif return; } -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { unsigned char byte; @@ -73,11 +73,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* chear the PM timeout flags, SECOND_TO_STS */ outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return -2; } - + /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -88,39 +88,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - + /* set the command address */ outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - + /* set the block length */ outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - + /* try sending out the first byte of data here */ byte=(data1>>(0))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); for(i=0;i<length;i++) { - + /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { return -3; } - + /* load the next byte */ if(i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - + /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c index 17da5d94c6..8ae921d194 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c @@ -11,7 +11,7 @@ static void ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); @@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c index cd622907ab..bbab6f1cc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ide.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c @@ -19,7 +19,7 @@ static void ide_init(struct device *dev) static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index b97af3860a..8753db17e3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -89,7 +89,7 @@ static void set_i82801ex_gpio_direction( switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; case ICH5R_GPIO_SEL_INPUT: val = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -121,7 +121,7 @@ static void set_i82801ex_gpio_level( case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -152,7 +152,7 @@ static void set_i82801ex_gpio_inv( switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { case ICH5R_GPIO_INV_OFF: val = 0; break; case ICH5R_GPIO_INV_ON: val = 1; break; - default: + default: continue; } gpio_inv &= ~( 1 << i); @@ -195,7 +195,7 @@ static void i82801ex_gpio_init(device_t dev) /* Find the GPIO bar */ res = find_resource(dev, GPIO_BAR); if (!res) { - return; + return; } /* Set the use selects */ @@ -271,7 +271,7 @@ static void lpc_init(struct device *dev) /* Set up the PIRQ */ i82801ex_pirq_init(dev); - + /* Set the state of the gpio lines */ i82801ex_gpio_init(dev); @@ -283,7 +283,7 @@ static void lpc_init(struct device *dev) /* Disable IDE (needed when sata is enabled) */ pci_write_config8(dev, 0xf2, 0x60); - + enable_hpet(dev); } @@ -330,7 +330,7 @@ static void i82801ex_lpc_enable_resources(device_t dev) acpi_cntl = pci_read_config8(dev, 0x44); acpi_cntl |= (1 << 4); pci_write_config8(dev, 0x44, acpi_cntl); - + /* Enable the GPIO bar */ gpio_cntl = pci_read_config8(dev, 0x5c); gpio_cntl |= (1 << 4); diff --git a/src/southbridge/intel/i82801ex/i82801ex_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c index 2394844ba4..80c6e49bc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_pci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c @@ -21,8 +21,8 @@ static void pci_init(struct device *dev) dword |= (1<<8); /* SERR# Enable */ dword |= (1<<6); /* Parity Error Response */ pci_write_config32(dev, 0x04, dword); -#endif - +#endif + word = pci_read_config16(dev, 0x1e); word |= 0xf800; /* Clear possible errors */ pci_write_config16(dev, 0x1e, word); diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c index a490f2a8c3..9b340e9afd 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_sata.c +++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c @@ -11,7 +11,7 @@ static void sata_init(struct device *dev) /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); - + /* Set timmings */ pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); @@ -25,10 +25,10 @@ static void sata_init(struct device *dev) /* Combine ide - sata configuration */ pci_write_config8(dev, 0x90, 0x0); - + /* port 0 & 1 enable */ pci_write_config8(dev, 0x92, 0x33); - + /* initialize SATA */ pci_write_config16(dev, 0xa0, 0x0018); pci_write_config32(dev, 0xa4, 0x00000264); diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h index 27acca494f..f330c0a5de 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_smbus.h +++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.h @@ -10,7 +10,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c index fe80079d09..56536b7273 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c @@ -12,7 +12,7 @@ static void uhci_init(struct device *dev) #if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index a4cf14c4f9..5899ad6c0e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -96,7 +96,7 @@ u32 cim_verb_data_size = 0; static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb) { int idx=0; - + while (idx < (cim_verb_data_size / sizeof(u32))) { u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 if (cim_verb_data[idx] != viddid) { diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c index b2523ff436..0f998dda9e 100644 --- a/src/southbridge/intel/i82870/p64h2_ioapic.c +++ b/src/southbridge/intel/i82870/p64h2_ioapic.c @@ -39,9 +39,9 @@ static void p64h2_ioapic_init(device_t dev) num_p64h2_ioapics++; // A note on IOAPIC addresses: - // 0 and 1 are used for the local APICs of the dual virtual + // 0 and 1 are used for the local APICs of the dual virtual // (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb). - // 6 and 7 are used for the local APICs of the dual virtual + // 6 and 7 are used for the local APICs of the dual virtual // (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb). // 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c) @@ -63,7 +63,7 @@ static void p64h2_ioapic_init(device_t dev) pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", - apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); apic_id <<= 24; // Convert ID to bitmask @@ -72,13 +72,13 @@ static void p64h2_ioapic_init(device_t dev) *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID if ((*pWindowRegister & (0xF<<24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); *pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); } static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c index a489fe53f9..89b86f5966 100644 --- a/src/southbridge/intel/i82870/p64h2_pcibridge.c +++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c @@ -35,5 +35,5 @@ static const struct pci_driver pcix_driver __pci_driver = { .ops = &pcix_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82870_1F0, -}; - +}; + diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c index 0a50e5a994..683ff20013 100644 --- a/src/southbridge/intel/pxhd/pxhd_bridge.c +++ b/src/southbridge/intel/pxhd/pxhd_bridge.c @@ -56,10 +56,10 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) word &= ~(3 << 9); word |= (2 << 9); pci_write_config16(dev, 0x40, word); - + /* reset the bus to make the new frequencies effective */ pci_bus_reset(&dev->link[0]); - } + } return pcix_scan_bridge(dev, max); } static void pcix_init(device_t dev) @@ -78,7 +78,7 @@ static void pcix_init(device_t dev) byte = pci_read_config8(dev, 0x04); byte |= 0x10; pci_write_config8(dev, 0x04, byte); - + /* Set drive strength */ word = pci_read_config16(dev, 0xe0); word = 0x0404; @@ -86,7 +86,7 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0xe4); word = 0x0404; pci_write_config16(dev, 0xe4, word); - + /* Set impedance */ word = pci_read_config16(dev, 0xe8); word = 0x0404; @@ -96,7 +96,7 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0x4c); word |= 1; pci_write_config16(dev, 0x4c, word); - + /* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); pci_write_config16(dev, 0xaa, word); @@ -108,12 +108,12 @@ static void pcix_init(device_t dev) dword = pci_read_config32(dev, 0x04); dword |= (1<<8); pci_write_config32(dev, 0x04, dword); - + /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); dword |= (3<<16); pci_write_config32(dev, 0x3c, dword); - + /* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); @@ -122,7 +122,7 @@ static void pcix_init(device_t dev) dword |= (1<<0); pci_write_config32(dev, 0x44, dword); } - + /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); if(dword) { /* do device A only */ @@ -133,7 +133,7 @@ static void pcix_init(device_t dev) dword |= (1<<1); pci_write_config32(dev, 0xc8, dword); } - + return; #endif } @@ -175,7 +175,7 @@ static void ioapic_init(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -197,14 +197,14 @@ static const struct pci_driver ioapic_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0326, - + }; static const struct pci_driver ioapic2_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0327, - + }; struct chip_operations southbridge_intel_pxhd_ops = { diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c index 8d80409719..753a663239 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c +++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c @@ -34,7 +34,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); device_t dev; - int is_mcp55 = 0; + int is_mcp55 = 0; dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0); if (dev) @@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->preferred_pm_profile = 1; //check fadt->sci_int = 9; /* disable system management mode by setting to 0 */ - fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt) + fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt) fadt->acpi_enable = 0xa1; fadt->acpi_disable = 0xa0; fadt->s4bios_req = 0x0; @@ -92,7 +92,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - fadt->duty_width = 3; + fadt->duty_width = 3; fadt->day_alrm = 0x7d; fadt->mon_alrm = 0x7e; fadt->century = 0x32; diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 84612890e9..1d2a066b1b 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -65,7 +65,7 @@ static void lpc_common_init(device_t dev, int master) if (master) setup_ioapic(ioapic_base, 0); - else + else clear_ioapic(ioapic_base); } diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index c276389bf7..70d74f5fab 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -51,7 +51,7 @@ static void rl5c476_init(device_t dev) printk(BIOS_DEBUG, "CF boot not enabled.\n"); return; } - + if (PCI_FUNC(dev->path.pci.devfn) != 1) { // Only configure if second CF slot. return; @@ -154,8 +154,8 @@ static void rl5c476_init(device_t dev) cptr = (unsigned char *)(cf_base + 0x200); printk(BIOS_DEBUG, "CF Config = %x\n",*cptr); - /* Set CF to decode 16 IO bytes on any 16 byte boundary - - * rely on the io windows of the bridge set up above to + /* Set CF to decode 16 IO bytes on any 16 byte boundary - + * rely on the io windows of the bridge set up above to * map those bytes into the addresses for IDE controller 3 * (0x1e8 - 0x1ef and 0x3ed - 0x3ee) */ @@ -167,10 +167,10 @@ static void rl5c476_read_resources(device_t dev) struct resource *resource; - /* For CF socket we need an extra memory window for + /* For CF socket we need an extra memory window for * the control structure of the CF itself */ - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ /* fake index as it isn't in PCI config space */ resource = new_resource(dev, 1); resource->flags |= IORESOURCE_MEM; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 2ade87214c..576578bb65 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -93,5 +93,5 @@ typedef struct pc16reg { u8 smpga0; } __attribute__ ((packed)) pc16reg_t; - + diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index fc73e39431..2efc3802b2 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -281,7 +281,7 @@ static const struct pci_driver lpc_driver __pci_driver = { .device = PCI_DEVICE_ID_SIS_SIS966_LPC, }; -#ifdef SLAVE_INIT // No device? +#ifdef SLAVE_INIT // No device? static struct device_operations lpc_slave_ops = { .read_resources = sis966_lpc_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c index e30cf60b4d..3e1e81730d 100644 --- a/src/southbridge/via/k8t890/k8t890_bridge.c +++ b/src/southbridge/via/k8t890/k8t890_bridge.c @@ -32,14 +32,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); - writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet - * says it is reserved + writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet + * says it is reserved */ writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ - /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP + /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP * (Forward VGA compatible memory and I/O cycles ) */ diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c index ad17fe624d..48aa739257 100644 --- a/src/southbridge/via/k8t890/k8t890_ctrl.c +++ b/src/southbridge/via/k8t890/k8t890_ctrl.c @@ -23,7 +23,7 @@ #include <device/pci_ids.h> #include <console/console.h> -/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate +/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c index 0505a6ff5a..037f5a75eb 100644 --- a/src/southbridge/via/k8t890/k8t890_early_car.c +++ b/src/southbridge/via/k8t890/k8t890_early_car.c @@ -38,7 +38,7 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. - */ + */ u8 k8t890_early_setup_ht(void) { @@ -115,7 +115,7 @@ u8 k8t890_early_setup_ht(void) static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { - + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); switch (size) { case 1: diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c index 38f69680fe..a1c42b7d59 100644 --- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c +++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c @@ -52,7 +52,7 @@ static void host_ctrl_enable_k8t890(struct device *dev) pci_write_config8(dev, 0xa6, 0x80); /* this will be possibly removed, when I figure out - * if the ROM SIP is good, second reason is that the + * if the ROM SIP is good, second reason is that the * unknown bits are AGP related, which are dummy on K8T890 */ diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 9642aa4d5c..aaaa76694d 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -48,7 +48,7 @@ tblpointer: .long 0x0 .long 0x0 .long 0x0 -.long 0x0 +.long 0x0 /* * The pointer to above table should be at 0xffffd, diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 43238ec050..85f007a097 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -18,7 +18,7 @@ static void keyboard_on(void) if (lpc_dev) { regval = pci_read_config8(lpc_dev, 0x51); - regval |= 0x0f; + regval |= 0x0f; pci_write_config8(lpc_dev, 0x51, regval); } pc_keyboard_init(0); @@ -27,9 +27,9 @@ static void keyboard_on(void) static void com_port_on(void) { #if 0 - // enable com1 and com2. + // enable com1 and com2. enables = pci_read_config8(dev, 0x6e); - + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 * is enable com port a as com1 kevinh/Ispiri - Old code * thought 0x01 would make it com1, that was wrong enables = diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c index 6cbf4c591f..647910aef6 100644 --- a/src/southbridge/via/vt8231/vt8231_acpi.c +++ b/src/southbridge/via/vt8231/vt8231_acpi.c @@ -10,20 +10,20 @@ static void acpi_init(struct device *dev) // Set ACPI base address to IO 0x4000 pci_write_config32(dev, 0x48, 0x4001); - + // Enable ACPI access (and setup like award) pci_write_config8(dev, 0x41, 0x84); - + // Set hardware monitor base address to IO 0x6000 pci_write_config32(dev, 0x70, 0x6001); - + // Enable hardware monitor (and setup like award) pci_write_config8(dev, 0x74, 0x01); - + // set IO base address to 0x5000 pci_write_config32(dev, 0x90, 0x5001); - - // Enable SMBus + + // Enable SMBus pci_write_config8(dev, 0xd2, 0x01); } diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index 5b38b8e521..af5a7729ee 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -8,18 +8,18 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vt8231_writesuper(uint8_t reg, uint8_t val) +static void vt8231_writesuper(uint8_t reg, uint8_t val) { outb(reg, SIO_BASE); outb(val, SIO_DATA); } -static void vt8231_writesiobyte(uint16_t reg, uint8_t val) +static void vt8231_writesiobyte(uint16_t reg, uint8_t val) { outb(val, reg); } -static void vt8231_writesioword(uint16_t reg, uint16_t val) +static void vt8231_writesioword(uint16_t reg, uint16_t val) { outw(val, reg); } @@ -29,26 +29,26 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) mainboard */ -static void enable_vt8231_serial(void) +static void enable_vt8231_serial(void) { uint8_t c; device_t dev; outb(6, 0x80); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - + if (dev == PCI_DEV_INVALID) { outb(7, 0x80); die("Serial controller not found\n"); } - - /* first, you have to enable the superio and superio config. + + /* first, you have to enable the superio and superio config. put a 6 reg 80 */ c = pci_read_config8(dev, 0x50); c |= 6; pci_write_config8(dev, 0x50, c); outb(2, 0x80); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address vt8231_writesuper(0xf4, 0xfe); // enable serial out diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index 40ef656c00..8ba72a387b 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -35,7 +35,7 @@ static void enable_smbus(void) // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - // Enable SMBus + // Enable SMBus c = pci_read_config8(dev, 0xd2); c |= 5; pci_write_config8(dev, 0xd2, c); @@ -244,7 +244,7 @@ static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) } #endif -/* for reference, here is the fancier version which we will use at some +/* for reference, here is the fancier version which we will use at some * point */ # if 0 diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c index c1df5ef5cd..46479c4af3 100644 --- a/src/southbridge/via/vt8231/vt8231_ide.c +++ b/src/southbridge/via/vt8231/vt8231_ide.c @@ -18,7 +18,7 @@ static void ide_init(struct device *dev) * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. */ - /* + /* printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); enables = pci_read_config8(dev, 0x42); printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); @@ -28,73 +28,73 @@ static void ide_init(struct device *dev) printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); */ } - + enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); enables |= 3; pci_write_config8(dev, 0x40, enables); enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - + // Enable prefetch buffers enables = pci_read_config8(dev, 0x41); enables |= 0xf0; pci_write_config8(dev, 0x41, enables); - + // Lower thresholds (cause award does it) enables = pci_read_config8(dev, 0x43); enables &= ~0x0f; enables |= 0x05; pci_write_config8(dev, 0x43, enables); - + // PIO read prefetch counter (cause award does it) pci_write_config8(dev, 0x44, 0x18); - + // Use memory read multiple pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. + + // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // kevinh@ispiri.com - the standard linux drivers seem ass slow when // used in native mode - I've changed back to classic enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. + // by the book, set the low-order nibble to 0xa. if (conf->enable_native_ide) { enables &= ~0xf; - // cf/cg silicon needs an 'f' here. + // cf/cg silicon needs an 'f' here. enables |= 0xf; } else { enables &= ~0x5; } - + pci_write_config8(dev, 0x9, enables); enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. + + // standard bios sets master bit. enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); enables |= 7; - + // No need for stepping - kevinh@ispiri.com enables &= ~0x80; - + pci_write_config8(dev, 0x4, enables); enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - + if (!conf->enable_native_ide) { // Use compatability mode - per award bios pci_write_config32(dev, 0x10, 0x0); pci_write_config32(dev, 0x14, 0x0); pci_write_config32(dev, 0x18, 0x0); pci_write_config32(dev, 0x1c, 0x0); - + // Force interrupts to use compat mode - just like Award bios pci_write_config8(dev, 0x3d, 00); pci_write_config8(dev, 0x3c, 0xff); - } + } } static struct device_operations ide_ops = { diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c index 6c517ff492..c874528dec 100644 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ b/src/southbridge/via/vt8231/vt8231_lpc.c @@ -25,7 +25,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); if (dev) { /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D + on the PCB routing of PINTA-D PINTA = IRQ11 PINTB = IRQ5 @@ -61,60 +61,60 @@ static void vt8231_init(struct device *dev) enables = pci_read_config8(dev, 0x6C); enables |= 0x80; pci_write_config8(dev, 0x6C, enables); - + // Map 4MB of FLASH into the address space pci_write_config8(dev, 0x41, 0x7f); - + // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered. enables = pci_read_config8(dev, 0x40); pci_write_config8(dev, 0x40, enables); - + // Set 0x42 to 0xf0 to match Award bios enables = pci_read_config8(dev, 0x42); enables |= 0xf0; pci_write_config8(dev, 0x42, enables); - + // Set bit 3 of 0x4a, to match award (dummy pci request) enables = pci_read_config8(dev, 0x4a); enables |= 0x08; pci_write_config8(dev, 0x4a, enables); - + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); - + // Set 0x58 to 0x03 to match Award pci_write_config8(dev, 0x58, 0x03); - + // enable the ethernet/RTC if (dev) { enables = pci_read_config8(dev, 0x51); - enables |= 0x18; + enables |= 0x18; pci_write_config8(dev, 0x51, enables); } // enable IDE, since Linux won't do it. // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. + // note: this should already be cleared, according to the book. enables = pci_read_config8(dev, 0x50); printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables); enables &= ~8; // need manifest constant here! printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables); pci_write_config8(dev, 0x50, enables); - + // set default interrupt values (IDE) enables = pci_read_config8(dev, 0x4c); printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. + // clear out whatever was there. enables &= ~0xf; enables |= 4; printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables); pci_write_config8(dev, 0x4c, enables); - - // set up the serial port interrupts. + + // set up the serial port interrupts. // com2 to 3, com1 to 4 pci_write_config8(dev, 0x46, 0x04); pci_write_config8(dev, 0x47, 0x03); @@ -123,7 +123,7 @@ static void vt8231_init(struct device *dev) /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); //ethernet_fixup(); - + // Start the rtc rtc_init(0); } diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c index d4771f6816..5cd6cd8ca1 100644 --- a/src/southbridge/via/vt8231/vt8231_nic.c +++ b/src/southbridge/via/vt8231/vt8231_nic.c @@ -5,7 +5,7 @@ #include <device/pci_ids.h> /* - * Enable the ethernet device and turn off stepping (because it is integrated + * Enable the ethernet device and turn off stepping (because it is integrated * inside the southbridge) */ static void nic_init(struct device *dev) diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c index 3dd0b4272b..e12a8db85a 100644 --- a/src/southbridge/via/vt8231/vt8231_usb.c +++ b/src/southbridge/via/vt8231/vt8231_usb.c @@ -9,7 +9,7 @@ static void usb_on(int enable) device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); /* USB controller 2 */ device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); - + /* enable USB1 */ if(dev2) { if (enable) { @@ -20,16 +20,16 @@ static void usb_on(int enable) pci_write_config8(dev2, 0x04, 0x00); } } - + if(dev0) { regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x10); + if (enable) + regval &= ~(0x10); else - regval |= 0x10; + regval |= 0x10; pci_write_config8(dev0, 0x50, regval); } - + /* enable USB2 */ if(dev3) { if (enable) { @@ -40,13 +40,13 @@ static void usb_on(int enable) pci_write_config8(dev3, 0x04, 0x00); } } - + if(dev0) { regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x20); + if (enable) + regval &= ~(0x20); else - regval |= 0x20; + regval |= 0x20; pci_write_config8(dev0, 0x50, regval); } } diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c index 747c2157f1..4fa2784661 100644 --- a/src/southbridge/via/vt8235/vt8235.c +++ b/src/southbridge/via/vt8235/vt8235.c @@ -12,7 +12,7 @@ static void keyboard_on(struct device *dev) u8 regval; regval = pci_read_config8(dev, 0x51); - regval |= 0x05; + regval |= 0x05; regval &= 0xfd; pci_write_config8(dev, 0x51, regval); @@ -23,7 +23,7 @@ static void keyboard_on(struct device *dev) void dump_south(device_t dev0) { int i,j; - + for(i = 0; i < 256; i += 16) { printk(BIOS_DEBUG, "0x%x: ", i); for(j = 0; j < 16; j++) { @@ -51,10 +51,10 @@ static void vt8235_enable(struct device *dev) model = pci_read_config16(dev,0x2); printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model); - + /* If this is not the southbridge itself just return. * This is necessary because USB devices are slot 10, whereas this - * device is slot 11 therefore usb devices get called first during + * device is slot 11 therefore usb devices get called first during * the bus scan. We don't want to wait until we could do dev->init * because that's too late. */ @@ -69,13 +69,13 @@ static void vt8235_enable(struct device *dev) /* enable RTC and ethernet */ regval = pci_read_config8(dev, 0x51); - regval |= 0x18; + regval |= 0x18; pci_write_config8(dev, 0x51, regval); /* turn on keyboard */ keyboard_on(dev); - /* enable USB 1.1 & USB 2.0 - redundant really since we've + /* enable USB 1.1 & USB 2.0 - redundant really since we've * already been there - see note above */ regval = pci_read_config8(dev, 0x50); diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c index 7823172485..11f98fae39 100644 --- a/src/southbridge/via/vt8235/vt8235_early_serial.c +++ b/src/southbridge/via/vt8235/vt8235_early_serial.c @@ -8,25 +8,25 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vt8235_writepnpaddr(uint8_t val) +static void vt8235_writepnpaddr(uint8_t val) { outb(val, 0x2e); outb(val, 0xeb); } -static void vt8235_writepnpdata(uint8_t val) +static void vt8235_writepnpdata(uint8_t val) { outb(val, 0x2f); outb(val, 0xeb); } -static void vt8235_writesiobyte(uint16_t reg, uint8_t val) +static void vt8235_writesiobyte(uint16_t reg, uint8_t val) { outb(val, reg); } -static void vt8235_writesioword(uint16_t reg, uint16_t val) +static void vt8235_writesioword(uint16_t reg, uint16_t val) { outw(val, reg); } @@ -36,12 +36,12 @@ static void vt8235_writesioword(uint16_t reg, uint16_t val) mainboard */ -static void enable_vt8235_serial(void) +static void enable_vt8235_serial(void) { // turn on pnp vt8235_writepnpaddr(0x87); vt8235_writepnpaddr(0x87); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address vt8235_writepnpaddr(0x7); vt8235_writepnpdata(0x2); diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c index db403eb5fb..1876461a3d 100644 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c @@ -12,7 +12,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf /* Define register settings */ #define HOST_RESET 0xff @@ -34,17 +34,17 @@ static void enable_smbus(void) /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); - + if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); - } + } // set IO base address to SMBUS_IO_BASE pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); - - // Enable SMBus + + // Enable SMBus pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); - + /* make it work for I/O ... */ pci_write_config16(dev, 4, 1); @@ -55,13 +55,13 @@ static void enable_smbus(void) for(i = 0 ; i < 5000 ; i++) outb(0x80,0x80); - /* + /* * The VT1211 serial port needs 48 mhz clock, on power up it is getting * only 24 mhz, there is some mysterious device on the smbus that can * fix this...this code below does it. * */ - outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); - outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); + outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); + outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD); outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); @@ -92,7 +92,7 @@ static int smbus_wait_until_ready(void) print_debug_hex8(c); print_debug("\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - /* nop */ + /* nop */ } } while(--loops); @@ -105,13 +105,13 @@ void smbus_reset(void) outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - + smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); print_debug("\n"); } - + static int smbus_wait_until_done(void) @@ -121,11 +121,11 @@ static int smbus_wait_until_done(void) loops = SMBUS_TIMEOUT; do { smbus_delay(); - + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); if (byte & 1) break; - + } while(--loops); return loops?0:-1; } @@ -156,46 +156,46 @@ static void smbus_print_error(unsigned char host_status_register) /* SMBus routines borrowed from VIA's Trident Driver */ /* this works, so I am not going to touch it for now -- rgm */ -static unsigned char smbus_read_byte(unsigned char devAdr, - unsigned char bIndex) +static unsigned char smbus_read_byte(unsigned char devAdr, + unsigned char bIndex) { unsigned short i; unsigned char bData; unsigned char sts = 0; - + /* clear host status */ outb(0xff, SMBUS_IO_BASE); - + /* check SMBUS ready */ for ( i = 0; i < 0xFFFF; i++ ) if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) break; - + /* set host command */ outb(bIndex, SMBUS_IO_BASE+3); - + /* set slave address */ outb(devAdr | 0x01, SMBUS_IO_BASE+4); - + /* start */ outb(0x48, SMBUS_IO_BASE+2); - + /* SMBUS Wait Ready */ for ( i = 0; i < 0xFFFF; i++ ) if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 ) break; - + if ((sts & ~3) != 0) { smbus_print_error(sts); return 0; } bData=inb(SMBUS_IO_BASE+5); - + return bData; - + } -/* for reference, here is the fancier version which we will use at some +/* for reference, here is the fancier version which we will use at some * point */ # if 0 @@ -203,11 +203,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) { unsigned char host_status_register; unsigned char byte; - + reset(); - + smbus_wait_until_ready(); - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); @@ -218,29 +218,29 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) /* set up for a byte data read */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - + /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - + /* clear the data byte...*/ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - + /* start the command */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - + /* poll for transaction completion */ smbus_wait_until_done(); - + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - + /* Ignore the In Use Status... */ host_status_register &= ~(1 << 6); - + /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); smbus_print_error(byte); - + *result = byte; return host_status_register != 0x02; } diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c index ec22f9053b..961f860fed 100644 --- a/src/southbridge/via/vt8235/vt8235_ide.c +++ b/src/southbridge/via/vt8235/vt8235_ide.c @@ -28,69 +28,69 @@ static void ide_init(struct device *dev) printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); /* } */ - + enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); enables |= 3; pci_write_config8(dev, 0x40, enables); enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - + // Enable prefetch buffers enables = pci_read_config8(dev, 0x41); enables |= 0xf0; pci_write_config8(dev, 0x41, enables); - + // Lower thresholds (cause award does it) enables = pci_read_config8(dev, 0x43); enables &= ~0x0f; enables |= 0x05; pci_write_config8(dev, 0x43, enables); - + // PIO read prefetch counter (cause award does it) pci_write_config8(dev, 0x44, 0x18); - + // Use memory read multiple pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. + + // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // kevinh@ispiri.com - the standard linux drivers seem ass slow when // used in native mode - I've changed back to classic enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. + // by the book, set the low-order nibble to 0xa. if (conf->enable_native_ide) { enables &= ~0xf; - // cf/cg silicon needs an 'f' here. + // cf/cg silicon needs an 'f' here. enables |= 0xf; } else { enables &= ~0x5; } - + pci_write_config8(dev, 0x9, enables); enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. + + // standard bios sets master bit. enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); enables |= 7; - + // No need for stepping - kevinh@ispiri.com enables &= ~0x80; - + pci_write_config8(dev, 0x4, enables); enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - + if (!conf->enable_native_ide) { // Use compatability mode - per award bios pci_write_config32(dev, 0x10, 0x0); pci_write_config32(dev, 0x14, 0x0); pci_write_config32(dev, 0x18, 0x0); pci_write_config32(dev, 0x1c, 0x0); - + // Force interrupts to use compat mode - just like Award bios pci_write_config8(dev, 0x3d, 0x0); pci_write_config8(dev, 0x3c, 0xff); @@ -103,10 +103,10 @@ static struct device_operations ide_ops = { .enable_resources = pci_dev_enable_resources, .init = ide_init, .enable = 0, - .ops_pci = 0, + .ops_pci = 0, }; -static const struct pci_driver northbridge_driver __pci_driver = { +static const struct pci_driver northbridge_driver __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_1, diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c index 0746bc9a13..e2bfc3681e 100644 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ b/src/southbridge/via/vt8235/vt8235_lpc.c @@ -88,7 +88,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_INFO, "setting pci slot\n"); pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - // Cardbus slot + // Cardbus slot printk(BIOS_INFO, "setting cardbus slot\n"); pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); @@ -99,11 +99,11 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __func__); } -/* +/* * Set up the power management capabilities directly into ACPI mode. This * avoids having to handle any System Management Interrupts (SMI's) which I * can't figure out how to do !!!! - */ + */ static void setup_pm(device_t dev) { @@ -112,7 +112,7 @@ static void setup_pm(device_t dev) // Set ACPI base address to IO 0x4000 pci_write_config16(dev, 0x88, 0x0401); - + // set ACPI irq to 5 pci_write_config8(dev, 0x82, 0x45); @@ -138,7 +138,7 @@ static void setup_pm(device_t dev) outw(0xffff, 0x420); outw(0xffff, 0x428); outl(0xffffffff, 0x430); - + outw(0x0, 0x424); outw(0x0, 0x42a); outw(0x1, 0x42c); @@ -152,29 +152,29 @@ static void setup_pm(device_t dev) static void vt8235_init(struct device *dev) { unsigned char enables; - + printk(BIOS_DEBUG, "vt8235 init\n"); // enable the internal I/O decode enables = pci_read_config8(dev, 0x6C); enables |= 0x80; pci_write_config8(dev, 0x6C, enables); - + // Map 4MB of FLASH into the address space pci_write_config8(dev, 0x41, 0x7f); - + // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered. enables = pci_read_config8(dev, 0x40); enables |= 0x45; pci_write_config8(dev, 0x40, enables); - + // Set 0x42 to 0xf0 to match Award bios enables = pci_read_config8(dev, 0x42); enables |= 0xf0; pci_write_config8(dev, 0x42, enables); - + /* Set 0x58 to 0x03 to match Award */ pci_write_config8(dev, 0x58, 0x03); @@ -187,16 +187,16 @@ static void vt8235_init(struct device *dev) enables = pci_read_config8(dev, 0x4a); enables |= 0x08; pci_write_config8(dev, 0x4a, enables); - + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); - + // Set 0x58 to 0x03 to match Award pci_write_config8(dev, 0x58, 0x03); - - + + /* enable serial irq */ pci_write_config8(dev, 0x52, 0x9); @@ -205,10 +205,10 @@ static void vt8235_init(struct device *dev) // Power management setup setup_pm(dev); - + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); - + // Start the rtc rtc_init(0); } @@ -248,7 +248,7 @@ static void vt8235_enable_resources(device_t dev) pci_dev_enable_resources(dev); enable_childrens_resources(dev); } - + static void southbridge_init(struct device *dev) { vt8235_init(dev); diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c index 86fef895de..71f169c055 100644 --- a/src/southbridge/via/vt8235/vt8235_nic.c +++ b/src/southbridge/via/vt8235/vt8235_nic.c @@ -5,7 +5,7 @@ #include <device/pci_ids.h> /* - * Enable the ethernet device and turn off stepping (because it is integrated + * Enable the ethernet device and turn off stepping (because it is integrated * inside the southbridge) */ static void nic_init(struct device *dev) diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index aa75f50651..9f824437bf 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -171,10 +171,10 @@ void enable_smbus(void) } /** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for * known-good data from a slot/address. Exits on either good data or a timeout. * * TODO: This should probably go into some global file, but one would need to diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index f7acb75766..5a08e3b16f 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -187,7 +187,7 @@ static void setup_pm(device_t dev) * 6 = SUSST# Deasserted Before PWRGD for STD * 5 = Keyboard/Mouse Swap * 4 = PWRGOOD reset on VT8237A/S - * 3 = GPO26/GPO27 is GPO + * 3 = GPO26/GPO27 is GPO * 2 = Disable Alert on Lan * 1 = SUSCLK/GPO4 * 0 = USB Wakeup @@ -247,7 +247,7 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; - + #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); /* @@ -260,9 +260,9 @@ static void vt8237r_init(struct device *dev) enables = pci_read_config8(dev, 0xe5); enables |= 0x23; pci_write_config8(dev, 0xe5, enables); - - /* - * Enable Flash Write Access. + + /* + * Enable Flash Write Access. * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) */ enables = pci_read_config8(dev, 0xe4); @@ -274,14 +274,14 @@ static void vt8237r_init(struct device *dev) enables |= 0x80; pci_write_config8(dev, 0x4E, enables); -#else +#else printk(BIOS_SPEW, "Entering vt8237r_init.\n"); /* * Enable SATA LED, disable special CPU Frequency Change - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. */ pci_write_config8(dev, 0xe5, 0x09); - + /* REQ5 as PCI request input - should be together with INTE-INTH. */ pci_write_config8(dev, 0xe4, 0x4); #endif @@ -329,7 +329,7 @@ static void vt8237s_init(struct device *dev) (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); /* - * REQ5 as PCI request input - should be together with INTE-INTH. + * REQ5 as PCI request input - should be together with INTE-INTH. */ pci_write_config8(dev, 0xe4, 0x04); diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 88c02bdc70..00e751ba98 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -1,4 +1,4 @@ -subdirs-y += fintek +subdirs-y += fintek subdirs-y += intel subdirs-y += ite subdirs-y += nsc diff --git a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c index 40de4e0007..c6527d1ba6 100644 --- a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c +++ b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c @@ -49,7 +49,7 @@ static void pnp_exit_conf_state(device_t dev) //---------------------------------------------------------------------------------- // Function: lpc47n227_pnp_set_iobase -// Parameters: dev - high 8 bits = Super I/O port, +// Parameters: dev - high 8 bits = Super I/O port, // low 8 bits = logical device number (per lpc47n227.h) // iobase - base I/O port for the logical device // Return Value: None @@ -80,7 +80,7 @@ void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase) //---------------------------------------------------------------------------------- // Function: lpc47n227_pnp_set_enable -// Parameters: dev - high 8 bits = Super I/O port, +// Parameters: dev - high 8 bits = Super I/O port, // low 8 bits = logical device number (per lpc47n227.h) // enable - 0 to disable, anythig else to enable // Return Value: None @@ -130,7 +130,7 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable) //---------------------------------------------------------------------------------- // Function: lpc47n227_enable_serial -// Parameters: dev - high 8 bits = Super I/O port, +// Parameters: dev - high 8 bits = Super I/O port, // low 8 bits = logical device number (per lpc47n227.h) // iobase - processor I/O port address to assign to this serial device // Return Value: bool diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 8dfb774b12..1431908f8e 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -76,9 +76,9 @@ static struct pnp_info pnp_dev_info[] = { //---------------------------------------------------------------------------------- // Function: enable_dev -// Parameters: dev - pointer to structure describing a Super I/O device +// Parameters: dev - pointer to structure describing a Super I/O device // Return Value: None -// Description: Create device structures and allocate resources to devices +// Description: Create device structures and allocate resources to devices // specified in the pnp_dev_info array (above). // static void enable_dev(device_t dev) @@ -89,7 +89,7 @@ static void enable_dev(device_t dev) //---------------------------------------------------------------------------------- // Function: lpc47n227_pnp_set_resources -// Parameters: dev - pointer to structure describing a Super I/O device +// Parameters: dev - pointer to structure describing a Super I/O device // Return Value: None // Description: Configure the specified Super I/O device with the resources // (I/O space, etc.) that have been allocate for it. @@ -137,11 +137,11 @@ void lpc47n227_pnp_enable(device_t dev) //---------------------------------------------------------------------------------- // Function: lpc47n227_init -// Parameters: dev - pointer to structure describing a Super I/O device +// Parameters: dev - pointer to structure describing a Super I/O device // Return Value: None // Description: Initialize the specified Super I/O device. // Devices other than COM ports and keyboard controller are ignored. -// For COM ports, we configure the baud rate. +// For COM ports, we configure the baud rate. // static void lpc47n227_init(device_t dev) { @@ -236,7 +236,7 @@ void lpc47n227_pnp_set_drq(device_t dev, unsigned drq) pnp_read_config(dev, PP_DMA_SELECTION_REGISTER); uint8_t new_config; - ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? + ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? new_config = (current_config & ~PP_DMA_MASK) | drq; pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config); } else { @@ -330,7 +330,7 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable) //---------------------------------------------------------------------------------- // Function: pnp_enter_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device +// Parameters: dev - pointer to structure describing a Super I/O device // Return Value: None // Description: Enable access to the LPC47N227's configuration registers. // @@ -341,7 +341,7 @@ static void pnp_enter_conf_state(device_t dev) //---------------------------------------------------------------------------------- // Function: pnp_exit_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device +// Parameters: dev - pointer to structure describing a Super I/O device // Return Value: None // Description: Disable access to the LPC47N227's configuration registers. // diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 4c69a2c2c0..b6918470e0 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -4,7 +4,7 @@ * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx * Copyright (C) 2004 Tyan By LYH change from PC87360 - * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) + * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by |