diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 33 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 43 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu_info.c | 50 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 16 |
8 files changed, 14 insertions, 133 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 763b96307f..26f90218d7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_ITSS diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 93eacfb0a8..75d57a9c19 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -45,7 +45,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c ramstage-y += cpu.c -ramstage-y += cpu_info.c ramstage-y += dsp.c ramstage-y += elog.c ramstage-y += finalize.c @@ -73,7 +72,6 @@ ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c -smm-y += cpu_info.c smm-y += gpio.c smm-y += pch.c smm-y += pmutil.c diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index f9b39f28a0..929afa46fe 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -30,6 +30,7 @@ #include <cpu/x86/tsc.h> #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/cpulib.h> #include <soc/intel/common/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index ee344efb13..4a5bf08042 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -14,18 +14,13 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <console/console.h> #include <cpu/x86/msr.h> #include <delay.h> +#include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/msr.h> #include <reset.h> #include <soc/bootblock.h> -#include <soc/cpu.h> -#include <soc/iomap.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <stdint.h> /* Soft Reset Data Register Bit 12 = MAX Boot Frequency */ #define SPI_STRAP_MAX_FREQ (1<<12) @@ -93,24 +88,10 @@ void bootblock_cpu_init(void) void set_max_freq(void) { - msr_t msr, perf_ctl, platform_info; - - /* Check for configurable TDP option */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { + if (cpu_config_tdp_levels()) /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - - perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); + cpu_set_p_state_to_nominal_tdp_ratio(); + else + /* Set to max non Turbo ratio */ + cpu_set_p_state_to_max_non_turbo_ratio(); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a40aefcf4f..7cf4a75575 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,6 +34,7 @@ #include <cpu/x86/name.h> #include <cpu/x86/smm.h> #include <delay.h> +#include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <pc80/mc146818rtc.h> #include <soc/cpu.h> @@ -105,15 +106,6 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - /* * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL @@ -193,7 +185,7 @@ void set_power_limits(u8 power_limit_1_time) if (cpu_config_tdp_levels()) { msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; - limit.lo = msr.lo & 0xff; + limit.lo = cpu_get_tdp_nominal_ratio(); wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); } } @@ -254,9 +246,9 @@ static void configure_misc(void) msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ if (conf->eist_enable) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + cpu_enable_eist(); else - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ + cpu_disable_eist(); wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ @@ -299,31 +291,6 @@ static void configure_dca_cap(void) } } -static void set_max_ratio(void) -{ - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); -} - static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -514,7 +481,7 @@ static void per_cpu_smm_trigger(void) static void post_mp_init(void) { /* Set Max Ratio */ - set_max_ratio(); + cpu_set_max_ratio(); /* * Now that all APs have been relocated as well as the BSP let SMIs diff --git a/src/soc/intel/skylake/cpu_info.c b/src/soc/intel/skylake/cpu_info.c deleted file mode 100644 index a1fa062225..0000000000 --- a/src/soc/intel/skylake/cpu_info.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/ramstage.h> -#include <soc/systemagent.h> - -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == SKYLAKE_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index f6803c9e04..7bfd8bae2b 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -59,7 +59,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); /* CPU identification */ u32 cpu_family_model(void); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 36eefdb7b0..98f25a153e 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -21,9 +21,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_BIOS_UPGD_TRIG 0x7a -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -31,13 +28,8 @@ #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define PRMRR_PHYS_BASE_MSR 0x1f4 -#define PRMRR_PHYS_MASK_MSR 0x1f5 -#define PRMRR_PHYS_MASK_LOCK (1 << 10) -#define PRMRR_PHYS_MASK_VALID (1 << 11) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 -#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define MSR_VR_CURRENT_CONFIG 0x601 @@ -46,12 +38,4 @@ #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) - #endif |