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-rw-r--r--src/mainboard/asus/Kconfig7
-rw-r--r--src/mainboard/asus/m2n-e/Kconfig105
-rw-r--r--src/mainboard/asus/m2n-e/Makefile.inc22
-rw-r--r--src/mainboard/asus/m2n-e/chip.h23
-rw-r--r--src/mainboard/asus/m2n-e/cmos.layout117
-rw-r--r--src/mainboard/asus/m2n-e/devicetree.cb120
-rw-r--r--src/mainboard/asus/m2n-e/fanctl.c64
-rw-r--r--src/mainboard/asus/m2n-e/get_bus_conf.c121
-rw-r--r--src/mainboard/asus/m2n-e/hda_verb.h123
-rw-r--r--src/mainboard/asus/m2n-e/mainboard.c39
-rw-r--r--src/mainboard/asus/m2n-e/mptable.c111
-rw-r--r--src/mainboard/asus/m2n-e/resourcemap.c281
-rw-r--r--src/mainboard/asus/m2n-e/romstage.c184
13 files changed, 1317 insertions, 0 deletions
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index 6848d8b79a..bf8742a3f0 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE
bool "A8V-E SE"
config BOARD_ASUS_A8V_E_DELUXE
bool "A8V-E Deluxe"
+config BOARD_ASUS_M2N_E
+ bool "M2N-E"
config BOARD_ASUS_M2V
bool "M2V"
config BOARD_ASUS_M2V_MX_SE
@@ -57,6 +59,7 @@ endchoice
source "src/mainboard/asus/a8n_e/Kconfig"
source "src/mainboard/asus/a8v-e_se/Kconfig"
source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
+source "src/mainboard/asus/m2n-e/Kconfig"
source "src/mainboard/asus/m2v/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
@@ -74,4 +77,8 @@ config MAINBOARD_VENDOR
string
default "ASUS"
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1043
+
endif # VENDOR_ASUS
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
new file mode 100644
index 0000000000..60b7e15684
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/Kconfig
@@ -0,0 +1,105 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_ASUS_M2N_E
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_SOCKET_AM2
+ select DIMM_DDR2
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
+ select SUPERIO_ITE_IT8716F
+ select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_HARD_RESET
+ select LIFT_BSP_APIC_ID
+ select K8_REV_F_SUPPORT
+ select BOARD_ROMSIZE_KB_512
+ select RAMINIT_SYSINFO
+ select K8_ALLOCATE_IO_RANGE
+
+config MAINBOARD_DIR
+ string
+ default asus/m2n-e
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "M2N-E"
+
+config PCI_64BIT_PREF_MEM
+ bool
+ default n
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
+config SERIAL_CPU_INIT
+ bool
+ default n
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x8239
+
+endif # BOARD_ASUS_M2N_E
diff --git a/src/mainboard/asus/m2n-e/Makefile.inc b/src/mainboard/asus/m2n-e/Makefile.inc
new file mode 100644
index 0000000000..6bf6d9d4fd
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
+
diff --git a/src/mainboard/asus/m2n-e/chip.h b/src/mainboard/asus/m2n-e/chip.h
new file mode 100644
index 0000000000..a69b9ef27c
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/asus/m2n-e/cmos.layout b/src/mainboard/asus/m2n-e/cmos.layout
new file mode 100644
index 0000000000..4c6b82cc20
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/cmos.layout
@@ -0,0 +1,117 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb
new file mode 100644
index 0000000000..e51f78a3f8
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/devicetree.cb
@@ -0,0 +1,120 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device lapic_cluster 0 on # (L)APIC cluster
+ chip cpu/amd/socket_AM2 # CPU socket
+ device lapic 0 on end # Local APIC of the CPU
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # Northbridge / RAM controller
+ device pci 18.0 on # Link 0 == LDT 0
+ chip southbridge/nvidia/mcp55 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/ite/it8716f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2 (N/A)
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ io 0x62 = 0x000
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ io 0x62 = 0x000
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard IRQ
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12 # PS/2 mouse IRQ
+ end
+ device pnp 2e.7 off # GPIO
+ io 0x60 = 0x0000 # SMI# Normal Run Access
+ io 0x62 = 0x800 # Simple I/O
+ io 0x64 = 0x0000 # Serial Flash I/F
+ end
+ device pnp 2e.8 off # MIDI (N/A)
+ end
+ device pnp 2e.9 off # Game port (N/A)
+ end
+ device pnp 2e.a off # Consumer IR (N/A)
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # Azalia (HD Audio)
+ device pci 8.0 on end # NIC
+ device pci 9.0 off end # NIC (N/A)
+ device pci a.0 on end # PCI E 5 (PCIEX4)
+ device pci b.0 off end # PCI E 4
+ device pci c.0 on end # PCI E 3 (PCIEX1_2)
+ device pci d.0 on end # PCI E 2 (PCIEX1_1)
+ device pci e.0 off end # PCI E 1
+ device pci f.0 off end # PCI E 0
+ register "ide0_enable" = "1" # Primary IDE
+ register "ide1_enable" = "0" # Secondary IDE (N/A)
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/asus/m2n-e/fanctl.c b/src/mainboard/asus/m2n-e/fanctl.c
new file mode 100644
index 0000000000..c5eb25e68b
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/fanctl.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The ASUS M2N-E has 6 different fans, connected to two different chips:
+ * - ITE IT8716F: fan1 = CPU_FAN, fan2 = CHA_FAN1, fan3 = PWR_FAN1
+ * - Analog Devices ADT7475: fan1 = CHA_FAN4, fan2 = CHA_FAN2, fan3 = CHA_FAN3
+ */
+
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/ite/it8716f/it8716f.h>
+
+static void write_index(u16 port, u8 reg, u8 value)
+{
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static const struct {
+ u8 index;
+ u8 value;
+} sequence[] = {
+ /* Enable startup of monitoring operations. */
+ { 0x00, 0x11},
+ /* Polarity active-high, PWM frequency 23.43KHz, activate fans 1-3. */
+ { 0x14, 0xd7},
+ /* Set the correct sensor types. TMPIN1: diode, TMPIN2/3: resistor. */
+ { 0x51, 0x31},
+ /* Fan1 (CPU_FAN) is software-controlled. */
+ { 0x15, 0x7f},
+ /* Fan2 (CHA_FAN1) is software-controlled. */
+ { 0x16, 0x7f},
+ /* Fan3 (PWR_FAN1) is software-controlled. */
+ { 0x17, 0x7f},
+ /* Enable fan1/2/3, select "on/off mode" for all of them. */
+ { 0x13, 0x70},
+};
+
+/* Called from src/ite/it8716f/superio.c. */
+void init_ec(u16 base)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sequence); i++)
+ write_index(base, sequence[i].index, sequence[i].value);
+}
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
new file mode 100644
index 0000000000..a39ac22d7e
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/get_bus_conf.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+#include <cpu/amd/amdk8_sysconf.h>
+#include <stdlib.h>
+
+/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
+// busnum is default.
+unsigned char bus_mcp55[8]; // 1
+unsigned apicid_mcp55;
+
+unsigned pci1234x[] = {
+ /* Here you only need to set value in pci1234 for HT-IO that could
+ * be installed or not. You may need to preset pci1234 for HTIO board,
+ * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
+ */
+ 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0
+};
+
+unsigned hcdnx[] = {
+ /* HT Chain device num, actually it is unit id base of every ht
+ * device in chain, assume every chain only have 4 ht device at most.
+ */
+ 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+};
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+ unsigned int apicid_base, sbdn;
+ device_t dev;
+ int i;
+
+ if (get_bus_conf_done == 1)
+ return; /* Do it only once. */
+
+ get_bus_conf_done = 1;
+
+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */
+ sbdn = sysconf.sbdn;
+
+ for (i = 0; i < 8; i++)
+ bus_mcp55[i] = 0;
+
+ bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+
+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
+ if (dev) {
+ bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_mcp55[2]++;
+ } else {
+ printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, "
+ "using defaults\n", sbdn + 0x06);
+ bus_mcp55[1] = 2;
+ bus_mcp55[2] = 3;
+ }
+
+ for (i = 2; i < 8; i++) {
+ dev = dev_find_slot(bus_mcp55[0],
+ PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
+ if (dev)
+ bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+
+#if CONFIG_LOGICAL_CPUS == 1
+ apicid_base = get_apicid_base(1);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_mcp55 = apicid_base + 0;
+}
diff --git a/src/mainboard/asus/m2n-e/hda_verb.h b/src/mainboard/asus/m2n-e/hda_verb.h
new file mode 100644
index 0000000000..d8f489e287
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/hda_verb.h
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * HDA codec soldered onto the ASUS M2N-E:
+ * Analog Devices AD1988B (High Definition Audio SoundMAX Codec), rev. 0x100200
+ * http://www.analog.com/static/imported-files/data_sheets/AD1988A_1988B.pdf
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11d4198b, /* Codec Vendor / Device ID: Analog Devices AD1988B */
+ 0x104381f6, /* Subsystem ID (0x1043 == ASUS) */
+ 0x0000000d, /* Number of "pin complex" entries in the table */
+
+ /* NID 0x01, FUNCTION, Designates this device as an audio codec */
+ /* Set the Implementation ID (IID), here: 0x104381f6. */
+ 0x001720f6,
+ 0x00172181,
+ 0x00172243,
+ 0x00172310,
+
+ /* "Pin complex" HDA widgets. Comments: Node ID, Name, Description. */
+
+ /* NID 0x11, Port A, Front panel headphone jack */
+ 0x01171c30,
+ 0x01171d41,
+ 0x01171e21,
+ 0x01171f02,
+
+ /* NID 0x12, Port D, Rear panel front speaker jack */
+ 0x01271c10,
+ 0x01271d40,
+ 0x01271e01,
+ 0x01271f01,
+
+ /* NID 0x13, MONO_OUT, Monaural output pin */
+ 0x01371cf0,
+ 0x01371d11,
+ 0x01371e17,
+ 0x01371f51,
+
+ /* NID 0x14, Port B, Front panel microphone jack */
+ 0x01471c22,
+ 0x01471d91,
+ 0x01471ea1,
+ 0x01471f02,
+
+ /* NID 0x15, Port C, Rear panel line-in jack */
+ 0x01571c21,
+ 0x01571d30,
+ 0x01571e81,
+ 0x01571f01,
+
+ /* NID 0x16, Port F, Rear panel surround-back (5.1) jack */
+ 0x01671c12,
+ 0x01671d10,
+ 0x01671e01,
+ 0x01671f01,
+
+ /* NID 0x17, Port E, Rear panel microphone jack */
+ 0x01771c20,
+ 0x01771d90,
+ 0x01771ea1,
+ 0x01771f01,
+
+ /* NID 0x18, CD IN, Analog CD input */
+ 0x01871c2e,
+ 0x01871d11,
+ 0x01871e33,
+ 0x01871f99,
+
+ /* NID 0x1a, Analog PCBEEP, External analog PCBEEP signal input */
+ 0x01a71cf0,
+ 0x01a71d01,
+ 0x01a71ef3,
+ 0x01a71f99,
+
+ /* NID 0x1b, S/PDIF Out, S/PDIF output pin */
+ 0x01b71cf0,
+ 0x01b71df1,
+ 0x01b71e45,
+ 0x01b71f01,
+
+ /* NID 0x1c, S/PDIF In, S/PDIF input pin */
+ 0x01c71cf0,
+ 0x01c71df1,
+ 0x01c71ec5,
+ 0x01c71f41,
+
+ /* NID 0x24, Port G, Rear panel C/LFE jack */
+ 0x02471c11,
+ 0x02471d60,
+ 0x02471e01,
+ 0x02471f01,
+
+ /* NID 0x25, Port H, Rear panel surround-side (7.1) jack */
+ 0x02571c14,
+ 0x02571d20,
+ 0x02571e01,
+ 0x02571f01,
+};
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+
diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c
new file mode 100644
index 0000000000..aa0cc5c77a
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "hda_verb.h"
+#include "chip.h"
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2N-E Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
new file mode 100644
index 0000000000..20531771fe
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+#define PCI_INT(bus, dev, fn, pin) \
+ smp_write_intsrc(mc, mp_INT, \
+ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, \
+ bus_mcp55[bus], (((dev) << 2) | (fn)), apicid_mcp55, (pin))
+
+extern unsigned char bus_mcp55[8];
+extern unsigned apicid_mcp55;
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ unsigned int sbdn;
+ int i, j, bus_isa;
+ device_t dev;
+ struct resource *res;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, "M2N-E ", LAPIC_ADDR);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+ sbdn = sysconf.sbdn;
+
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_1);
+ if (res)
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+
+ pci_write_config32(dev, 0x7c, 0x00000000);
+ pci_write_config32(dev, 0x80, 0x11002009);
+ pci_write_config32(dev, 0x84, 0x2000dd08);
+ }
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
+
+ /* I/O Ints */
+ PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */
+ PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */
+ PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */
+ PCI_INT(0, sbdn + 4, 0, 14); /* IDE */
+ PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */
+ PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */
+ PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */
+ PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */
+ PCI_INT(0, sbdn + 8, 0, 24); /* NIC */
+
+ /* PCI-E slots (two x1, one x4, one x16) */
+ for (j = 7; j >= 2; j--) {
+ if (!bus_mcp55[j])
+ continue;
+ for (i = 0; i < 4; i++)
+ PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
+ }
+
+ /* PCI slots (three on this board) */
+ for (j = 0; j < 3; j++) {
+ for (i = 0; i < 4; i++)
+ PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4);
+ }
+
+ /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+
+ /* Compute the checksums. */
+ mc->mpe_checksum =
+ smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
new file mode 100644
index 0000000000..c190399cbd
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/resourcemap.c
@@ -0,0 +1,281 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration region i
+ */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+
+ };
+
+ int max = ARRAY_SIZE(register_values);
+ setup_resource_map(register_values, max);
+}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
new file mode 100644
index 0000000000..eaa9edaace
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -0,0 +1,184 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/nvidia/mcp55/early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include <lib.h>
+#include <spd.h>
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/ite/it8716f/early_serial.c"
+#include "superio/ite/it8716f/early_init.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/debug.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
+
+static void memreset(int controllers, const struct mem_controller *ctrl) {}
+static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/f.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "lib/generic_sdram.c"
+#include "resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+static void sio_setup(void)
+{
+ u8 byte;
+ u32 dword;
+ device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
+
+ /* Subject decoding */
+ byte = pci_read_config8(dev, 0x7b);
+ byte |= (1 << 5);
+ pci_write_config8(dev, 0x7b, byte);
+
+ /* LPC Positive Decode 0 */
+ dword = pci_read_config32(dev, 0xa0);
+ dword |= (1 << 0); /* COM1 */
+ pci_write_config32(dev, 0xa0, dword);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const u16 spd_addr[] = {
+ DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */
+ DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */
+ };
+
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ int needs_reset = 0;
+ unsigned bsp_apicid = 0;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Allow the HT devices to be found. */
+ enumerate_ht_chain();
+ sio_setup();
+ }
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+ /* FIXME: This should be part of the Super I/O code/config. */
+ pnp_enter_ext_func_mode(SERIAL_DEV);
+ pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */
+ it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ pnp_exit_ext_func_mode(SERIAL_DEV);
+
+ setup_mb_resource_map();
+ uart_init();
+ report_bist_failure(bist);
+#if CONFIG_USBDEBUG
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+ early_usbdebug_init();
+#endif
+ console_init();
+
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
+ printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
+
+#if CONFIG_MEM_TRAIN_SEQ == 1
+ /* In BSP so could hold all AP until sysinfo is in RAM. */
+ set_sysinfo_in_ram(0);
+#endif
+
+ setup_coherent_ht_domain(); /* Routing table and start other core0. */
+ wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS == 1
+ /*
+ * It is said that we should start core1 after all core0 launched
+ * becase optimize_link_coherent_ht is moved out from
+ * setup_coherent_ht_domain, so here need to make sure last core0 is
+ * started, esp for two way system (there may be APIC ID conflicts in
+ * that case).
+ */
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+ /* Set up chains and store link pair for optimization later. */
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+ /* TODO: FIDVID */
+
+ init_timer(); /* Need to use TMICT to synconize FID/VID. */
+
+ needs_reset |= optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ needs_reset |= mcp55_early_setup_x();
+
+ /*
+ * FIDVID change will issue one LDTSTOP and the HT change will be
+ * effective too.
+ */
+ if (needs_reset) {
+ print_info("ht reset -\n");
+ soft_reset();
+ }
+ allow_all_aps_stop(bsp_apicid);
+
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+ enable_smbus();
+
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+ /* BSP switch stack to RAM and copy sysinfo RAM now. */
+ post_cache_as_ram();
+}
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