diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/include/arch/memlayout.h | 2 | ||||
| -rw-r--r-- | src/device/pci_ops_mmconf.c | 2 | ||||
| -rw-r--r-- | src/drivers/elog/boot_count.c | 2 | ||||
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pcr/pcr.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 12 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 18 |
7 files changed, 21 insertions, 19 deletions
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index f93dece086..de80f42a0d 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -23,7 +23,7 @@ #define ARCH_STAGE_HAS_BSS_SECTION 0 #endif -#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP +#if (CONFIG_RAMTOP == 0) # error "CONFIG_RAMTOP not configured" #endif diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c index 04f3d23fd3..f321347fda 100644 --- a/src/device/pci_ops_mmconf.c +++ b/src/device/pci_ops_mmconf.c @@ -15,7 +15,7 @@ #include <device/pci.h> #include <device/pci_ops.h> -#if !defined(CONFIG_MMCONF_BASE_ADDRESS) || !CONFIG_MMCONF_BASE_ADDRESS +#if (CONFIG_MMCONF_BASE_ADDRESS == 0) #error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!" #endif diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index c4373ee44a..fd86f39065 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -30,7 +30,7 @@ # include "option_table.h" # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) #else -# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) && CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET +# if (CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET != 0) # define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET # else # error "Must configure CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 5d7497df56..5b71c3d1e2 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -198,7 +198,7 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, # include "option_table.h" # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) #else -# if defined(CONFIG_CMOS_POST_OFFSET) && CONFIG_CMOS_POST_OFFSET +# if (CONFIG_CMOS_POST_OFFSET != 0) # define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET # else # error "Must configure CONFIG_CMOS_POST_OFFSET" diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 804ccff39b..e354c032fc 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -21,7 +21,7 @@ #include <soc/pci_devs.h> #include <timer.h> -#if !defined(CONFIG_PCR_BASE_ADDRESS) || (CONFIG_PCR_BASE_ADDRESS == 0) +#if (CONFIG_PCR_BASE_ADDRESS == 0) #error "PCR_BASE_ADDRESS need to be non-zero!" #endif diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 07ac4e8fa3..cbbfaaaf06 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -170,12 +170,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->LockDownConfigSpiEiss = 0; } /* only replacing preexisting subsys ID defaults when non-zero */ -#if defined(CONFIG_SUBSYSTEM_VENDOR_ID) && CONFIG_SUBSYSTEM_VENDOR_ID - params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; -#endif -#if defined(CONFIG_SUBSYSTEM_DEVICE_ID) && CONFIG_SUBSYSTEM_DEVICE_ID - params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; -#endif + if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) + params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; + + if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) + params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; + params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride; params->WakeConfigPcieWakeFromDeepSx = diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 18c2aef676..3ade8d72cf 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -391,14 +391,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SpiFlashCfgLockDown = 0; } /* only replacing preexisting subsys ID defaults when non-zero */ -#if defined(CONFIG_SUBSYSTEM_VENDOR_ID) && CONFIG_SUBSYSTEM_VENDOR_ID - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; -#endif -#if defined(CONFIG_SUBSYSTEM_DEVICE_ID) && CONFIG_SUBSYSTEM_DEVICE_ID - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; -#endif + if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { + params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; + params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; + } + + if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { + params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; + params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; + } + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |