diff options
Diffstat (limited to 'src')
46 files changed, 8 insertions, 56 deletions
diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 267ecb15fd..15ec61e717 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -38,7 +38,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x001c0301" register "gen4_dec" = "0x00fc0701" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 9eba6fca82..32438a102f 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "0" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f393f6..0c25d4d91a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071fabb..27705b91f7 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index d3f1795f91..e791d70976 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" # HWM - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index a6bcb1d7aa..6fa9e8357d 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x000406f1" register "gen4_dec" = "0x000c06a1" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index ceb9279365..57b4960a12 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" register "pcie_port_coalesce" = "0" - register "p_cnt_throttling_supported" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index d8a0ee1c31..3c08b8bb60 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 1b27a69b54..ec7fb201d7 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 046db97585..33d3544264 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ddcf4e22d1..b9ccbf938c 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 79a84b73c2..c638676e54 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index a301857b7a..06124ed30d 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x007c0281" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index a06aea9669..6852f02710 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -60,7 +60,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 471537218e..3725b08f66 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index d98402c540..0a30de287b 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -49,7 +49,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 95659beaf5..1472f84043 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index d626934343..cd610b6ac6 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index ad69ca27e4..32d04ea190 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 68e7c63767..5108db4a65 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 4ed1f3c694..0a024b70d3 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x003c0701" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fad139a7ac..8928b87988 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 48c2ea010e..024b8f8dd1 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x00000000" register "gpi13_routing" = "2" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index a9e8babe6e..15d323d8b9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index c4092fe901..6deff6039c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index d1e3f75499..aa6cc68154 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69ec0..f7e04367c6 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 21d54acf11..0c2f668897 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index eff2d69304..7893daf9ec 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index ceca46ea84..8716046410 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 335543a8f7..190539ac1f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 0a80fa1d8c..0844124f0e 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen4_dec" = "0x000c06a1" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 21d38f5ab2..2a98a60cac 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "0x0065" - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 8caa0d1a2f..288870f81d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6ece08bee6..bf74d710bb 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/nehalem register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "p_cnt_throttling_supported" = "1" register "c2_latency" = "1" register "docking_supported" = "1" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 360de04943..26fa1a4d1f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 4687e9ccc3..61a5468a78 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 4db2536148..fc23f359e3 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "p_cnt_throttling_supported" = "1" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 1dfa02d317..68f2ba437f 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "p_cnt_throttling_supported" = "1" register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index f1016210e6..76ad9859c6 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "p_cnt_throttling_supported" = "1" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index feae5bf1e8..1a4ecfdd54 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fc1601" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 060fc40bb6..034e166ca1 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" register "gen1_dec" = "0x00fc1601" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59dfca3..aff01302b2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0a01" register "gen3_dec" = "0x00000000" register "gen4_dec" = "0x00000000" - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 29f6881fc2..4be91522d2 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; - int p_cnt_throttling_supported; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8794602978..bd3c993912 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; fadt->flush_stride = 16; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { - fadt->duty_width = 3; - } else { - fadt->duty_width = 0; - } + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa1ca92d78..c7464a05f1 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -680,12 +680,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; fadt->flush_stride = 16; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { - fadt->duty_width = 3; - } else { - fadt->duty_width = 0; - } + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; |