diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 34 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 16 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 40 |
3 files changed, 57 insertions, 33 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index eaaef07d56..ae85b91315 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <device/pci_ids.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -20,14 +21,37 @@ /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { - ADL_P_POWER_LIMITS_282_CORE, - ADL_P_POWER_LIMITS_482_CORE, - ADL_P_POWER_LIMITS_682_CORE, - ADL_M_POWER_LIMITS_282_CORE, - ADL_M_POWER_LIMITS_242_CORE, + ADL_P_282_CORE, + ADL_P_482_CORE, + ADL_P_682_28W_CORE, + ADL_P_682_45W_CORE, + ADL_M_282_CORE, + ADL_M_242_CORE, ADL_POWER_LIMITS_COUNT }; +/* TDP values for different SKUs */ +enum soc_intel_alderlake_cpu_tdps { + TDP_9W = 9, + TDP_15W = 15, + TDP_28W = 28, + TDP_45W = 45 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int cpu_id; + enum soc_intel_alderlake_power_limits limits; + enum soc_intel_alderlake_cpu_tdps cpu_tdp; +} cpuid_to_adl[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_CORE, TDP_15W }, + { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, +}; + /* Types of display ports */ enum ddi_ports { DDI_PORT_A, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index eff64f17d4..c89fe6ae06 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,30 +2,36 @@ chip soc/intel/alderlake device cpu_cluster 0 on end - register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_P_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ + register "power_limits_config[ADL_P_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + .tdp_pl4 = 140, + }" + + register "power_limits_config[ADL_P_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, }" - register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_M_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 45, }" - register "power_limits_config[ADL_M_POWER_LIMITS_242_CORE]" = "{ + register "power_limits_config[ADL_M_242_CORE]" = "{ .tdp_pl1_override = 9, .tdp_pl2_override = 30, .tdp_pl4 = 68, diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index cfb6f798b4..6bd02ee02b 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <delay.h> #include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> @@ -56,6 +55,8 @@ void soc_systemagent_init(struct device *dev) struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + u8 tdp; + size_t i; config_t *config; /* Enable Power Aware Interrupt Routing */ @@ -72,31 +73,24 @@ void soc_systemagent_init(struct device *dev) sa = pcidev_path_on_root(SA_DEVFN_ROOT); sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; - /* Choose a power limits configuration based on the SoC SKU type, - * differentiated here based on SA PCI ID. */ - switch (sa_pci_id) { - case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_282_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_482_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: - soc_config = &config->power_limits_config[ADL_P_POWER_LIMITS_682_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: - soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_282_CORE]; - break; - case PCI_DEVICE_ID_INTEL_ADL_M_ID_2: - soc_config = &config->power_limits_config[ADL_M_POWER_LIMITS_242_CORE]; - break; - default: - printk(BIOS_ERR, "ADL: unknown SA ID: 0x%4x, skipping power limits configuration\n", + tdp = get_cpu_tdp(); + + /* Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_adl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_adl)) { + printk(BIOS_ERR, "ERROR: unknown SA ID: 0x%4x, skipped power limits configuration.\n", sa_pci_id); return; } - - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |