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-rw-r--r--src/mainboard/apple/macbook21/devicetree.cb2
-rw-r--r--src/mainboard/getac/p470/devicetree.cb2
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb2
-rw-r--r--src/mainboard/ibase/mb899/devicetree.cb2
-rw-r--r--src/mainboard/intel/d945gclf/devicetree.cb2
-rw-r--r--src/mainboard/kontron/986lcd-m/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/t60/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/x60/devicetree.cb2
-rw-r--r--src/mainboard/roda/rk886ex/devicetree.cb2
-rw-r--r--src/northbridge/intel/i945/chip.h1
-rw-r--r--src/northbridge/intel/i945/raminit.c21
11 files changed, 37 insertions, 3 deletions
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index 4bbe28db1b..f37e768b76 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x8086 0x7270
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 4771a3ac0f..415d9a3945 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -25,6 +25,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index 655065a2d9..acf743b18c 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -25,6 +25,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on # host bridge
subsystemid 0x1458 0x5000
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 77ceaddc52..c63e5d645f 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -9,6 +9,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index aa8c441664..e8c2792420 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -21,6 +21,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
subsystemid 0x8086 0x464c inherit
device pci 00.0 on end # host bridge
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index 6795cdc38e..c768b64f4c 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -9,6 +9,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 2dc9f4535d..f66455bcce 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2015
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index e2a24c1232..0ac92737c2 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -30,6 +30,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2017
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 15c0fd0ea5..28f8f434c1 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -25,6 +25,8 @@ chip northbridge/intel/i945
end
end
+ register "pci_mmio_size" = "768"
+
device domain 0 on
subsystemid 0x4352 0x6886 inherit
device pci 00.0 on end # host bridge
diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h
index 446af72e4d..8eaa5b4a40 100644
--- a/src/northbridge/intel/i945/chip.h
+++ b/src/northbridge/intel/i945/chip.h
@@ -8,6 +8,7 @@ struct northbridge_intel_i945_config {
u32 gpu_backlight;
int gpu_lvds_use_spread_spectrum_clock;
struct i915_gpu_controller_info gfx;
+ int pci_mmio_size;
};
#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index ca800f7bf6..a4a1eaf0ca 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -16,6 +16,8 @@
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <device/pci_def.h>
+#include <device/device.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
#include <spd.h>
@@ -25,6 +27,7 @@
#include <lib.h>
#include "raminit.h"
#include "i945.h"
+#include "chip.h"
#include <cbmem.h>
/* Debugging macros. */
@@ -48,6 +51,7 @@
#define RAM_EMRS_2 (0x1 << 21)
#define RAM_EMRS_3 (0x2 << 21)
+#define DEFAULT_PCI_MMIO_SIZE 768
static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
{
if (sysinfo->spd_addresses)
@@ -1495,7 +1499,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
static int sdram_program_row_boundaries(struct sys_info *sysinfo)
{
int i;
- int cum0, cum1, tolud, tom;
+ int cum0, cum1, tolud, tom, pci_mmio_size;
+ const struct device *dev;
+ const struct northbridge_intel_i945_config *cfg = NULL;
printk(BIOS_DEBUG, "Setting RAM size...\n");
@@ -1534,8 +1540,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
tom = tolud >> 3;
/* Limit the value of TOLUD to leave some space for PCI memory. */
- if (tolud > 0xd0)
- tolud = 0xd0; /* 3.25GB : 0.75GB */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev)
+ cfg = dev->chip_info;
+
+ /* Don't use pci mmio sizes smaller than 768M */
+ if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE)
+ pci_mmio_size = DEFAULT_PCI_MMIO_SIZE;
+ else
+ pci_mmio_size = cfg->pci_mmio_size;
+
+ tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud);
pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 21:38:38 +0000