summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/x220/variants/x1/overridetree.cb1
-rw-r--r--src/mainboard/lenovo/x220/variants/x220/overridetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
index 68a70f08ce..d2361396f2 100644
--- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
@@ -26,6 +26,7 @@ chip northbridge/intel/sandybridge
device pci 1c.3 off end # PCIe Port #4
device pci 1f.0 on #LPC bridge
chip ec/lenovo/h8
+ device pnp ff.2 on end # dummy
register "config2" = "0xe0"
register "config3" = "0xc0"
diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
index 604eadf2a9..8e939fd14c 100644
--- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
@@ -3,6 +3,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1f.0 on #LPC bridge
chip ec/lenovo/h8
+ device pnp ff.2 on end # dummy
register "eventa_enable" = "0x01"
register "eventb_enable" = "0xf0"
end