diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e3222be02e..f14adbdc83 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -673,6 +673,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); if (rp_cfg->pcie_rp_aspm) s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); + /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ + if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) + s_cfg->PcieRpSlotImplemented[i] = 0; + s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; } } diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 66ced7ee46..9832feb83f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -27,6 +27,8 @@ enum pcie_rp_flags { PCIE_RP_CLK_REQ_DETECT = (1 << 4), /* Clock request signal is not used by the root port. */ PCIE_RP_CLK_REQ_UNUSED = (1 << 5), + /* indicates that this root port is built-in. */ + PCIE_RP_BUILT_IN = (1 << 6), }; enum pcie_clk_src_flags { @@ -63,6 +65,8 @@ struct pcie_rp_config { enum L1_substates_control PcieRpL1Substates; /* PCIe RP ASPM */ enum ASPM_control pcie_rp_aspm; + /* timeout for device detect */ + uint32_t pcie_rp_detect_timeout_ms; }; /* |