diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/superio/ite/common/early_serial.c | 27 | ||||
| -rw-r--r-- | src/superio/ite/common/ite.h | 1 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index d19548ebca..48e414b0da 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -95,6 +95,33 @@ void ite_enable_3vsbsw(pnp_devfn_t dev) } /* + * + * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge + * This can be needed for S3 resume. + * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked + * as reserved. + * + * Delay PWRGD3 assertion after setting 3VSBSW#. + * 0: There will be no extra delay before PWRGD3 is set. + * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased. + * + * in romstage.c + * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: GPIO_DEV + */ + +void ite_delay_pwrgd3(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); + tmp |= 0x01; + pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); + pnp_exit_conf_state(dev); +} + +/* * in romstage.c * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) * and pass: GPIO_DEV diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index a0c20ff8e1..3e9b50289a 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -15,6 +15,7 @@ void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); |