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-rw-r--r--src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 168c95a5d9..dc61cbac67 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -146,6 +146,13 @@ enum {
CLK_ENB_CSITE = 0x1 << 9
};
+static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr =
+ (void *)(CLK_RST_BASE + 0x388);
+enum {
+ CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0,
+ CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT
+};
+
static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440);
enum {
CLK_ENB_CPUG = 0x1 << 0,
@@ -787,6 +794,9 @@ void lp0_resume(void)
/* Disable PLLX since it isn't used in the kernel as CPU clk source. */
clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
+ /* Set CAR2PMC_CPU_ACK_WIDTH to 0 */
+ clrbits32(CAR2PMC_CPU_ACK_WIDTH_MASK, clk_rst_cpu_softrst_ctrl2_ptr);
+
/* Clear PMC_SCRATCH190 */
clrbits32(1, pmc_scratch190_ptr);