diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_acpi.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_nic.c | 6 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index f318b37621..67a789c08a 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -73,12 +73,12 @@ unsigned pm_base; static void acpi_init(struct device *dev) { uint8_t byte; - uint16_t word; uint16_t pm10_bar; uint32_t dword; int on; #if 0 + uint16_t word; printk_debug("ACPI: disabling NMI watchdog.. "); byte = pci_read_config8(dev, 0x49); pci_write_config8(dev, 0x49, byte | (1<<2)); @@ -98,9 +98,8 @@ static void acpi_init(struct device *dev) word = pci_read_config16(dev, 0x46); pci_write_config16(dev, 0x46, word | (1<<9)); printk_debug("done.\n"); - - #endif + /* To enable the register 0xcf9 in the IO space * bit [D5] is set in the amd8111 configuration register. * The config. reg. is devBx41. Register 0xcf9 allows diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index 98ac62b5d7..aa06253a46 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -54,12 +54,12 @@ static void nic_init(struct device *dev) /* Hard Reset PHY */ printk_debug("Reseting PHY... "); if (conf->phy_lowreset) { - write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); + write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { - write32((void *)(mmio + CMD3), VAL0 | RESET_PHY); + write32((mmio + CMD3), VAL0 | RESET_PHY); } mdelay(15); - write32((void *)(mmio + CMD3), RESET_PHY); + write32((mmio + CMD3), RESET_PHY); printk_debug("Done\n"); } |