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-rw-r--r--src/southbridge/amd/agesa/hudson/acpi/fch.asl2
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/fch.asl2
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/fch.asl2
-rw-r--r--src/southbridge/intel/bd82x6x/azalia.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/i82371eb/acpi_tables.c2
-rw-r--r--src/southbridge/intel/i82371eb/smbus.c2
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801gx/azalia.c2
-rw-r--r--src/southbridge/intel/i82801ix/azalia.c2
-rw-r--r--src/southbridge/intel/i82801jx/azalia.c2
-rw-r--r--src/southbridge/intel/ibexpeak/azalia.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/me_status.c2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h2
16 files changed, 16 insertions, 16 deletions
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
index 38f2bca6da..b87b9e4946 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
@@ -67,7 +67,7 @@ Name(CRES, ResourceTemplate() {
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
+ * PCI buses can have 256 secondary buses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/
diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 2059db0594..88fbf7b48c 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -77,7 +77,7 @@ Name(CRES, ResourceTemplate() {
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
+ * PCI buses can have 256 secondary buses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 88cf47f7ef..9a2c7445db 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -50,7 +50,7 @@ Name(CRES, ResourceTemplate() {
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
+ * PCI buses can have 256 secondary buses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 1f14c422a8..3b07a15298 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b4f0c4c5fc..dfebaf0dac 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -31,7 +31,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 7507cd5d5d..41fc4eeaa1 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -29,7 +29,7 @@ void generate_cpu_entries(const struct device *device)
int numcpus = determine_total_number_of_cores();
printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
- /* without the outer scope, furhter ssdt addition will end up
+ /* without the outer scope, further ssdt addition will end up
* within the processor statement */
acpigen_write_scope("\\_SB");
for (cpu=0; cpu < numcpus; cpu++) {
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 988d7418d3..5b9f8be30e 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -27,7 +27,7 @@ static void pwrmgt_enable(struct device *dev)
* bit25 (lid_pol): 1=invert lid polarity
* bit24 (sm_freeze): 1=freeze idle and standby timers
* bit16 (end of smi): 0=disable smi assertion (cleared by hw)
- * bits8-15,26: global standby timer inital count 127 * 4minutes
+ * bits8-15,26: global standby timer initial count 127 * 4minutes
* bit2 (thrm_pol): 1=active low THRM#
* bit0 (smi_en): 1=disable smi generation upon smi event
*/
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 6ff606422b..321c605366 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -32,7 +32,7 @@ static void i82801dx_enable_acpi(struct device *dev)
}
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index fde06b4aac..0473de64de 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -190,7 +190,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base);
diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c
index ff890a265f..90d784cd65 100644
--- a/src/southbridge/intel/i82801ix/azalia.c
+++ b/src/southbridge/intel/i82801ix/azalia.c
@@ -183,7 +183,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c
index 5efbc9f601..885c332f8f 100644
--- a/src/southbridge/intel/i82801jx/azalia.c
+++ b/src/southbridge/intel/i82801jx/azalia.c
@@ -183,7 +183,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index ef781b7174..683715fd6b 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 8cc9b42c17..c14c6a28b1 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_ibexpeak_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f3c08d885f..d0eb4b33f0 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -25,7 +25,7 @@
#define NMI_OFF 0
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c
index 82a8f8ed0a..fb4490f867 100644
--- a/src/southbridge/intel/lynxpoint/me_status.c
+++ b/src/southbridge/intel/lynxpoint/me_status.c
@@ -187,7 +187,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2)
break;
default:
- printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x",
+ printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
hfs2->progress_code, hfs2->current_state);
}
printk(BIOS_DEBUG, "\n");
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 598c2dc7b2..7d9fc6d6af 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -647,7 +647,7 @@ void mainboard_config_rcba(void);
#define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET)
#define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
-/* Reigsters within the SPIBAR */
+/* Registers within the SPIBAR */
#define SSFC 0x91
#define FDOC 0xb0
#define FDOD 0xb4
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 19:04:21 +0000