2 files changed, 1 insertions, 21 deletions
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 5bea98c6bd..840aeb42dc 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -6,6 +6,7 @@ config SOUTHBRIDGE_INTEL_I82801DX
 	select IOAPIC
 	select HAVE_SMI_HANDLER
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_RTC
 	select SOUTHBRIDGE_INTEL_COMMON_RESET
 	select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index fc225b0466..76ef1b8a15 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
 #include <device/smbus_host.h>
 #include "i82801dx.h"
 
@@ -9,22 +7,3 @@ void i82801dx_early_init(void)
 {
 	enable_smbus();
 }
-
-uintptr_t smbus_base(void)
-{
-	return CONFIG_FIXED_SMBUS_IO_BASE;
-}
-
-int smbus_enable_iobar(uintptr_t base)
-{
-	pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	/* set smbus iobase */
-	pci_write_config32(dev, 0x20, base | 1);
-	/* Set smbus enable */
-	pci_write_config8(dev, 0x40, 0x01);
-	/* Set smbus iospace enable */
-	pci_write_config16(dev, 0x4, 0x01);
-
-	return 0;
-}