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-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup.c6
-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup_car.c12
-rw-r--r--src/southbridge/nvidia/ck804/ck804_lpc.c3
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c14
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_lpc.c3
5 files changed, 20 insertions, 18 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index 6634161362..bbce8207de 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -102,7 +102,7 @@ static void ck804_early_set_port(void)
#endif
};
- setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]));
+ setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
}
@@ -121,7 +121,7 @@ static void ck804_early_clear_port(void)
#endif
};
- setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]));
+ setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
}
@@ -324,7 +324,7 @@ static void ck804_early_setup(void)
- setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0]));
+ setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
index 729a47f178..ec18ffc8b6 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
@@ -105,12 +105,12 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *i
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf,
- sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+ ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_b,
- sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
+ ARRAY_SIZE(ctrl_devport_conf_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
}
@@ -132,12 +132,12 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
- sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_clear_b,
- sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
@@ -327,13 +327,13 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_b
for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
+ setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
PCI_DEV(busn[0],0,0), io_base[0]);
continue;
}
- setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
+ setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
PCI_DEV(busn[j],0,0), io_base[j]);
}
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index 69afb182ae..b06de3e558 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -15,6 +15,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "ck804.h"
#define CK804_CHIP_REV 2
@@ -82,7 +83,7 @@ static void setup_ioapic(unsigned long ioapic_base)
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index 48218558ee..64ec785781 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -106,7 +106,7 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *d
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf,
- sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
+ ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
}
@@ -123,7 +123,7 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf_clear,
- sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
+ ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
@@ -327,23 +327,23 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
for(j=0; j<mcp55_num; j++) {
mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
- setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
+ setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
for(i=0; i<3; i++) { // three SATA
- setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
+ setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
PCI_DEV(busn[j], devn[j], i), io_base[j]);
}
if(busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
+ setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
if( (busn[j] == 0) && (mcp55_num>1) ) {
- setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
+ setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
- setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
+ setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index f4df404e13..3cfcd57a71 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -34,6 +34,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
@@ -106,7 +107,7 @@ static void setup_ioapic(unsigned long ioapic_base, int master)
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
+ for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 14:59:33 +0000