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-rw-r--r--src/southbridge/nvidia/ck804/ck804_fadt.c2
-rw-r--r--src/southbridge/nvidia/ck804/ck804_ide.c4
-rw-r--r--src/southbridge/nvidia/ck804/ck804_lpc.c10
-rw-r--r--src/southbridge/nvidia/ck804/ck804_pci.c6
-rw-r--r--src/southbridge/nvidia/ck804/ck804_sata.c14
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_aza.c14
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_fadt.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_ide.c4
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_lpc.c8
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_nic.c4
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_pci.c6
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_sata.c6
13 files changed, 41 insertions, 41 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_fadt.c b/src/southbridge/nvidia/ck804/ck804_fadt.c
index 1bfc22d915..205f1f0550 100644
--- a/src/southbridge/nvidia/ck804/ck804_fadt.c
+++ b/src/southbridge/nvidia/ck804/ck804_fadt.c
@@ -13,7 +13,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- printk_debug("pm_base: 0x%04x\n", pm_base);
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ck804_ide.c
index df4659c228..f46a057ef7 100644
--- a/src/southbridge/nvidia/ck804/ck804_ide.c
+++ b/src/southbridge/nvidia/ck804/ck804_ide.c
@@ -25,12 +25,12 @@ static void ide_init(struct device *dev)
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
- printk_debug("IDE1 \t");
+ printk(BIOS_DEBUG, "IDE1 \t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */
word |= (1 << 1);
- printk_debug("IDE0\n");
+ printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1 << 12);
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index 2b840fcbdd..d68a5b1077 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -95,7 +95,7 @@ static void enable_hpet(struct device *dev)
pci_write_config32(dev, 0x44, 0xfed00001);
hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
- printk_debug("Enabling HPET @0x%lx\n", hpet_address);
+ printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
}
unsigned pm_base=0;
@@ -108,7 +108,7 @@ static void lpc_init(device_t dev)
lpc_common_init(dev);
pm_base = pci_read_config32(dev, 0x60) & 0xff00;
- printk_info("%s: pm_base = %x \n", __func__, pm_base);
+ printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
#if CK804_CHIP_REV==1
if (dev->bus->secondary != 1)
@@ -129,7 +129,7 @@ static void lpc_init(device_t dev)
if (!on)
byte |= 0x40;
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
- printk_info("set power %s after power fail\n", on ? "on" : "off");
+ printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
/* Throttle the CPU speed down for testing. */
on = SLOW_CPU_OFF;
@@ -141,7 +141,7 @@ static void lpc_init(device_t dev)
outl(((on << 1) + 0x10), (pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8 - on;
- printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+ printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on * 12) + (on >> 1), (on & 1) * 5);
}
#if 0
@@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
continue;
base = res->base;
end = resource_end(res);
- printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
+ printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
switch (base) {
case 0x3f8: // COM1
reg |= (1 << 0);
diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c
index 70ccdc6329..ccbbbd48a9 100644
--- a/src/southbridge/nvidia/ck804/ck804_pci.c
+++ b/src/southbridge/nvidia/ck804/ck804_pci.c
@@ -53,13 +53,13 @@ static void pci_init(struct device *dev)
if (!pref || pref->base > mem->base) {
dword = mem->base & (0xffff0000UL);
- printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
+ printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
} else {
dword = pref->base & (0xffff0000UL);
- printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
+ printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
}
- printk_debug("[0x50] <-- 0x%08x\n", dword);
+ printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); /* TOM */
}
diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c
index e9218abf3a..8eed906ce8 100644
--- a/src/southbridge/nvidia/ck804/ck804_sata.c
+++ b/src/southbridge/nvidia/ck804/ck804_sata.c
@@ -26,7 +26,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
base = (uint32_t *) pci_read_config32(dev, 0x24);
- printk_debug("base = %08lx\n", base);
+ printk(BIOS_DEBUG, "base = %08lx\n", base);
if (reset) {
*(base + 4) = 0xffffffff;
@@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
return;
dword = *(base + 0);
- printk_debug("*(base+0)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword);
if (dword == 0x113) {
loop = 200000; // 2
do {
@@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset)
break;
udelay(10);
} while (--loop > 0);
- printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword);
}
dword = *(base + 0x40);
- printk_debug("*(base+0x40)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword);
if (dword == 0x113) {
loop = 200000; //2
do {
@@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
break;
udelay(10);
} while (--loop > 0);
- printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
}
}
#endif
@@ -91,12 +91,12 @@ static void sata_init(struct device *dev)
if (conf->sata1_enable) {
/* Enable secondary SATA interface. */
dword |= (1 << 0);
- printk_debug("SATA S \t");
+ printk(BIOS_DEBUG, "SATA S \t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface. */
dword |= (1 << 1);
- printk_debug("SATA P \n");
+ printk(BIOS_DEBUG, "SATA P \n");
}
#if 0
/* Write back */
diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c
index 4c07a60162..aa86cf3bc7 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.c
+++ b/src/southbridge/nvidia/mcp55/mcp55.c
@@ -218,7 +218,7 @@ void mcp55_enable(device_t dev)
// reg |= (1<<0);
reg &= ~(0x3f<<4);
if (reg != reg_old) {
- printk_debug("mcp55.c pcie enabled\n");
+ printk(BIOS_DEBUG, "mcp55.c pcie enabled\n");
pci_write_config32(sm_dev, 0xe4, reg);
}
#endif
diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c
index b86530b7af..cea0b49e8c 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_aza.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c
@@ -80,7 +80,7 @@ static int codec_detect(uint8_t *base)
/* 6 */
if(!dword) {
set_bits(base + 0x08, 1, 0);
- printk_debug("No codec!\n");
+ printk(BIOS_DEBUG, "No codec!\n");
return 0;
}
return dword;
@@ -186,15 +186,15 @@ static void codec_init(uint8_t *base, int addr)
dword = read32(base + 0x64);
/* 2 */
- printk_debug("codec viddid: %08x\n", dword);
+ printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
verb_size = find_verb(dword, &verb);
if(!verb_size) {
- printk_debug("No verb!\n");
+ printk(BIOS_DEBUG, "No verb!\n");
return;
}
- printk_debug("verb_size: %d\n", verb_size);
+ printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
/* 3 */
for(i=0; i<verb_size; i++) {
do {
@@ -207,7 +207,7 @@ static void codec_init(uint8_t *base, int addr)
dword = read32(base + 0x68);
} while ((dword & 3) != 2);
}
- printk_debug("verb loaded!\n");
+ printk(BIOS_DEBUG, "verb loaded!\n");
}
static void codecs_init(uint8_t *base, uint32_t codec_mask)
@@ -230,12 +230,12 @@ static void aza_init(struct device *dev)
return;
base =(uint8_t *) res->base;
- printk_debug("base = %08x\n", base);
+ printk(BIOS_DEBUG, "base = %08x\n", base);
codec_mask = codec_detect(base);
if(codec_mask) {
- printk_debug("codec_mask = %02x\n", codec_mask);
+ printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
index 212cbe6f3a..7c7ad6954c 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
@@ -49,7 +49,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 42;
- printk_info("ACPI: pm_base: %u...\n", pm_base);
+ printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base);
fadt->firmware_ctrl = facs;
fadt->dsdt = dsdt;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_ide.c b/src/southbridge/nvidia/mcp55/mcp55_ide.c
index e62a5477d9..fac5997513 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_ide.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_ide.c
@@ -43,12 +43,12 @@ static void ide_init(struct device *dev)
if (conf->ide1_enable) {
/* Enable secondary ide interface */
word |= (1<<0);
- printk_debug("IDE1 \t");
+ printk(BIOS_DEBUG, "IDE1 \t");
}
if (conf->ide0_enable) {
/* Enable primary ide interface */
word |= (1<<1);
- printk_debug("IDE0\n");
+ printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1<<12);
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index c247d98be1..869e8392e2 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -80,7 +80,7 @@ static void enable_hpet(struct device *dev)
pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
- printk_debug("enabling HPET @0x%x\n", hpet_address);
+ printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
}
static void lpc_init(device_t dev)
@@ -108,7 +108,7 @@ static void lpc_init(device_t dev)
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
- printk_info("set power %s after power fail\n", on?"on":"off");
+ printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
#endif
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
@@ -120,7 +120,7 @@ static void lpc_init(device_t dev)
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
- printk_debug("Throttling CPU %2d.%1.1d percent.\n",
+ printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on*12)+(on>>1),(on&1)*5);
}
@@ -224,7 +224,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
- printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
+ printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
switch(base) {
case 0x3f8: // COM1
reg |= (1<<0); break;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_nic.c b/src/southbridge/nvidia/mcp55/mcp55_nic.c
index d3b92b97bb..92ea633a20 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_nic.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_nic.c
@@ -83,13 +83,13 @@ static void phy_detect(uint8_t *base)
val = phy_read(base, phyaddr, 2);
if (val < 0 || val == 0xffff) continue;
id |= ((val & 0xffff)<<16);
- printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
+ printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
// if((id == 0xe0180000) || (id==0x0032cc00))
break;
}
if(i>32) {
- printk_debug("MCP55 MAC PHY not found\n");
+ printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n");
}
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_pci.c b/src/southbridge/nvidia/mcp55/mcp55_pci.c
index 3bc3a1ab18..02b0124884 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_pci.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_pci.c
@@ -75,13 +75,13 @@ static void pci_init(struct device *dev)
if (!pref || pref->base > mem->base) {
dword = mem->base & (0xffff0000UL);
- printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
+ printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
} else {
dword = pref->base & (0xffff0000UL);
- printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
+ printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
}
- printk_debug("[0x50] <-- 0x%08x\n", dword);
+ printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); /* TOM */
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_sata.c b/src/southbridge/nvidia/mcp55/mcp55_sata.c
index 1b40aa0983..8df5f6bcbd 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_sata.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_sata.c
@@ -43,16 +43,16 @@ static void sata_init(struct device *dev)
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
- printk_debug("SATA S \t");
+ printk(BIOS_DEBUG, "SATA S \t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
- printk_debug("SATA P \n");
+ printk(BIOS_DEBUG, "SATA P \n");
}
} else {
dword |= (1<<1) | (1<<0);
- printk_debug("SATA P and S \n");
+ printk(BIOS_DEBUG, "SATA P and S \n");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 19:29:45 +0000