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-rw-r--r--src/southbridge/intel/i82371eb/Makefile.inc3
-rw-r--r--src/southbridge/intel/i82371eb/acpi/isabridge.asl94
-rw-r--r--src/southbridge/intel/i82371eb/acpi/pirq.asl79
-rw-r--r--src/southbridge/intel/i82371eb/acpi_tables.c137
-rw-r--r--src/southbridge/intel/i82371eb/chip.h4
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h51
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_early_pm.c2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_early_smbus.c2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_fadt.c222
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_isa.c15
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_smbus.c92
11 files changed, 690 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 816ef1bcc3..b5ac581ff1 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -24,7 +24,8 @@ driver-y += i82371eb_ide.c
driver-y += i82371eb_usb.c
driver-y += i82371eb_smbus.c
driver-y += i82371eb_reset.c
+driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
+driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
romstage-y += i82371eb_early_pm.c
romstage-y += i82371eb_early_smbus.c
-
diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl
new file mode 100644
index 0000000000..9640a523d1
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+// Intel LPC Bus Device - 0:4.0
+Device (LPCB)
+{
+ Name(_ADR, 0x00040000)
+
+ OperationRegion(PCIC, PCI_Config, 0x00, 0x100)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+}
+
+Device(MBRS) {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+
+ External(_CRS) /* Resource Template in SSDT */
+}
diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl
new file mode 100644
index 0000000000..8b25fd8069
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve)
+{
+ Offset (0x60), // Interrupt Routing Registers
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+}
+
+Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+})
+
+Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
+})
+
+/* adapted from ma78gm/dsdt.asl */
+#define PCI_INTX_DEV(intx, pinx, uid) \
+Device(intx) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ \
+ Method(_STA, 0) { \
+ If (And(pinx, 0x80)) { \
+ Return(0x09) \
+ } \
+ Return(0x0B) \
+ } \
+ \
+ Method(_DIS ,0) { \
+ Store(0x80, pinx) \
+ } \
+ \
+ Method(_PRS ,0) { \
+ Return(IRQP) \
+ } \
+ \
+ Method(_CRS ,0) { \
+ CreateWordField(IRQB, 1, IRQN) \
+ ShiftLeft(1, And(pinx, 0x0f), IRQN) \
+ Return(IRQB) \
+ } \
+ \
+ Method(_SRS, 1) { \
+ CreateWordField(ARG0, 1, IRQM) \
+ \
+ /* Use lowest available IRQ */ \
+ FindSetRightBit(IRQM, Local0) \
+ if (Local0) { \
+ Decrement(Local0) \
+ } \
+ Store(Local0, pinx) \
+ } \
+} \
+
+PCI_INTX_DEV(LNKA, PRTA, 1)
+PCI_INTX_DEV(LNKB, PRTB, 2)
+PCI_INTX_DEV(LNKC, PRTC, 3)
+PCI_INTX_DEV(LNKD, PRTD, 4)
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
new file mode 100644
index 0000000000..2b536e6f18
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+
+extern const unsigned char AmlCode[];
+
+unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long __attribute__((weak)) acpi_fill_srat(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long __attribute__((weak)) acpi_fill_madt(unsigned long current)
+{
+ /* mainboard has no ioapic */
+ return current;
+}
+
+unsigned long __attribute__((weak)) acpi_fill_mcfg(unsigned long current)
+{
+ /* chipset doesn't have mmconfig */
+ return current;
+}
+
+unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+ return (unsigned long) acpigen_get_current();
+}
+
+unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_madt_t *madt;
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ /* Align ACPI tables to 16 byte. */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT table. */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* Clear all table memory. */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* We explicitly add these tables later on: */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+
+ /* we should align FACS to 64B as per ACPI specs */
+ current = ALIGN(current, 64);
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ /* Don't trust iasl to get checksum right. */
+ dsdt->checksum = 0; /* needs to be set to 0 first (part of csum) */
+ dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ if (madt->header.length > sizeof(acpi_madt_t)) {
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+ } else {
+ /* don't add empty madt */
+ current = (unsigned long)madt;
+ }
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "DYNADATA");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 2be0f4ffdf..1cb2929346 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -34,6 +34,10 @@ struct southbridge_intel_i82371eb_config {
int ide1_drive1_udma33_enable:1;
int ide_legacy_enable:1;
int usb_enable:1;
+ /* acpi */
+ u32 gpo; /* gpio output default */
+ u8 lid_polarity;
+ u8 thrm_polarity;
};
#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 0536c54541..a77a8e68aa 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -56,14 +56,61 @@ void i82371eb_hard_reset(void);
/* SMBus */
#define SMBBA 0x90 /* SMBus base address */
+#define SMBUS_IO_BASE 0x0f00
#define SMBHSTCFG 0xd2 /* SMBus host configuration */
/* Power management (ACPI) */
+#define PMSTS 0x00 /* Power Management Status */
+#define PMEN 0x02 /* Power Management Resume Enable */
+#define PWRBTN_EN (1<<8)
+#define GBL_EN (1<<5)
+#define PMCNTRL 0x04 /* Power Management Control */
+#define SUS_EN (1<<13) /* S0-S5 trigger */
+#define SUS_TYP_MSK (7<<10)
+#define SUS_TYP_S0 (5<<10)
+#define SUS_TYP_S1 (4<<10)
+#define SUS_TYP_S2 (3<<10)
+//#define SUS_TYP_S2>---(2<<10)
+#define SUS_TYP_S3 (1<<10)
+#define SUS_TYP_S5 (0<<10)
+#define SCI_EN (1<<0)
+#define PMTMR 0x08 /* Power Management Timer */
+#define GPSTS 0x0c /* General Purpose Status */
+#define GPEN 0x0e /* General Purpose Enable */
+#define THRM_EN (1<<0)
+#define PCNTRL 0x10 /* Processor control */
+#define GLBSTS 0x18 /* Global Status */
+#define IRQ_RSM_STS (1<<11)
+#define EXTSMI_STS (1<<10)
+#define GSTBY_STS (1<<8)
+#define GP_STS (1<<7)
+#define BM1_STS (1<<6)
+#define APM_STS (1<<5)
+#define DEV_STS (1<<4)
+#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */
+#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */
+#define DEVSTS 0x1c /* Device Status */
+#define GLBEN 0x20 /* Global Enable */
+#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */
+#define GSTBY_EN (1<<8)
+#define BM_TRP_EN (1<<1)
+#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */
+#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */
+#define GLBCTL 0x28 /* Global Control */
+#define EOS (1<<16) /* End of SMI */
+#define SMI_EN (1<<0) /* SMI enable */
+#define DEVCTL 0x2c /* Device Control */
+#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */
+#define GPO0 0x34
+#define GPO1 0x35
+#define GPO2 0x36
+#define GPO3 0x37
+
#define PMBA 0x40 /* Power management base address */
+#define DEFAULT_PMBASE 0xe400
+#define PM_IO_BASE DEFAULT_PMBASE
#define PMREGMISC 0x80 /* Miscellaneous power management */
-#define PM_IO_BASE 0xe400
-
/* Bit definitions */
#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
index ad5fe7cfd8..66c2712b7b 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
@@ -39,7 +39,7 @@ void enable_pm(void)
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the PM I/O base. */
- pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
+ pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
/* Enable access to the PM I/O space. */
reg16 = pci_read_config16(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 0ae5667e86..b7c79075eb 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -27,8 +27,6 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
-#define SMBUS_IO_BASE 0x0f00
-
int smbus_read_byte(u8 device, u8 address);
void enable_smbus(void)
diff --git a/src/southbridge/intel/i82371eb/i82371eb_fadt.c b/src/southbridge/intel/i82371eb/i82371eb_fadt.c
new file mode 100644
index 0000000000..5891440d2e
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_fadt.c
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ * Reference: ACPIspec40a, 5.2.9, page 118
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ device_t dev;
+
+ /* Power management controller */
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 42;
+
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+ fadt->preferred_pm_profile = 0; /* unspecified */
+ fadt->sci_int = 9;
+ fadt->smi_cmd = 0; /* smi command port */
+ fadt->acpi_enable = 0; /* acpi enable smi command */
+ fadt->acpi_disable = 0; /* acpi disable smi command */
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0x0;
+
+ fadt->pm1a_evt_blk = DEFAULT_PMBASE;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
+ fadt->pm1b_cnt_blk = 0x0;
+
+ fadt->pm2_cnt_blk = 0;
+ fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
+ fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
+ fadt->gpe1_blk = 0x0;
+ fadt->gpe1_base = 0;
+ fadt->gpe1_blk_len = 0;
+
+ /* *_len define register width in bytes */
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0; /* not supported */
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+
+ fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
+ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
+ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
+ fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
+ fadt->duty_width = 3; /* this width is in bits */
+ fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+ fadt->mon_alrm = 0x0; /* not supported */
+ fadt->century = 0x0; /* not supported */
+ /*
+ * bit meaning
+ * 0 1: We have user-visible legacy devices
+ * 1 1: 8042
+ * 2 0: VGA is ok to probe
+ * 3 1: MSI are not supported
+ */
+ fadt->iapc_boot_arch = 0xb;
+ /*
+ * bit meaning
+ * 0 WBINVD
+ * Processors in new ACPI-compatible systems are required to
+ * support this function and indicate this to OSPM by setting
+ * this field.
+ * 1 WBINVD_FLUSH
+ * If set, indicates that the hardware flushes all caches on the
+ * WBINVD instruction and maintains memory coherency, but does
+ * not guarantee the caches are invalidated.
+ * 2 PROC_C1
+ * C1 power state (x86 hlt instruction) is supported on all cpus
+ * 3 P_LVL2_UP
+ * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
+ * 4 PWR_BUTTON
+ * 0: pwr button is fixed feature
+ * 1: pwr button has control method device if present
+ * 5 SLP_BUTTON
+ * 0: sleep button is fixed feature
+ * 1: sleep button has control method device if present
+ * 6 FIX_RTC
+ * 0: RTC wake status supported in fixed register spce
+ * 7 RTC_S4
+ * 1: RTC can wake from S4
+ * 8 TMR_VAL_EXT
+ * 1: pmtimer is 32bit, 0: pmtimer is 24bit
+ * 9 DCK_CAP
+ * 1: system supports docking station
+ * 10 RESET_REG_SUPPORT
+ * 1: fadt describes reset register for system reset
+ * 11 SEALED_CASE
+ * 1: No expansion possible, sealed case
+ * 12 HEADLESS
+ * 1: Video output, keyboard and mouse are not connected
+ * 13 CPU_SW_SLP
+ * 1: Special processor instruction needs to be executed
+ * after writing SLP_TYP
+ * 14 PCI_EXP_WAK
+ * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
+ * on platforms with pci express support
+ * 15 USE_PLATFORM_CLOCK
+ * 1: OS should prefer platform clock over processor internal
+ * clock.
+ * 16 S4_RTC_STS_VALID
+ * 17 REMOTE_POWER_ON_CAPABLE
+ * 1: platform correctly supports OSPM leaving GPE wake events
+ * armed prior to an S5 transition.
+ * 18 FORCE_APIC_CLUSTER_MODEL
+ * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE
+ */
+ fadt->flags = 0xa5;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+ fadt->reset_value = 0;
+
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index 21fd4db780..d025bf2393 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -67,6 +67,13 @@ static void isa_init(struct device *dev)
rtc_init(0);
/*
+ * Enable special cycles, needed for soft poweroff.
+ */
+ reg32 = pci_read_config16(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_SPECIAL;
+ pci_write_config16(dev, PCI_COMMAND, reg32);
+
+ /*
* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
* bus, which is a subset of ISA. We select the full ISA bus here.
*/
@@ -105,12 +112,16 @@ static void sb_read_resources(struct device *dev)
res = new_resource(dev, 2);
res->base = 0xff800000UL;
res->size = 0x00800000UL; /* 8 MB for flash */
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+#if CONFIG_IOAPIC
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+#endif
}
static const struct device_operations isa_ops = {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 3072b6c547..4dfd2f4caf 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -2,6 +2,9 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +21,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <console/console.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
@@ -26,17 +31,98 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
-/* TODO: Needed later? */
+static void pwrmgt_enable(struct device *dev)
+{
+ struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
+ u32 reg, gpo = sb->gpo;
+
+ /* Sets the base address of power management ports. */
+ pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1);
+
+ /* Set Power Management IO Space Enable bit */
+ u8 val = pci_read_config8(dev, PMREGMISC);
+ pci_write_config8(dev, PMREGMISC, val | 1);
+
+ /* set global control:
+ * bit25 (lid_pol): 1=invert lid polarity
+ * bit24 (sm_freeze): 1=freeze idle and standby timers
+ * bit16 (end of smi): 0=disable smi assertion (cleared by hw)
+ * bits8-15,26: global standby timer inital count 127 * 4minutes
+ * bit2 (thrm_pol): 1=active low THRM#
+ * bit0 (smi_en): 1=disable smi generation upon smi event
+ */
+ reg = (sb->lid_polarity<<25)|
+ (1<<24)|
+ (0xff<<8)|
+ (sb->thrm_polarity<<2);
+ outl(reg, DEFAULT_PMBASE + GLBCTL);
+
+ /* set processor control:
+ * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3
+ * bit11 (sleep_en): 1=enable slp# assertion on lvl3
+ * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs
+ */
+ outl(0, DEFAULT_PMBASE + PCNTRL);
+
+ /* disable smi event enables */
+ outw(0, DEFAULT_PMBASE + GLBEN);
+ outl(0, DEFAULT_PMBASE + DEVCTL);
+
+ /* set default gpo value.
+ * power-on default is 0x7fffbfffh */
+ if (gpo) {
+ /* only 8bit access allowed */
+ outb( gpo & 0xff, DEFAULT_PMBASE + GPO0);
+ outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1);
+ outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);
+ outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);
+ } else {
+ printk(BIOS_SPEW,
+ "%s: gpo default missing in devicetree.cb!\n", __func__);
+ }
+
+ /* Clear status events. */
+ outw(0xffff, DEFAULT_PMBASE + PMSTS);
+ outw(0xffff, DEFAULT_PMBASE + GPSTS);
+ outw(0xffff, DEFAULT_PMBASE + GLBSTS);
+ outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
+
+ /* set pmcntrl default */
+ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
+}
+
+static void pwrmgt_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ pci_dev_read_resources(dev);
+
+ res = new_resource(dev, 1);
+ res->base = DEFAULT_PMBASE;
+ res->size = 0x0040;
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+
+ res = new_resource(dev, 2);
+ res->base = SMBUS_IO_BASE;
+ res->size = 0x0010;
+ res->limit = 0xffff;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+ IORESOURCE_RESERVE;
+}
+
+
static const struct smbus_bus_operations lops_smbus_bus = {
};
static const struct device_operations smbus_ops = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = pwrmgt_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
- .enable = 0,
+ .enable = pwrmgt_enable,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
.ops_smbus_bus = &lops_smbus_bus,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 18:42:08 +0000