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-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c10
2 files changed, 5 insertions, 9 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3f37887567..be4285b1da 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -195,10 +195,6 @@ void mainboard_config_superio(void);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
/* Power Management Control and Status */
#define PCH_PCS 0x84
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index a3b2e096d8..1eb8e4bcc4 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@@ -684,11 +685,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);