summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/azalia.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 1f14c422a8..3b07a15298 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b4f0c4c5fc..dfebaf0dac 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -31,7 +31,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/