diff options
Diffstat (limited to 'src/southbridge/amd/rs780')
| -rw-r--r-- | src/southbridge/amd/rs780/cmn.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/early_setup.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.c | 2 |
4 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 3c79a81244..17ca98079a 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -342,7 +342,7 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port) void rs780_set_tom(struct device *nb_dev) { /* set TOM */ -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); #else diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index cccec44e56..6be6423266 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -105,7 +105,7 @@ static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, } } /* family 10 only, for reg > 0xFF */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -151,7 +151,7 @@ static u8 is_famly10(void) return (cpuid_eax(1) & 0xff00000) != 0; } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; @@ -231,7 +231,7 @@ void rs780_htinit(void) } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + #if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -271,7 +271,7 @@ void rs780_htinit(void) } } -#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if !CONFIG(NORTHBRIDGE_AMD_AMDFAM10) /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -327,7 +327,7 @@ static void k8_optimization(void) #define k8_optimization() do {} while (0) #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) static void fam10_optimization(void) { pci_devfn_t cpu_f0, cpu_f2, cpu_f3; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 8431223690..ca7414a9eb 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -380,7 +380,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* GFX_InitFBAccess finished. */ -#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */ +#if CONFIG(GFXUMA) /* for UMA mode. */ /* GFX_StartMC. */ set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); @@ -442,7 +442,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.sHeader.ucTableFormatRevision = 1; vgainfo.sHeader.ucTableContentRevision = 2; -#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */ +#if !CONFIG(GFXUMA) /* SP mode. */ // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; @@ -627,7 +627,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; @@ -756,7 +756,7 @@ static void rs780_internal_gfx_enable(struct device *dev) struct device *nb_dev = pcidev_on_root(0x0, 0); msr_t sysmem; -#if !IS_ENABLED(CONFIG_GFXUMA) +#if !CONFIG(GFXUMA) u32 FB_Start, FB_End; #endif @@ -799,7 +799,7 @@ static void rs780_internal_gfx_enable(struct device *dev) set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f); set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24); -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ struct device *k8_f1 = pcidev_on_root(0x18, 1); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index 6478ade955..fa9433b56b 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -204,7 +204,7 @@ static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev) /* Program Straps. */ romstrap2 = 1 << 26; // enables audio function -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) // bits 7-9: aperture size // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; |