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-rw-r--r--src/soc/amd/common/block/cpu/noncar/memmap.c4
-rw-r--r--src/soc/amd/common/fsp/fsp_report_resources.c2
-rw-r--r--src/soc/amd/stoneyridge/memmap.c2
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c2
-rw-r--r--src/soc/amd/stoneyridge/romstage.c2
-rw-r--r--src/soc/intel/baytrail/memmap.c4
-rw-r--r--src/soc/intel/broadwell/memmap.c4
-rw-r--r--src/soc/intel/common/block/systemagent/memmap.c2
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent.c3
-rw-r--r--src/soc/intel/denverton_ns/acpi.c2
-rw-r--r--src/soc/intel/denverton_ns/memmap.c4
-rw-r--r--src/soc/intel/denverton_ns/systemagent.c4
-rw-r--r--src/soc/intel/xeon_sp/memmap.c2
-rw-r--r--src/soc/intel/xeon_sp/uncore.c6
-rw-r--r--src/soc/sifive/fu740/chip.c2
15 files changed, 19 insertions, 26 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c
index 396260f176..0626205d23 100644
--- a/src/soc/amd/common/block/cpu/noncar/memmap.c
+++ b/src/soc/amd/common/block/cpu/noncar/memmap.c
@@ -42,7 +42,7 @@ static const struct memmap_early_dram *memmap_get_early_dram_usage(void)
/* report SoC memory map up to cbmem_top */
void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
- const uint32_t mem_usable = (uintptr_t)cbmem_top();
+ const uint32_t mem_usable = cbmem_top();
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
const uintptr_t early_reserved_dram_start = e->base;
const uintptr_t early_reserved_dram_end = e->base + e->size;
@@ -76,7 +76,7 @@ void smm_region(uintptr_t *start, size_t *size)
if (CONFIG(PLATFORM_USES_FSP2_0)) {
fsp_get_smm_region(start, size);
} else {
- *start = (uintptr_t)cbmem_top();
+ *start = cbmem_top();
*size = CONFIG_SMM_TSEG_SIZE;
}
diff --git a/src/soc/amd/common/fsp/fsp_report_resources.c b/src/soc/amd/common/fsp/fsp_report_resources.c
index 37049fb0df..d5f4a02943 100644
--- a/src/soc/amd/common/fsp/fsp_report_resources.c
+++ b/src/soc/amd/common/fsp/fsp_report_resources.c
@@ -9,7 +9,7 @@
void read_fsp_resources(struct device *dev, unsigned long *idx)
{
- const uint32_t mem_usable = (uintptr_t)cbmem_top();
+ const uint32_t mem_usable = cbmem_top();
const struct hob_header *hob_iterator;
const struct hob_resource *res;
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 32d6d96a5b..f99c884ccf 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -22,7 +22,7 @@ uintptr_t cbmem_top_chipset(void)
static uintptr_t smm_region_start(void)
{
- return (uintptr_t)cbmem_top();
+ return cbmem_top();
}
static size_t smm_region_size(void)
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index b51601ba02..9519713447 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -259,7 +259,7 @@ void domain_read_resources(struct device *dev)
{
uint64_t uma_base = get_uma_base();
uint32_t uma_size = get_uma_size();
- uint32_t mem_useable = (uintptr_t)cbmem_top();
+ uint32_t mem_useable = cbmem_top();
uint32_t tom = get_top_of_mem_below_4gb();
uint64_t high_tom = get_top_of_mem_above_4gb();
uint64_t high_mem_useable;
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index fc918f916f..900d1a668a 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -125,7 +125,7 @@ void __noreturn romstage_main(void)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 43b96c1c34..924853482a 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -29,13 +29,11 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram;
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 98c80165b0..770201baf0 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -47,13 +47,11 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram;
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
- top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 04ab735f46..ca9f680195 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -60,7 +60,7 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
/* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
- uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB);
+ const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB);
/*
* We need to make sure ramstage will be run cached. At this
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e8e75d7eb2..b2ae3cd0cd 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -188,10 +188,9 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
static void sa_add_dram_resources(struct device *dev, int *resource_count)
{
uint64_t sa_map_values[MAX_MAP_ENTRIES];
- uintptr_t top_of_ram;
int index = *resource_count;
- top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = cbmem_top();
/* 0 - > 0xa0000 */
ram_from_to(dev, index++, 0, 0xa0000);
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index afda045a42..207f4df31d 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -56,7 +56,7 @@ static const acpi_cstate_t cstate_map[] = {
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* Top of Low Memory (start of resource allocation) */
- gnvs->tolm = (uintptr_t)cbmem_top();
+ gnvs->tolm = cbmem_top();
/* MMIO Low/High & TSEG base and length */
gnvs->mmiob = (u32)get_top_of_low_memory();
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index f607d0f0df..957605964e 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -41,14 +41,12 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram;
-
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
- top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c
index 6c5149bb9f..e8bcba77fb 100644
--- a/src/soc/intel/denverton_ns/systemagent.c
+++ b/src/soc/intel/denverton_ns/systemagent.c
@@ -240,10 +240,10 @@ static void mc_add_dram_resources(struct device *dev)
reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
/* 0x100000 -> cbmem_top() */
- ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+ ram_from_to(dev, index++, 1 * MiB, cbmem_top());
/* cbmem_top() -> TSEG */
- mmio_from_to(dev, index++, (uintptr_t)cbmem_top(), mc_values[TSEG_REG]);
+ mmio_from_to(dev, index++, cbmem_top(), mc_values[TSEG_REG]);
/* TSEG -> TOLUD */
reserved_ram_from_to(dev, index++, mc_values[TSEG_REG], mc_values[TOLUD_REG]);
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index 8fe21e8430..bf4c13e4d3 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -30,7 +30,7 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = cbmem_top();
uintptr_t cbmem_base;
size_t cbmem_size;
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 96451913fd..2e5023d04e 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -139,7 +139,7 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
static void configure_dpr(struct device *dev)
{
- const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB;
+ const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB;
union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
/* The DPR lock bit has to be set sufficiently early. It looks like
@@ -245,7 +245,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
LOG_RESOURCE("low_ram", dev, res);
/* top_of_ram -> cbmem_top */
- res = ram_from_to(dev, index++, top_of_ram, (uintptr_t)cbmem_top());
+ res = ram_from_to(dev, index++, top_of_ram, cbmem_top());
LOG_RESOURCE("cbmem_ram", dev, res);
/* Mark TSEG/SMM region as reserved */
@@ -261,7 +261,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
* DPR has a 1M granularity so it's possible if cbmem_top is not 1M
* aligned that some memory does not get marked as assigned.
*/
- res = reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(),
+ res = reserved_ram_from_to(dev, index++, cbmem_top(),
(dpr.top - dpr.size) * MiB);
LOG_RESOURCE("unused_dram", dev, res);
diff --git a/src/soc/sifive/fu740/chip.c b/src/soc/sifive/fu740/chip.c
index cd5052be1a..7829624484 100644
--- a/src/soc/sifive/fu740/chip.c
+++ b/src/soc/sifive/fu740/chip.c
@@ -8,7 +8,7 @@
static void fu740_init(struct device *dev)
{
int index = 0;
- ram_from_to(dev, index++, FU740_DRAM, (uintptr_t)cbmem_top());
+ ram_from_to(dev, index++, FU740_DRAM, cbmem_top());
}
struct chip_operations soc_sifive_fu740_ops = {
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 23:26:52 +0000