diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/finalize.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 18 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 4 |
7 files changed, 50 insertions, 25 deletions
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 880e1e02ed..b31395d74a 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -80,23 +80,6 @@ static void sa_finalize(void) sa_lock_pam(); } -static void heci_finalize(void) -{ - unsigned int cse_dev[] = { - PCH_DEVFN_CSE, - PCH_DEVFN_CSE_2, - PCH_DEVFN_CSE_3, - PCH_DEVFN_CSE_4 - }; - - for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { - if (!is_cse_devfn_visible(cse_dev[i])) - continue; - - set_cse_device_state(cse_dev[i], DEV_IDLE); - } -} - static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -105,7 +88,7 @@ static void soc_finalize(void *unused) apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); - heci_finalize(); + heci_set_to_d0i3(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cd0abf7122..38e7491537 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -120,6 +120,10 @@ config CPU_SPECIFIC_OPTIONS config DISABLE_HECI1_AT_PRE_BOOT default y +config MAX_HECI_DEVICES + int + default 1 + config MAX_CPUS int default 4 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1a112bd68a..164159c702 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -1,10 +1,3 @@ -config SOC_INTEL_COMMON_BLOCK_CSE - bool - default n - help - Driver for communication with Converged Security Engine (CSE) - over Host Embedded Controller Interface (HECI) - config DISABLE_HECI1_AT_PRE_BOOT bool "Disable HECI1 at the end of boot" depends on SOC_INTEL_COMMON_BLOCK_CSE @@ -14,6 +7,17 @@ config DISABLE_HECI1_AT_PRE_BOOT Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload. +config MAX_HECI_DEVICES + int + default 6 + +config SOC_INTEL_COMMON_BLOCK_CSE + bool + default n + help + Driver for communication with Converged Security Engine (CSE) + over Host Embedded Controller Interface (HECI) + config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32f6d4f0c2..6dfe329fc4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -988,6 +988,26 @@ bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_st return true; } +void cse_set_to_d0i3(void) +{ + if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) + return; + + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); +} + +/* Function to set D0I3 for all HECI devices */ +void heci_set_to_d0i3(void) +{ + for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i)); + if (!is_cse_devfn_visible(dev)) + continue; + + set_cse_device_state(dev, DEV_IDLE); + } +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 15b7313b19..c2efab15fc 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -489,6 +489,12 @@ bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); +/* Set CSE device state to D0I3 */ +void cse_set_to_d0i3(void); + +/* Function sets D0I3 for all HECI devices */ +void heci_set_to_d0i3(void); + /* * SoC override API to make heci1 disable using PCR. * diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 31e733cba9..5addfb2c7e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -87,6 +87,10 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2015_BINDING +config MAX_HECI_DEVICES + int + default 5 + config MAX_CPUS int default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 0f025ac99e..32c2380216 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -75,6 +75,10 @@ config MAX_SOCKET int default 2 +config MAX_HECI_DEVICES + int + default 5 + # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS |