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-rw-r--r--src/soc/intel/xeon_sp/Makefile.inc1
-rw-r--r--src/soc/intel/xeon_sp/acpi.c (renamed from src/soc/intel/xeon_sp/skx/acpi.c)12
-rw-r--r--src/soc/intel/xeon_sp/cpx/Makefile.inc2
-rw-r--r--src/soc/intel/xeon_sp/cpx/acpi.c275
-rw-r--r--src/soc/intel/xeon_sp/skx/Makefile.inc1
5 files changed, 11 insertions, 280 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index f3e6839584..40a1020c5c 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -9,6 +9,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
postcar-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index 1e760d3ea7..acf030b450 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -78,9 +78,15 @@ unsigned long acpi_fill_madt(unsigned long current)
struct iiostack_resource stack_info = {0};
/* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
- int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
- int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
-
+#if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
+ const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
+ const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
+#endif
+
+#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
+ const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
+ const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
+#endif
/* Local APICs */
current = xeonsp_acpi_create_madt_lapics(current);
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc
index 79a83b5416..b2e653e50e 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc
@@ -12,7 +12,7 @@ romstage-y += romstage.c ddr.c
romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c soc_acpi.c
+ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
deleted file mode 100644
index 3066dda22e..0000000000
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <acpi/acpigen.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <assert.h>
-#include <cbmem.h>
-#include <cf9_reset.h>
-#include <console/console.h>
-#include <cpu/intel/turbo.h>
-#include <cpu/x86/smm.h>
-#include <device/pci.h>
-#include <intelblocks/acpi.h>
-#include <hob_iiouds.h>
-#include <hob_memmap.h>
-#include <soc/acpi.h>
-#include <soc/cpu.h>
-#include <soc/iomap.h>
-#include <soc/msr.h>
-#include <soc/nvs.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/soc_util.h>
-
-static int acpi_sci_irq(void)
-{
- int sci_irq = 9;
- uint32_t scis;
-
- scis = soc_read_sci_irq_select();
- scis &= SCI_IRQ_SEL;
- scis >>= SCI_IRQ_ADJUST;
-
- /* Determine how SCI is routed. */
- switch (scis) {
- case SCIS_IRQ9:
- case SCIS_IRQ10:
- case SCIS_IRQ11:
- sci_irq = scis - SCIS_IRQ9 + 9;
- break;
- case SCIS_IRQ20:
- case SCIS_IRQ21:
- case SCIS_IRQ22:
- case SCIS_IRQ23:
- sci_irq = scis - SCIS_IRQ20 + 20;
- break;
- default:
- printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
- sci_irq = 9;
- break;
- }
-
- printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
- return sci_irq;
-}
-
-static unsigned long acpi_madt_irq_overrides(unsigned long current)
-{
- int sci = acpi_sci_irq();
- uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
-
- flags |= soc_madt_sci_irq_polarity(sci);
-
- /* SCI */
- current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
-
- current +=
- acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0xff, 0x0d, 1);
-
- return current;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- int cur_index;
- struct iiostack_resource stack_info = {0};
-
- /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
- int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
- int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
-
- /* Local APICs */
- current = xeonsp_acpi_create_madt_lapics(current);
-
- cur_index = 0;
- get_iiostack_info(&stack_info);
-
- for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) {
- const STACK_RES *ri = &stack_info.res[stack];
- assert(cur_index < ARRAY_SIZE(ioapic_ids));
- assert(cur_index < ARRAY_SIZE(gsi_bases));
- int ioapic_id = ioapic_ids[cur_index];
- int gsi_base = gsi_bases[cur_index];
- printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, "
- "ioapic_base: 0x%x, gsi_base: 0x%x\n",
- stack, ioapic_id, ri->IoApicBase, gsi_base);
- current += acpi_create_madt_ioapic(
- (acpi_madt_ioapic_t *)current,
- ioapic_id, ri->IoApicBase, gsi_base);
- ++cur_index;
-
- /*
- * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
- * Add entry for PCH IOAPIC.
- */
- if (stack == 0) { /* PCH IOAPIC */
- assert(cur_index < ARRAY_SIZE(ioapic_ids));
- assert(cur_index < ARRAY_SIZE(gsi_bases));
- ioapic_id = ioapic_ids[cur_index];
- gsi_base = gsi_bases[cur_index];
- printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, "
- "ioapic_base: 0x%x, gsi_base: 0x%x\n",
- stack, ioapic_id,
- ri->IoApicBase + 0x1000, gsi_base);
- current += acpi_create_madt_ioapic(
- (acpi_madt_ioapic_t *)current,
- ioapic_id, ri->IoApicBase + 0x1000, gsi_base);
- ++cur_index;
- }
- }
-
- return acpi_madt_irq_overrides(current);
-}
-
-void acpi_fill_fadt(acpi_fadt_t *fadt)
-{
- const uint16_t pmbase = ACPI_BASE_ADDRESS;
-
- fadt->header.revision = get_acpi_table_revision(FADT);
-
- fadt->sci_int = acpi_sci_irq();
-
- if (permanent_smi_handler()) {
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- }
-
- fadt->pm1a_evt_blk = pmbase + PM1_STS;
- fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
-
- fadt->gpe0_blk = pmbase + GPE0_STS(0);
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
-
- /* GPE0 STS/EN pairs each 32 bits wide. */
- fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
-
- fadt->duty_offset = 1;
- fadt->day_alrm = 0xd;
-
- fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
- ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
- fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
- fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-
- fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
- fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-
- /*
- * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
- * The bit_width field intentionally overflows here.
- * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
- * seems to work fine on Linux 5.0 and Windows 10.
- */
- fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
- fadt->x_gpe0_blk.addrh = 0;
-}
-
-unsigned long southbridge_write_acpi_tables(const struct device *device,
- unsigned long current, struct acpi_rsdp *rsdp)
-{
- current = acpi_write_hpet(device, current, rsdp);
- current = (ALIGN(current, 16));
- printk(BIOS_DEBUG, "current = %lx\n", current);
- return current;
-}
-
-void southbridge_inject_dsdt(const struct device *device)
-{
- struct global_nvs *gnvs;
-
- gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
- if (!gnvs) {
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000);
- if (gnvs)
- memset(gnvs, 0, sizeof(*gnvs));
- }
-
- if (gnvs) {
- acpi_create_gnvs(gnvs);
- /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */
- // apm_control(APM_CNT_GNVS_UPDATE);
-
- /* Add it to DSDT. */
- printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs);
- acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (uint32_t)gnvs);
- acpigen_pop_len();
- }
-}
-
-int calculate_power(int tdp, int p1_ratio, int ratio)
-{
- u32 m;
- u32 power;
-
- /*
- * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
- *
- * Power = (ratio / p1_ratio) * m * tdp
- */
-
- m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
- m = (m * m) / 1000;
-
- power = ((ratio * 100000 / p1_ratio) / 100);
- power *= (m / 100) * (tdp / 1000);
- power /= 1000;
-
- return (int)power;
-}
-
-void generate_cpu_entries(const struct device *device)
-{
- int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
- int plen = 6;
- int total_threads = dev_count_cpu();
- int threads_per_package = get_threads_per_package();
- int numcpus = total_threads / threads_per_package;
-
- printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n",
- numcpus, threads_per_package, total_threads);
-
- for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
- for (core_id = 0; core_id < threads_per_package; core_id++) {
- if (core_id > 0) {
- pcontrol_blk = 0;
- plen = 0;
- }
-
- /* Generate processor \_PR.CPUx */
- acpigen_write_processor((cpu_id) * threads_per_package +
- core_id, pcontrol_blk, plen);
-
- /* NOTE: Intel idle driver doesn't use ACPI C-state tables */
-
- /* Soc specific power states generation */
- soc_power_states_generation(core_id, threads_per_package);
-
- acpigen_pop_len();
- }
- }
- /* PPKG is usually used for thermal management of the first and only package. */
- acpigen_write_processor_package("PPKG", 0, threads_per_package);
-
- /* Add a method to notify processor nodes */
- acpigen_write_processor_cnot(threads_per_package);
-}
diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc
index 1a7e3dd564..f042d36890 100644
--- a/src/soc/intel/xeon_sp/skx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/skx/Makefile.inc
@@ -23,7 +23,6 @@ ramstage-y += soc_acpi.c
ramstage-y += chip.c
ramstage-y += soc_util.c
ramstage-y += cpu.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += hob_display.c
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 22:19:00 +0000