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-rw-r--r--src/soc/intel/alderlake/chip.h7
-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a69e6455ee..2dae9cd202 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -441,6 +441,13 @@ struct soc_intel_alderlake_config {
uint8_t dmi_power_optimize_disable;
/*
+ * Used to communicate the power delivery design capability of the board. This
+ * value is an enum of the available power delivery segments that are defined in
+ * the Platform Design Guide.
+ */
+ uint8_t vr_power_delivery_design;
+
+ /*
* Enable(1)/Disable(0) CPU Replacement check.
* Default 0. Setting this to 1 to check CPU replacement.
*/
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd2c0bea0e..bd41480e75 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -748,6 +748,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
}
s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
+
+ s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design;
}
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,