diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/broadcom/cygnus/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/broadcom/cygnus/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/broadcom/cygnus/include/soc/memlayout.ld | 24 | ||||
| -rw-r--r-- | src/soc/broadcom/cygnus/verstage.c | 40 |
4 files changed, 55 insertions, 11 deletions
diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 2f5ad21bc3..158f61cf38 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -32,7 +32,6 @@ config SOC_BROADCOM_CYGNUS select HAVE_MONOTONIC_TIMER select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL - select RETURN_FROM_VERSTAGE if SOC_BROADCOM_CYGNUS diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index 244b11f46b..dea6cef2bc 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -24,6 +24,7 @@ bootblock-y += timer.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c +verstage-y += verstage.c verstage-y += i2c.c verstage-y += timer.c verstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 41d13fd7c5..c48c1bc221 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -28,14 +28,18 @@ SECTIONS RAMSTAGE(0x00200000, 128K) POSTRAM_CBFS_CACHE(0x01000000, 1M) - SRAM_START(0x61000000) - TTB(0x61000000, 16K) - BOOTBLOCK(0x61004000, 16K) - PRERAM_CBMEM_CONSOLE(0x61008000, 4K) - VBOOT2_WORK(0x61009000, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0x6100C000, 40K) - PRERAM_CBFS_CACHE(0x61016000, 1K) - CBFS_HEADER_OFFSET(0x61016800) - STACK(0x61017800, 4K) - SRAM_END(0x610040000) + SRAM_START(0x02000000) + REGION(reserved_for_system_status, 0x02000000, 4K, 4) + TTB(0x02004000, 16K) /* must be aligned to 16K */ + REGION(reserved_for_maskrom, 0x02009400, 4K, 4) + BOOTBLOCK(0x0200A440, 18K) + PRERAM_CBMEM_CONSOLE(0x0200F000, 4K) + VBOOT2_WORK(0x02010000, 16K) + VERSTAGE(0x02014000, 48K) + ROMSTAGE(0x02020000, 48K) + PRERAM_CBFS_CACHE(0x0202C000, 1K) + CBFS_HEADER_OFFSET(0x0202C800) + STACK(0x0202D000, 12K) + REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4) + SRAM_END(0x02040000) } diff --git a/src/soc/broadcom/cygnus/verstage.c b/src/soc/broadcom/cygnus/verstage.c new file mode 100644 index 0000000000..b5ec27ff73 --- /dev/null +++ b/src/soc/broadcom/cygnus/verstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/hlt.h> +#include <arch/stages.h> +#include <console/console.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void main(void) +{ + void *entry; + + console_init(); + exception_init(); + + entry = vboot2_verify_firmware(); + + if (entry != (void *)-1) + stage_exit(entry); + + hlt(); +} |