2 files changed, 29 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index dcf6ad6079..14358d8d58 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -20,10 +20,10 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 
+void romstage(void);
+void romstage_mainboard_init(void);
+
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
-void mainboard_init_tpm_i2c(void);
-void mainboard_init_ec_spi(void);
-void mainboard_init_ec_i2c(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index be431f7975..8d12dedaf1 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -32,7 +32,25 @@
 #include <soc/clock.h>
 #include <soc/romstage.h>
 
-void romstage(void);
+void __attribute__((weak)) romstage_mainboard_init(void)
+{
+	/* Default empty implementation. */
+}
+
+static void *load_ramstage(void)
+{
+	void *entry;
+	/*
+	 * This platform does not need to cache a loaded ramstage nor do we
+	 * go down this path on resume. Therefore, no romstage_handoff is
+	 * required.
+	 */
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+				CONFIG_CBFS_PREFIX "/ramstage");
+
+	return entry;
+}
+
 void romstage(void)
 {
 	void *entry;
@@ -67,12 +85,14 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
-	mainboard_init_tpm_i2c();
-	mainboard_init_ec_spi();
-	mainboard_init_ec_i2c();
+	romstage_mainboard_init();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				CONFIG_CBFS_PREFIX "/ramstage");
+	entry = load_ramstage();
+
+	if (entry == NULL) {
+		printk(BIOS_INFO, "T132 romstage: error loading ramstage\n");
+		clock_halt_avp();
+	}
 
 	cbmemc_reinit();